an017-msk5031 evaluation board user`s guide
Application Note 017
MSK5031 Evaluation Board User's Guide
By Bob Abel & Paul Musil, MSK; Revised 1/13/15
The MSK5031 is a 200KHz to 2.4MHz step-down switching regulator controller with a high
efficiency integrated switch. Synchronized or fixed high frequency switching coupled with
wide input and output voltage ranges allows the designer to minimize the required board
space for supporting components. With no load quiescent currents typically less than 100uA
efficiency remains high at light loads. The shutdown circuitry allows the user to further
reduce the input voltage supply current to less than 1uA. The MSK5031 is packaged in a
hermetically sealed 16 pin flatpack and is available with a straight or gull wing lead form.
The evaluation board provides a platform from which to evaluate new designs with ample
real estate to make changes and evaluate results. Evaluation early in the design phase
reduces the likelihood of excess ripple, instability, or other issues, from becoming a problem
at the application PCB level.
This application note is intended to be used in conjunction with the MSK5031 data sheet
and the LT3480 data sheet. Reference those documents for additional application
information and specifications.
Use the standard turret terminals to connect to your power supply and test equipment.
Connect a power supply across the Vin and GND1 terminals (see note 1). Connect the output
load between the VOUT and GND2 terminals. Use separate or Kelvin connections to
connect input and output monitoring equipment. When measuring output ripple voltage with
an oscilloscope probe, the wire from the probe to the ground clip will act as an antenna,
picking up excessive noise. For improved results, the test hook should be removed from the
tip of the probe. Minimize the ground lead effect by using a twisted pair or a short leaded
probe tip, and measure directly across the output capacitor. This reduces the erroneous noise
seen on the waveform.
Note 1: The input voltage range of the evaluation card is limited by the 20V rating of the
input capacitor. For input voltages greater than 20V—up to the maximum input voltage of
36V—the user must change the input capacitor to one with a sufficient voltage rating for the
application. Keep in mind that circuit stability may be affected, and should be reevaluated.
Output Voltage Programming
VOUT = VFB * (1+R1/R2)
R1 = R2 * (VOUT/VFB-1)
Given: VREF = 0.79V Typ.
Factory Configuration: R1 = 8.98K, R2 = 10.0K
VOUT = 0.79 * (1+8.98K/10.0K) = 1.499V
Switching Frequency Programming
The operating frequency is programmed by the value of RT. The value for RT will vary from
187k at 200 kHz to 8.66k at 2.4 MHz based on the application requirements. Higher
operating frequencies require smaller inductor and capacitor values, but are less efficient,
have lower maximum input voltages, and higher dropout voltages. The flexibility of the
frequency adjustment also helps avoid issues with noise sensitive frequency bands.
FSW(Max) is the maximum switching frequency
VD is the catch diode voltage drop (~0.5V)
VSW is the internal switch drop (~0.3V at 1A)
Typical efficiency vs. load current curves for 5.0V, 7.0V, and 12.0V input voltages are
shown in Figure 1.
V IN = 5V
V IN = 7V
V IN = 5V
Efficiency (%)
Efficiency (%)
V IN = 7V
V IN = 12V
V IN = 12V
V OUT = 1.5V
V OUT = 3.3V
Load Current (A)
Load Current (A)
Figure 1
Boost Pin and Boost Drive (BD)
The Boost pin provides drive voltage greater than VIN to the base of the power transistor.
Using a voltage greater than VIN ensures hard saturation of the power switch significantly
improving overall efficiency. Connect a capacitor between Boost and SW to store a charge.
A boost pin voltage of at least 2.3V, relative to the SW pin, is required throughout the ontime of the switch to guarantee that it remains saturated. Capacitor C2 and an internal boost
Schottky diode are used to generate a boost voltage that is higher than the input voltage. In
most cases a 0.22μF capacitor will work well. Figure 2 shows two ways to arrange the boost
(2a) VOUT < 3.0V
(2b) VOUT ≥ 3.0V
Figure 2. Boost/BD Pin Configurations
For outputs less than 3.0V, Figure 2a is best—BD tied to the input voltage. For outputs
greater than 3.0V figure 2b is best—BD tied to the output. Tying BD to VIN reduces the
maximum allowable input voltage to 30V. The circuit in Figure 2b is more efficient because
the BOOST pin current and BD pin quiescent current comes from a lower voltage source.
You must also be sure that the maximum voltage ratings of the BOOST and BD pins are not
exceeded. Efficiency is not affected by the capacitor value, but the capacitor should have an
ESR of less than 1Ω to ensure that it can be recharged fully under the worst-case condition
of minimum input voltage. Almost any type of film or ceramic capacitor will work fine.
For maximum efficiency, switch rise and fall times are made as short as possible. To prevent
radiation and high frequency resonance problems, proper layout of the components
connected to the switch node is essential.
Loop Stability
The evaluation board compensation consists of a 150pF capacitor in parallel with a series
RC consisting of a .015µF capacitor and a 18.2k resistor. This compensation was selected
for use with the default components on this evaluation board. New values may have to be
selected if different components are used. The values for loop compensation components
depend on parameters which are not always well controlled. These include inductor value
(±30% due to production tolerance, load current and ripple current variations), output
capacitance (±20% to ±50% due to production tolerance, temperature, aging and changes at
the load), output capacitor ESR (±200% due to production tolerance, temperature and
aging), and finally, DC input voltage and output load current. This makes it important to
check out the final design to ensure that it is stable and tolerant of all these variations.
Phase margin and gain margin are measures of stability in closed loop systems. Phase
margin indicates relative stability, and whether or not there is a tendency to oscillate during
its damped response to an input change such as a step function. Moreover, the phase margin
measures how much phase variation is needed at the gain crossover frequency to lose
stability. Gain margin is also an indication of relative stability. Gain margin measures how
much the gain of the system can increase before the system becomes unstable. Together,
these two numbers give an estimate of the safety margin for closed-loop stability. The
smaller the stability margins, the more likely the circuit will become unstable.
One method for measuring the stability of a feedback circuit is a network analyzer. Use an
isolation transformer / adapter to isolate the grounded output analyzer from the feedback
network. Remove the jumper across R4 and connect the output of the isolation transformer
across R4 using TP1 and TP2 terminals. Use 1M-ohm or greater probes to connect the
inputs of the analyzer to TP1 and TP2. Use GND3 for the ground reference for the network
analyzer inputs. Inject a swept frequency signal into the feedback loop, and plot the loop’s
gain and phase response between 1 kHz and 1 MHz. This provides a full picture of the
frequency response on both sides of the unity gain frequency (18 kHz in this case). Figure 2
illustrates typical results for the default configuration. The phase margin is the phase value
at the unity gain frequency, or about 81.6 Deg. The gain margin is the gain at the 0° phase
shift frequency, or approximately 32.4dB.
Phase Margin
Gain Margin
TR1: Mag(Gain)
TR2: Phase(Gain)
Figure 2
An alternate method to look at phase margin is to step the output load and monitor the
response of the system to the transient. Filtering may be required to remove switching
frequency components of the signal to make the small transients more visible. Any filter
used for this measurement must be carefully designed such that it will not alter the signal of
interest. A well behaved loop will settle back quickly and smoothly (Figure 3-C) and is
termed critically damped. A loop with low phase margin will ring as it settles (Figure 3-B)
under damped. A loop with high phase margin will take longer to achieve the setpoint
(Figure 3-A) over damped. The number of rings indicates the degree of stability, and the
frequency of the ringing shows the approximate unity-gain frequency of the loop. The
amplitude of the signal is not particularly important, as long as the amplitude is not so high
that the loop behaves nonlinearly. This method is easy to implement in labs not equipped
with network analyzers, but it does not indicate gain margin or evidence of conditional
stability. In these situations, a small shift in gain or phase caused by production tolerances or
temperature could cause instability even though the circuit functioned properly in
Figure 3-A
Figure 3-B
Figure 3-C
Figure 4 illustrates the typical results for a critically damped step load response between
500ma and 1.0A.
Figure 4 (Typical Step Response)
Current Sharing and Synchronization
There are several advantages to using a multiple switcher approach compared to a single
larger switcher. The inductor size is considerably reduced. Three 2A inductors store less
energy (LI2/2) than one 6A inductor so are far smaller. In addition, synchronizing three
converters 120° out of phase with each other reduces input and output ripple currents. This
reduces the ripple rating, size and cost of filter capacitors. If the SYNC pin is not used in the
application, tie it to ground. To synchronize switching to an external clock, apply a logiclevel signal to the SYNC pin. The recommended clock source is a square-wave with 20% to
80% duty cycle. The clock source rise and fall times must be faster than 1uS. The
Synchronization range is from 250KHz to 2.4MHz. The RT pin resistor must be set to a
frequency which is 20% below the lowest synchronized frequency. Reference the PGOOD
pin description. It is important to note that slope compensation is set by the RT value: When
the sync frequency is much higher than the one set by RT, the slope compensation will be
significantly reduced which may require a larger inductor value to prevent subharmonic
The PGOOD pin is an open collector output driven by a comparator with a 0.7V reference
and the FB pin as its input. PGOOD is a low until the FB pin is 86% of its final voltage. For
PGOOD to be valid VIN must be greater than 3.6V and the RUN/SS pin must be high. A
high level on the PGOOD pin also indicates the regulator is ready for switching frequency
synchronization at the SYNC pin.
The RUN/SS pin provides for shutting the regulator down and soft-start control. Less than
0.2V on the RUN/SS pin shuts down the regulator. If the RUN/SS pin is greater than 2.5V,
the regulator runs in normal mode. Soft-start control is achieved by adding a RC network on
the RUN/SS pin. The voltage ramp on the RUN/SS pin limits the current during startup to
minimize startup surge current and output overshoot. Tie RUN/SS to VIN if shutdown and
soft-start are not required.
Input/Output Capacitors
The input capacitor C2B is a AVX TAZ series 4.7µF tantalum capacitor and it was chosen
due to its low ESR, and effective low frequency filtering; see BOM for specific part number.
The input ripple current for a buck converter is high, typically IOUT/2. Tantalum capacitors
become resistive at higher frequencies, requiring careful ripple-rating selection to prevent
excessive heating. Measure the capacitor case rise above ambient in the worst case thermal
environment of the application, and if it exceeds 10°C, increase the voltage rating or lower
the ESR rating. Ceramic capacitors’ ESL (effective series inductance) tends to dominate
their ESR, making them less susceptible to ripple-induced heating. Ceramic capacitors filter
high frequencies well, and C1A and B were chosen for that purpose.
The output capacitors C5A and B are AVX TAZ series 47uF tantalum capacitors; see BOM
for specific part number. AVX TAZ series capacitors were chosen to provide a design
starting point using high reliability MIL-PFR-55365/4 qualified capacitors. Ceramic
capacitance is not recommended as the main output capacitor, since loop stability relies on a
resistive characteristic at higher frequencies to form a zero. At switching frequencies, ripple
voltage is more a function of ESR than of absolute capacitance value. If lower output ripple
voltage is required, reduce the ESR by choosing a different capacitor or placing more
capacitors in parallel. For very low ripple, an additional LC filter in the output may be a
more suitable solution. Re-compensation of the loop may be required if the output
capacitance is altered. The output contains very narrow voltage spikes caused by the
parasitic inductance of C5. Ceramic capacitors C6A and B remove these spikes on the demo
board. In application, trace impedance and local bypass capacitors will perform this
Catch Diode CR1 and L1
Use diodes designed for switching applications, with adequate current rating and fast turnon times, such as Schottky or ultrafast diodes. The parameters of interest are forward
voltage, maximum reverse voltage, reverse leakage current, average operating current, and
peak current. Lower forward voltage yields higher circuit efficiency and lowers power
dissipation in the diode. The reverse voltage rating must be greater than the input voltage.
Average diode current is always less than output current, but under a shorted output
condition, diode current can equal the switch current limit. If the application must withstand
this condition, the diode must be rated for maximum switch current. There are a number of
tradeoffs to consider when selecting an inductor for your application. The inductance value
determines the peak to peak ripple current under various operating conditions. A common
starting point for the peak to peak current ripple is 20% of the load current. The following
equation determines an inductor value based on desired ripple current and circuit
L = D*(Vin – Vout)/(fsw * Ipp)
= Duty cycle, approximately Vout/Vin
= Peak to peak ripple current, typically 0.2 * Iout DC
= Switching frequency in Hz
= Inductor value in Henries
Current Limitations
Peak current for a buck converter is limited by the maximum switch current rating. This
current rating is at least 3.5A for lower duty cycles and decreases linearly to 3.0A at a duty
cycle of 0.8 for the MSK5031.
Figure 5
Maximum output current is then reduced by one-half peak-to-peak inductor current.
IMAX = IP – (VOUT)(VIN – VOUT)/2(L)(f)(VIN)
Example given: VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, L = 4.7µH IP = 3.2A (Figure 5)
IMAX = 3.2A – (5V)(8V-5V) / 2(4.7µH)(800 kHz)(8V) = 2.95A
Figure 6
MSK5031 Evaluation Board Schematic
MSK5031 Evaluation Board Typical Performance
Output Voltage
Switching Frequency
Output Ripple Voltage
Line Regulation
Load Regulation
Gain Margin
Phase Margin
Vin = 5.0V, IOUT = 1.0A
Vin = 5.0V, IOUT = 1.0A
Vin = 5.0V, IOUT = 1.0A
5V ≤ Vin ≤ 15V, IOUT = 1.0A
Vin = 5.0V, IOUT = .5A to 2.0A
Vin = 5.0V, IOUT = 1.0A
Vin = 5.0V, IOUT = 2.0A
Vin = 5.0V, IOUT = 2.0A
1.5V (Factory Default)
MSK5031 Evaluation Board PCB Layout Artwork
Top Side
Bottom Side
MSK5031 Evaluation Board Bill Of Materials
Ref Des U1 C1A C1B C2A C2B C3 C4 C5A C5B C5C C5D C5E C5F C6A C6B C7 C8 C9 C10 C11 R1 R2 R3 R4 R5 R6 R7 CR1 Description Switching Regulator 1210 Ceramic cap 1.0uF 8050 Ceramic cap 0.1uF NP 47 uF Low ESR tantalum 1210 Ceramic cap .33uF 8050 Ceramic Cap 2000pF 47 uF Low ESR tantalum 47 uF Low ESR tantalum NP NP NP NP 1210 Ceramic cap 1.0uF 8050 Ceramic cap 0.1uF 8050 Ceramic Cap 150pF 8050 Ceramic Cap 0.015uF NP NP NP Resistor 8.98K, 1/8W Resistor 10.0K, 1/8W Resistor 18.2K, 1/8W Resistor 20Ω, 1/8W Resistor 40.2K, 1/8W Resistor 49.9K, 1/8W Resistor 49.9K, 1/8W Rectifier, 40V, 3A, Schottky
MSK AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX AVX Part Number MSK5031 12101C105K 08051C104K TAZH476K020L (CWR29JC476K) 12101C334K 08051C202K TAZF476K010L (CWR29FC476K) TAZF476K010L (CWR29FC476K) 12101C105K 08051C104K 08055A151K 08055C153K Fairchild SS34 Winding: 7 Turns, 24 AWG HAPT Core: Mag Inc 55268‐A2 Core L1 J1 J2 Inductor, 6.5uH MSK Jumper Wire, U1‐16 to VIN Jumper Wire, NP