M-986-2R2 MFC Transceivers INTEGRATED CIRCUITS DIVISION Features • Direct A-Law PCM digital input • 2.048 Mb/s clocking • Programmable forward/backward mode • Programmable compelled/direct control • Operates with standard codecs for analog interfacing • Microprocessor read/write interface • Binary or 2-of-6 data formats • Single- or dual-channel versions • 5 volt power Applications • Test equipment • Trunk adapters • Paging terminals • Traffic recorders • PBXs Pin Assignments Description The M-986-1R2 and -2R2 MFC Transceivers contain all the logic necessary to transmit and receive CCITT R2F (forward) and R2B (backward) multifrequency signals on one 40-pin integrated circuit (IC). M-9861R2 is a single-channel version; M-986-2R2 provides two channels. R1 single and dual multifrequency transceivers are also available as M-986-1R1 and 2R1. Operating with a 20.48 MHz crystal, the M-986 is capable of providing a direct digital interface to an Alaw-encoded PCM digital input. Each channel can be connected to an analog source using a coder-decoder (codec) as shown in the Block Diagram below. The M-986 can be configured by the customer to operate with the transmitter and receiver either coupled together or independently, allowing it to handle a compelled cycle automatically or via command from the host processor. For the R2 versions of the M-986, A-law is used for coding/decoding. The M-986 is configured and controlled through an integral coprocessor port. Ordering Information Part # Description M-986-1R2P M-986-1R2PL M-986-2R2P M-986-2R2PL 40-pin plastic DIP, Single Channel 44-pin PLCC, Single Channel 40-pin plastic DIP, Dual Channel 44-pin PLCC, Dual Channel Block Diagram DS-M-986-2R2_R04 www.ixysic.com 1 M-986-2R2 INTEGRATED CIRCUITS DIVISION Function Description The M-986 can be set up for various operating modes by writing two configuration bytes to the coprocessor port. Configuration Options External/Internal Codec Clock (ECLK): If external codec clocking is selected, an external clocking source provides an 8kHz transmit framing clock and an 8kHz receive framing clock. It also provides a serial bit clock with a frequency that is a multiple of 8 kHz between 2.496 MHz and 216 kHz for exchange of data via the serial ports. When internal codec clocking is selected, the M-986 provides an 8kHz framing clock and a 2.048 MHz serial bit clock. Binary/2 of 6 Input/Output (IOM): When the 2-of-6 input/output is selected, the M-986 encodes the received R2 MF tone pair into in a 6-bit format, where each bit represents one of the six possible frequencies. A logic high level indicates the presence of a frequency. The digital input to the M-986 that selects the transmitted R2 MF tone pair must also be coded in the 2-of-6 format. When binary input/output is selected, the M-986 encodes the received R2 MF tone pair into a 4 bit binary format. The digital input to the M-986 that selects the transmitted R2 MF tone pair must also be coded in a 4 bit binary format. Enable/Disable Channel (ENC): When a channel is disabled, the receiver does not process its codec input for R2 MF tones, and the transmitter does not respond to transmit commands. If a transmit command is given while the channel is enabled, the “tone off” command must be given before the channel is disabled. Disabling the channel does not automatically shut off the transmitter. When a channel is enabled, the receiver and transmitter for that channel function normally. End-of-Digit Indication (EOD): The end-of-digit indication option configures the M-986 to inform the host processor when the far end terminates transmission of the R2 MF tone it is sending. If this option is disabled, the host processor will not be notified when tone transmission terminates. Automatic Compelled/Manual Sequence Signaling (CMP): When manual mode is selected, R2 MF tone transmission is turned on and off only via command from the host processor. If the automatic mode is selected, the transmitter and receiver perform the compelled signaling handshake automatically. The specifics of operation are different for the forward and backward configurations. In forward mode, the transceiver can exist in two states, STATE 1 and STATE 2: • STATE 1: No backward signal detected. Transmitter under control of the host. • STATE 2: Backward signal detected. Transmitter off unconditionally. Configuration Bytes Configuration Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 ECLK IOM ENC1 EOD1 Bit 1 CMP1 Bit 0 FB1 ECLK Channels 1 & 2 1 = External codec clock; 0 = Internal codec clock IOM Channels 1 & 2 1 = Binary input/output; 0 = 2-of-6 input/output ENC1 Channel 1 1 = Enable channel; 0 = Disable channel EOD1 Channel 1 1 = Indicate end of digit; 0 = No end of digit indication CMP1 Channel 1 1 = Automatic Compelled mode; 0 = Manual mode FB1 Channel 1 1 = Forward mode (Tx forward frequencies and Rx backward frequencies) 0 = Backward mode (Tx backward frequencies and Rx forward frequencies) Configuration Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 1 0 0 ENC2 EOD2 CMP2 Bit 0 FB2 ENC2 Channel 2 1 = Enable channel; 0 = Disable channel EOD2 Channel 2 1 = Indicate end of digit; 0 = No end of digit indication CMP2 Channel 2 1 = Automatic Compelled mode; 0 = Manual mode FB2 Channel 2 1 = Forward mode (Tx forward frequencies and Rx backward frequencies) 0 = Backward mode(Tx backward frequencies and Rx forward frequencies) 2 www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION Both transceivers are in STATE 1. A compelled signaling sequence begins with the R2F host writing a transmit command byte to its transceiver via the coprocessor bus. The transceiver immediately begins transmitting the signal. A Transmit Tone Command written while the transceiver is in STATE 1 will be acted upon immediately. The transmitter is unconditionally disabled upon entry into STATE 2. If a transmit command is written to the transceiver while in STATE 2, that command will become pending. Upon entry into STATE 1, a pending transmit command is acted upon. In backward mode, the transceiver can exist in two states, STATE 1 and STATE 2: Automatic Compelled Mode Operation STATE 1: No forward signal detected. Transmitter off unconditionally. STATE 2: Forward signal detected. Transmitter transmits backward signal. A transmit tone command written while the transceiver is in STATE 2 will be acted upon immediately. The transmitter is unconditionally disabled upon entry into STATE 1. If a transmit command is written to the transceiver while in STATE 1, that command will become pending. Upon entry into STATE 2, a pending transmit command is acted upon. EXAMPLE: Assume that the transceivers at both ends of a link are configured in automatic compelled mode. 2 of 6 Coding Format Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transmit tone command 1 CHN F6 F5 F4 F3 F2 F1 Receive tone return 0 CHN F6 F5 F4 F3 F2 F1 CHN: 1 = channel 2; 0 = channel 1 R2 MF Frequencies: Bit name F6 F5 F4 Forward (Hz) 1980 1860 1740 Backward (Hz) 540 660 780 Bit name F3 F2 F1 Forward (Hz) 1620 1500 1380 Backward (Hz) 900 1020 1140 Binary Coding Format Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transmit tone command 1 CHN 0 0 A B C D Receive tone return 0 CHN 0 0 A B C D CHN: 1 = channel 2; 0 = channel 1 R2 MF Frequencies: ABCD Forward (Hz) Tone off 0000 0001 1380 & 1500 0010 1380 & 1620 0011 1500 & 1620 0100 1380 & 1740 0101 1500 & 1740 0110 1620 & 1740 0111 1380 & 1860 R04 Backward (Hz) Tone off 1140 & 1020 1140 & 900 1020 & 900 1140 & 780 1020 & 780 900 & 780 1140 & 660 ABCD 1000 1001 1010 1011 1100 1101 1110 1111 www.ixysic.com Forward (Hz) 1500 & 1860 1620 & 1860 1740 & 1860 1380 & 1980 1500 & 1980 1620 & 1980 1740 & 1980 1860 & 1980 Backward (Hz) 1020 & 660 900 & 660 780 & 660 1140 & 540 1020 & 540 900 & 540 780 & 540 660 & 540 3 M-986-2R2 INTEGRATED CIRCUITS DIVISION The R2B transceiver detects the signal, enters STATE 2, and outputs the received tone code to its host via the coprocessor port. If the R2B host had determined the next tone to transmit and written a transmit command to the transceiver prior to entry into STATE 2, the state transition will cause this tone to be transmitted. Otherwise, the R2B transmitter waits for a transmit tone command from the host, and starts transmitting a tone once the transmit tone command is received. The R2F transceiver detects the backward signal, enters STATE 2, and outputs the received tone code to its host. Entry into STATE 2 unconditionally disables the transmitter. The R2B transceiver detects the absence of signal, enters STATE 1, and informs the host with the end-oftone code if configured to do so. Entry into STATE 1 unconditionally disables the transmitter. Recieved Tone Detection When a tone is detected by the M-986, the TBLF output goes low, indicating reception of the tone to the host processor. The host processor can determine which tone was detected and which channel the tone was detected on by reading data from the M-986 coprocessor port. The M-986 will return a single byte indicating the tone received and the channel that the tone was received on.The format of the returned byte depends on whether the M-986 is configured for binary or 2-of-6 coding. Coprocessor Port Commands are written to the M-986 via the coprocessor port, and data indicating the received R2 MF tone is read from the coprocessor port. The R2F transceiver detects the absence of signal, enters STATE 1, and informs the host with the end-oftone code if configured to do so. If the R2F host had determined the next signal to transmit and written a transmit command to the transceiver prior to entry into STATE 1, the state transition will cause this signal to be transmitted. Otherwise, the transmitter remains silent until the next transmit command by its host. Writing to the Coprocessor Port: The following sequence describes writing a command to the M-986. Forward/Backward Frequencies (FB): When forward mode is selected, the R2F (forward) frequencies are transmitted and R2B (backward) frequencies are received. When backward mode is selected, R2B frequencies are transmitted and R2F frequencies are received. The R2F frequencies are 1380, 1500, 1620, 1740, 1860, and 1980 Hertz. The R2B frequencies are 540, 660, 780, 900, 1020, and 1140 Hz. (4) The RBLE signal transitions to a logic low level after the M-986 reads the data. This signals the host processor that the receive buffer is empty. Initial The configuration of the M-986 immediately after a reset will be as follows: · · · · · End-of-digit indication ON Forward mode ON Channel disabled 2-of-6 input/output External serial and serial frame clocks. (1) The WR signal is driven low by the host processor. (2) The RBLE (receive buffer latch empty) signal transitions to a logic high level. (3) Data is written from LD7-LD0 to the receive buffer latch (D7-D0) when the WR signal goes high. Note: The RBLE should be low before writing to the coprocessor. Reading the Coprocessor Port: The following sequence describes reading received tone information from the coprocessor port. (1) The TBLF (transmit buffer latch full) port pin on the M-986 goes low indicating the reception of a tone. (2) The host processor detects the low logic level on the TBLF pin either by polling a connected port pin or by an interrupt. (3) The host processor drives the RD signal low. Also, the M-986 will place 00 hex on the coprocessor port to indicate to the host processor that it is working. (4) The TBLF (transmit buffer latch full) signal transitions to a logic high level. Transmit Tone Command (5) Data is driven onto LD7-LD0 by the M-986 until the RD signal is driven high by the host processor. The transmit tone command allows the host processor to transmit any two of the 6 possible frequencies in the transmission mode the channel has been configured for (forward or backward). The format of the command depends on whether the M-986 is configured for binary format or 2-of-6 format. 4 Clock Characteristics and Timing Internal Clock Option: The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The crystal must be 20.48 MHz, fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF. www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION External Clock Option: An external frequency source can be used by injecting the frequency directly in X2/CLKIN, with X1 left unconnected. The external frequency injected must conform to the specifications listed in the External Frequency specification Table on page 7. Flammability/Reliability Specifications Reliability: Flammability: 185 FITS failures/billion hours Passes UL 94 V-0 tests Signal Description Signal DIP Pinout PLCC Pinout I/O/Z Description Note: Please see the following definitions: DIP = Dual In-line Package PLCC = Plastic Leaded Chip Carrier D15-D8 18-11 13-17, 19-21 I/O/Z D7-D0 19-26 22-28, 30 I/O/Z TBLF 40 44 O Transmit buffer latch full flag. RBLE 1 2 O Receive buffer latch empty flag HI/LO 2 3 I Latch byte select pin. Tie low. Unused. Leave open. Unused. Leave open. 8-bit coprocessor latch. BIO 9 10 I RD 32 36 I/O EXINT 5 6 I Unused. Leave open. Used by the external processor to read from the coprocessor latch by driving the RD line active (low), thus enabling the output latch to drive the latched data. When the data has been read, the external device must bring the RD line high. MC 3 4 I Microcomputer mode select pin. Tie low. MC/PM 27 31 I Coprocessor mode select pin. Tie low. RS 4 5 I WR 31 35 I/O XF 28 32 O Watchdog signal. Toggles at least once every 15 milliseconds when the processor is functioning properly. If the pin is not toggled at least once every 15 ms, the processor is lost and should be reset. CLKOUT 6 7 O System clock output (one-fourth crystal/CLKIN frequency, nominally 5.12 MHz). VCC 30 34 I 5V supply pin. VSS 10 1, 12, 18, 29 I Ground pin. X1 7 8 O Crystal output pin for internal oscillator. If an internal oscillator is not used, this pin should be left unconnected. X2/CLKIN 8 9 I Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for the external oscillator (CLKIN). DR1 & DR0 33 & 29 DX1 & DX0 36 & 35 R04 37, 33 40, 39 I O Reset input for initializing the device. When an active low is placed on RS pin for a minimum of five clock cycles, RD and WR are forced high, and the data bus (D7 through D0) goes to a high impedance state. The serial port clock and transmit outputs also go to the high impedance state. Used by the external processor to write data to the coprocessor port. To write data the external processor drives the WR line low, places data on the data bus, and then drives the WR line high to clock the data into the on-chip latch. Serial-port receive-channel inputs. 2.048 MHz serial data is received in the receive registers via these pins. DR0 = channel 1; DR1 = channel 2 Serial-port transmit-channel outputs. 2.048 MHz serial data is transmitted from the transmit registers on these pins.These outputs are in the high-impedance state when not transmitting. www.ixysic.com 5 M-986-2R2 INTEGRATED CIRCUITS DIVISION Signal Description (continued) Signal DIP Pinout PLCC Pinout I/O/Z Description FR 37 41 O 8 kHz internal serial-port framing output. If internal clocking is selected, serial-port transmit and receive operations occur simultaneously on an active (high) FR framing pulse. FSR 39 43 I 8 kHz external serial-port receive-framing input. If external clocking is selected, data is received via the receive pins (DR1 and DR0) on the active (low) FSR input. The falling edge of FSR initiates the receive process, and the rising edge causes the M-986 to process the data. FSX 38 42 I 8 kHz external serial-port transmit-framing input. If external clocking is enabled, data is transmitted on the transmit pins (DX1, DX0) on the active (low) input. The falling edge of FSX initiates the transmit process,and the rising edge causes the M-986 to internally load data for the next cycle. SCLK 34 38 I/O/Z 2.048 MHz serial-port clock. Master clock for transmitting and receiving serial-port data. Configured as an input in external clocking mode or output in internal clocking mode. Reset (RS) forces SCLK to the high-impedance state. Absolute Maximum Ratings Over Specified Temperature Supply voltage range, VCC Input voltage range Output voltage range Ambient air temperature range Storage temperature range Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability. -0.3 V to 7 V -0.3 V to 15 V -0.3 V to 15 V 0°C to 70°C -45°C to 150°C Serial Port Timing Parameter Min Max Units - - 70 ns DX bit 1 valid before SCLK falling edge 20 - - ns DX bit 2 valid before SCLK falling edge 20 - - ns td (CH-FR) Internal framing delay from SCLK rising edge td (DX1-CL) td (DX2-CL) Nom th ( DX) DX hold time after S CLK falling edge 244 - - ns tsu ( DR ) DR s etup time before S CLK falling edge 20 - - ns th ( DR ) DR hold time after S CLK falling edge 20 - - ns tc ( S CLK) S erial port clock cycle time 399 488. 28 4770 ns tf ( S CLK) S erial port clock fall time - - 30 ns tr ( S CLK) S erial port clock ris e time - - 30 ns tw (SCLKL) Serial port clock low-pulse duration* 220 244.14 2500 ns tw (SCLKH) Serial port clock high-pulse duration* 220 244.14 2500 ns tsu ( FS ) FS X/FS R s etup time before S CLK falling edge 100 - - ns * The duty cycle of the serial port clock must be within 45% to 55%. 6 www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION Electrical Characteristics/Temperature Range I CC Parameter Supply current VOH High-level output voltage VOL I OZ Low-level output voltage output current II Input current CI Input capacitance CO Data bus All others Output capacitance Data bus All others Tes t Condi ti ons f=20.5MHz, VCC=5.5V, TA = 0˚ to 70 ˚C I OH = MAX I OH = 20 µA I OL = MAX VCC = MAX VO = 2.4 V VO = 0.4 V Except CLKIN V I = VSS to VCC CLKI N f = 1 MHz, all other pins 0 V Mi n - Typ 50 Max 75 Uni t mA 2. 4 VCC -0.4 - 3 0. 3 25 15 25 10 0. 6 20 -20 ±20 ± 50 - V V V µA µA µA µA pF pF pF pF Min 48. 818 20 Nom 48. 828 5 - Max 48. 838 10 - Unit ns ns ns All inputs except CLKIN CLKI N Min 4. 75 2 3 Nom 5 0 - Max 5. 25 - Unit V V V V MC/PM 2. 2 - External Frequency Specifications t C ( MC) t r ( MC) t f ( MC) Parameter Mas ter clock cycle time R is e time mas ter clock input Puls e duration mas ter clock Recommended Operating Conditions VCC VSS VIH Parameter S upply voltage S upply voltage High-level input voltage VIL Low-level input voltage I OH I OL High-level output current ( all outputs ) Low-level output current ( all outputs ) All inputs except MC/MP MC/MP - - - - Min 25 30 25 80 60 - Nom - - V 0.8 0. 6 -300 2 V V µA mA Max 75 75 80 1 Unit ns ns ns ns ns ns ns ns ms Coprocessor Interface Timing td(R-A) td(W-A) ta(RD) th(RD) tsu(WR) th(WR) tw(RDL) tw(WRL) twr(RBLE) R04 Parameter R D low to TBLF high WR low to R BLE high R D low to data valid Data hold time after R D high Data s etup time prior to WR high Data hold time after WR high R D low-puls e duration WR low-puls e duration RBLE↑ to RBLE↓ www.ixysic.com 7 M-986-2R2 INTEGRATED CIRCUITS DIVISION Reset (RS) Timing tdis( R ) td12 td13 tsu( R ) tw(R ) Parameter Data bus dis able time after R S Delay time from RS↓ to high-impedance SCLK Delay time from RS↓ to high-impedance DX1, DX0 R es et ( R S ) s etup time prior to CLKOUT R S puls e duration Test Conditions R L = 825 C L = 100 pFΩ Min 50 977 Max 75 200 200 - Unit ns ns ns ns ns Min Nom Max Unit CLKOUT Timing Parameters Parameter tc(C) CLKOUT cycle time tr(C) CLKOUT ris e time tf(C) CLKOUT fall time Delay time CLKIN↑ to CLKOUT↓ td(MCC) Test Conditions 195. 27 195. 31 195. 35 ns R L = 825 - 10 - ns C L = 100 pFΩ 25 8 - 60 ns ns Test Conditions Min Typ Max Unit From nominal High/low Per component Between components -9. 26 - -8. 86 - ±1 ±0. 5 -8. 46 0 Hz dB dBm0 ms - - -46. 5 dBm0 Min Max Unit -35 -5 dBm0 Transmitter Characteristics Parameter FOS TW AS TS Phi Frequency offs et Twis t S ignal amplitude Time s kew Power due to harmonic distortion and intermodulation 300 to 3400 Hz Receiver Characteristics Parameter Test Conditions Ad Detect amplitude Per frequency And No-detect amplitude Per frequency -42 -35 dBm0 Fd Detect with frequency offs et From nominal ±10 - Hz TWd Detect with twis t Adjacent frequencies ±5 - dB Nonadjacent frequencies ±7 - dB TWnd No detect with twis t ±20 - dB T3r Third R 2F tone reject R elative to highes t level frequency -20 - dB FFd Detect R2B with R2F disturbing Above lowest level R2B tone (-12.5 dBm0 max.) 13.5 - dB FTnd No detect R2F with 2 out-of-band sine waves Any frequencies from 330 - 1150 Hz and 2130 - 3400 Hz -5 - dBm0 RT nd No detect R2B with 2 out-of-band sine waves -5 - dBm0 Ton Tone time R eject 7 - ms Tint Interrupted tone time R eject 7 - ms Tor Operate and release time - 80 8 Any frequencies from 1300-3400 Hz www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION External Framing Timing Diagrams Internal Framing Timing R04 www.ixysic.com 9 M-986-2R2 INTEGRATED CIRCUITS DIVISION Reset Timing Coprocessor Timing 10 www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION M-986 Dual Channel 4-Wire Interface Circuit R04 www.ixysic.com 11 M-986-2R2 INTEGRATED CIRCUITS DIVISION Manufacturing Information ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time All Versions 245ºC for 30 seconds Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a wash is used after solder reflow processes. Chlorine- or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 12 e3 www.ixysic.com R04 M-986-2R2 INTEGRATED CIRCUITS DIVISION Mechanical Dimensions Tolerances (inches) Metric (mm) Min Max Min Max A A1 B B1 C D E E1 e L .250 .015 .014 .022 .030 .070 .008 .015 1.98 2.095 .600 .625 .485 .580 .100 BSC .115 .200 (inches) A A1 A2 C D D1 Min .165 .090 .062 Tolerances Max .180 .20 .083 .020 min .685 .650 6.35 .39 .356 .558 .77 1.78 .204 .38 50.30 53.20 15.24 15.87 12.32 14.73 2.54 BSC 2.93 5.08 .695 .653 Metric (mm) Min Max 4.191 4.572 2.286 5.08 1.575 2.108 .508 min 17.399 17.653 16.510 16.662 Dimensions mm (inches) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-M-986-2R2-R04 ©Copyright 2013, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 1/10/2013 R04 www.ixysic.com 13