USE GAL DEVICES FOR NEW DESIGNS FINAL COM’L: H-7/10/15/20 IND: H-7/10/15/20 Lattice Semiconductor PALCE20RA10 Family 24-Pin Asynchronous EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ Low power at 100 mA ICC ■ TTL-level register preload for testability ■ As fast as 7.5 ns maximum propagation delay and 100 MHz fMAX (external) ■ Extensive third-party software and programmer support through FusionPLD partners ■ Individually programmable asynchronous clock, preset, reset, and enable ■ 24-pin PDIP and 28-pin PLCC packages save space ■ Registered or combinatorial outputs ■ 7.5 ns, 10 ns, and 15 ns versions utilize split leadframes for improved performance ■ Programmable polarity ■ Programmable replacement for high-speed CMOS or TTL logic GENERAL DESCRIPTION The PALCE20RA10 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. The PALCE20RA10 offers asynchronous clocking for each of the ten flip-flops in the device. The ten macrocells feature programmable clock, preset, reset, and enable, and all can operate asynchronously to other macrocells in the same device. The PALCE20RA10 also has flip-flop bypass, allowing any combination of registered and combinatorial outputs. very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The PALCE20RA10 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the Dedicated Inputs BLOCK DIAGRAM Output Enable Preload 10 I9 – I 0 Programmable AND Array 40 x 80 4 Enable 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro 4 3 Macro Preload I/O0 2-184 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 Publication# 15434 Rev. H Issue Date: February 1996 I/O9 15434H-1 Amendment /0 CONNECTION DIAGRAMS Top View NC I/O8 PL I/O9 I0 4 3 2 1 28 27 26 23 I/O9 I1 3 22 I/O8 I2 5 25 I/O7 I2 4 21 I/O7 I3 6 24 I/O6 I3 5 20 I/O6 I4 7 23 I/O5 I4 6 19 I/O5 NC 8 22 NC I5 7 18 I/O4 I5 9 21 I/O4 I6 8 17 I/O3 I6 10 20 I/O3 I7 9 16 I/O2 I7 11 19 I/O2 I8 10 15 I/O1 12 13 14 15 16 17 18 I9 11 14 I/O0 GND 12 13 OE 15434H-2 I/O0 2 I/O1 I0 OE VCC NC 24 GND 1 I9 PL I8 I1 VCC PLCC JEDEC SKINNYDIP 15434H-3 Note: Pin 1 is marked for orientation. PIN DESIGNATIONS GND = Ground I = Input I/O = Input/Output NC = No Connect OE = Output Enable PL = Preload VCC = Supply Voltage PALCE20RA10 Family 2-185 ORDERING INFORMATION Commercial and Industrial Products Programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 20 RA 10 H -7 J I FAMILY TYPE PAL = Programmable Array Logic OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (–40°C to +85°C) TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF ARRAY INPUTS PACKAGE TYPE P = 24-Pin 300 mil Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) OUTPUT TYPE RA = Registered Asynchronous NUMBER OF OUTPUTS POWER H = Half Power (ICC = 100 mA) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD Valid Combinations PALCE20RA10H-7 PALCE20RA10H-10 PALCE20RA10H-15 PALCE20RA10H-20 2-186 JC, JI PC, JC, PI, JI Valid Combinations Valid Combinations lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE20RA10H-7/10/15/20 (Com’l, Ind) Commercial and Industrial Products PL OE 1 AP D Q PL P AR S0 Output 0 15434H-5 Figure 1. PALCE20RA10 Macrocell FUNCTIONAL DESCRIPTION Programmable Clock The PALCE20RA10 has ten dedicated input lines and ten programmable I/O macrocells. The Registered Asynchronous (RA) macrocell is shown in Figure 1. PL serves as global register preload and OE serves as global output enable. Programmable output polarity is available to provide user-programmable output polarity for each individual macrocell. The clock input to each flip-flop comes from the programmable array, allowing any flip-flop to be clocked independently if desired. The programmable functions in the PALCE20RA10 are automatically configured from the user’s design specification, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. AP D Q AR Registered/Active Low Combinatorial/Active Low Programmable Preset and Reset In each macrocell, two product lines are dedicated to asynchronous preset and asynchronous reset. If the preset product line is HIGH, the Q output of the register becomes a logic 1 and the output pin will be a logic 0. If the reset product line is HIGH, the Q output of the register becomes a logic 0 and the output pin will be logic 1. The operation of the programmable preset and reset overrides the clock. AP D Q AR Registered/Active High Combinatorial/Registered Outputs Combinatorial/Active High 15434H-6 If both the preset and reset product lines are HIGH, the flip-flop is bypassed and the output becomes combinatorial. Otherwise, the output is from the register. Each output can be configured to be combinatorial or registered. Figure 2. Macrocell Configurations PALCE20RA10 Family 2-187 Three-State Outputs Output Register Preload The devices provide a product term dedicated to local output control. There is also a global output control pin. The output is enabled if both the global output control pin is LOW and the local output control product term is HIGH. If the global output control pin is HIGH, all outputs will be disabled. If the local output control product term is LOW, then that output will be disabled. The output registers on the PALCE20RA10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Register preload is controlled by a TTL-level signal, making it a convenient board-level initialization function. Details on output register preload can be found on page 16. Security Bit A security bit is also provided to prevent unauthorized copying of PAL device patterns. Once the bit is programmed, the circuitry enabling verification is permanently disabled, and the array will read as if every bit is programmed. With verification not operating, it is impossible to simply copy the PAL device pattern on a PAL device programmer. The security bit can only be erased in conjunction with the entire pattern. Programmable Polarity The outputs can be programmed either active-LOW or active-HIGH. This is represented by the Exclusive-OR gate shown in the PALCE20RA10 logic diagram. When the output polarity bit is programmed, the lower input to the Exclusive-OR gate is HIGH, so the output is activeHIGH. Similarly when the output polarity bit is unprogrammed, the output is active-LOW. The programmable output polarity feature allows the user a higher degree of flexibility when writing equations. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Registered outputs of the PALCE20RA10 will be HIGH due to the output inverter. The state of combinatorial outputs will be a function of the logic. Details on power-up reset can be found on page 16. Quality and Testability The PALCE20RA10 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Programming and Erasing Technology The PALCE20RA10 can be programmed on standard logic programmers. Approved programmers are listed at the end of this databook. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. The high-speed PALCE20RA10 is fabricated with Our advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. 2-188 PALCE20RA10 Family LOGIC DIAGRAM SKINNYDIP (PLCC JEDEC) Pinouts 1 (2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 24 Vcc (28) 0 1 2 3 1 4 5 D 6 7 2 (3) AP PL Q 0 23 (27) P AR 8 9 10 11 12 1 13 14 D PL 15 3 (4) AP Q 22 (26) P AR 16 17 18 19 1 20 21 D 22 23 4 (5) 0 AP PL Q 0 21 (25) P AR 24 25 26 27 28 1 29 30 D PL 31 5 (6) AP Q 20 (24) AR 32 33 34 35 1 36 37 D 38 39 6 (7) 0 P AP PL Q 0 19 (23) P AR 40 41 42 43 44 1 45 46 D PL 47 7 (9) AP Q 0 18 (21) P AR 48 49 50 51 1 52 53 D 54 55 AP PL Q 0 17 (20) P AR 8 (10) 56 57 58 59 60 1 61 62 D PL 63 9 (11) AP Q 0 16 (19) P AR 64 65 66 67 68 69 70 71 1 D AP PL Q 0 15 (18) P AR 10 (12) 72 73 74 75 76 1 77 78 D PL 79 11 (13) AP Q 0 14 (17) P AR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 13 (16) 12 (14) 15434H-7 PALCE20RA10 Family 2-189 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . –40°C to +85°C Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Latchup Current (TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VIN = VIH or VIL VCC = Min 2.4 VOL Output LOW Voltage IOL = 16 mA VIN = VIH or VIL VCC = Min VIH Input HIGH Voltage Voltage for all Inputs Guaranteed Input Logical HIGH (Note 1) VIL Input LOW Voltage Voltage for all Inputs Guaranteed Input Logical LOW (Note 1) IIH Input HIGH Leakage Current VIN = 5.5 V, VCC = Max IIL Input LOW Leakage Current VIN = 0 V, VCC = Max IOZH Off-State Output Leakage Current HIGH VOUT = 5.5 V, VCC = Max VIN = VIL or VIH (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) ICC (Static) Commercial Supply Current ICC (Static) Industrial Supply Current Max Unit V 0.4 2.0 V V 0.8 V 10 µA –100 µA 10 µA –100 µA –130 mA VIN = 0 V, Outputs Open -7/10/15 -20 IOUT = 0 mA, VCC = Max, (Note 4) 100 90 mA mA VIN = 0 V, Outputs Open -7/10/15 -20 IOUT = 0 mA, VCC = Max, (Note 4) 115 100 mA mA –30 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed under worst case test conditions. 2-190 PALCE20RA10H-7/10/15/20 (Com’l, Ind) CAPACITANCE (Note 1) Parameter Symbol CIN Parameter Description Input Capacitance Test Conditions Inputs Typ VIN = 2.0 V OE COUT Output Capacitance VOUT = 2.0 V VCC = 5.0 V 5 TA = +25°C 9 f = 1 MHz 8 Unit pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) -7 Min (3) Max Parameter Symbol Parameter Description tPD Input or Feedback to Combinatorial Output tS Setup Time from Input, Feedback or SP to Clock 2.5 tH Hold Time -10 Min (3) Max 7.5 10 3 2.5 -15 Min (3) Max 15 4 3 -20 Min (3) Max Unit 20 ns 4 4 ns 4 ns tCO Clock to Output or Feedback 7.5 10 15 20 ns tAP Asynchronous Preset to Registered Output 7.5 10 15 20 ns tAPW Asynchronous Preset Width (Note 3) tAPR Asynchronous Preset Recovery Time (Note 3) tAR Asynchronous Reset to Registered Output tARW Asynchronous Reset Width (Note 3) tARR Asynchronous Reset Recovery Time (Note 3) tWL Clock Width tWH fMAX Maximum Frequency (Note 4) 5 8 10 12 ns 5 7 10 12 ns 7.5 10 15 20 ns 5 8 10 5 7 12 10 ns 12 ns LOW 4 5 8 12 ns HIGH 4 5 8 12 ns 100 76.9 52.6 37 MHz 125 100 62.5 41.6 MHz External Feedback 1/(tS + tCO) No Feedback 1/(tWH + tWL) tPZX OE to Output Enable 5 8 10 15 ns tPXZ OE to Output Disable 5 8 10 15 ns tEA Input to Output Enable Using Product Term Control 7.5 10 15 20 ns tER Input to Output Disable Using Product Term Control 7.5 10 15 20 ns tWP Preload Pulse Duration 5 7 10 15 ns tSP Preload Setup Time 5 7 10 15 ns tHP Preload Hold Time 5 7 10 15 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where the frequency may be affected. PALCE20RA10H-7/10/15/20 (Com’l, Ind) 2-191 SWITCHING WAVEFORMS Input or Feedback Input or Feedback VT VT tS tPD tH Clock Combinatorial Output VT VT tCO 15434H-8 Registered Output VT 15434H-9 Combinatorial Output Registered Output tAPW Input Asserting Asynchronous Preset tARW Input Asserting Asynchronous Reset VT tAP VT tAR Registered Output VT Registered Output VT tAPR Clock tARR VT 15434H-10 Clock VT 15434H-11 Asynchronous Preset Asynchronous Reset tWH VT Clock tWL 15434G-12 Clock Width Input or Feedback tER Output OE VT tPXZ tEA VOH - 0.5V VOL + 0.5V VT Output 15434H-13 Input to Output Disable/Enable Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V 3. Input rise and fall times 2 ns – 5 ns typical. 2-192 VT PALCE20RA10 Family tPZX VOH - 0.5V VT VOL + 0.5V 15434H-14 OE to Output Disable/Enable KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 15434H-15 Commercial and Industrial Specification S1 CL R1 R2 Measured Output Value All except H-20: All except H-20: 1.5 V tPD, tCO Closed tPZX, tEA Z → H: Open Z → L: Closed 50 pF 300 Ω 300 Ω 1.5 V tPXZ, tER H → Z: Open 5 pF H-20: 560 Ω H-20: 1.1 kΩ H → Z: VOH – 0.5 V L → Z: Closed L → Z: VOL + 0.5 V PALCE20RA10 Family 2-193 TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 150 80 70 PALCE20RA10 Family 60 50 ICC (mA) 40 30 20 10 0 0 1 5 10 15 20 25 Frequency (MHz) 30 35 40 50 15434H-16 ICC vs. Frequency The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. 2-194 PALCE20RA10 Family parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. ENDURANCE CHARACTERISTICS The PALCE20RA10 is manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol tDR N Parameter Test Conditions Min Pattern Data Retention Time Max Storage Temperature Min Reprogramming Cycles Min Unit 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles pull-down resistors be used if the condition of a floating bus line exists. Robustness The PALCE20RA10 has been designed with some unique features that make it extremely robust, even when operating in high-speed design environments. Pull-up resistors on the inputs and I/Os cause unconnected pins to default to the HIGH state. Please note that these pull-up resistors are only for this purpose, and do not provide enough current to sufficiently pull a bus line high. We recommend that external pull-up or Input-clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns. INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC VCC > 50 kΩ ESD Protection and Clamping Programming Pins Only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC VCC > 50 kΩ Provides ESD Protection and Clamping Preload Circuitry Feedback Input 15434H-17 Typical Output PALCE20RA10 Family 2-195 POWER-UP RESET and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: The PALCE20RA10 has been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset Parameter Symbol The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Max Unit tPR Power-Up Reset Time 1000 ns tS Input or Feedback Setup Time See Switching Characteristics Clock Width LOW tWL VCC 4V Power tPR Registered Output tS Clock tWL 15434H-18 Power-Up Reset Waveform OUTPUT REGISTER PRELOAD 5. Enable the output registers. The preload function allows the register to be loaded from the output pins. This feature aids functional testing of sequential designs by allowing direct setting of output states. The procedure for preloading follows. 6. Verify VOL/VOH at all registered output pins. Note that because of the output inverter, a register that has been preloaded HIGH will provide a LOW at the output. Also note that because there is an inverter on the register preload input, the level presented on the register preload input at the time of preload will be present on the register output pin following the preload sequence e.g., a low on the register pin at the time of preload will result in a low on that pin after preload. 1. Disable output registers. 2. Apply either VIH or VIL to all registered outputs. Leave combinatorial outputs floating. 3. Pulse PL from VIH to VIL to VIH. 4. Remove VIL/VIH from all registered output pins. Output Disable/Enable tER tEA Register Outputs tS tHP Pin 1 Preload Clock tWL Output Register Preload Waveform 2-196 PALCE20RA10 Family 15434H-19