PALCE26V12 Family Data Sheet

USE GAL DEVICES FOR NEW DESIGNS
FINAL
COM’L: H-7/10/15/20
IND: H-10/15/20
Lattice Semiconductor
PALCE26V12 Family
28-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
■ 28-pin versatile PAL programmable logic
device architecture
■ Electrically erasable CMOS technology
provides half power (only 115 mA) at high
speed (7.5 ns propagation delay)
■ Two clock inputs for independent functions
■ Global asynchronous reset and synchronous
preset for initialization
■ Register preload for testability and built-in
register reset on power-up
■ 14 dedicated inputs and 12 input/output
macrocells for architectural flexibility
■ Space-efficient 28-pin SKINNYDIP and PLCC
packages
■ Macrocells can be registered or combinatorial,
and active high or active low
■ Center VCC and GND pins to improve signal
characteristics
■ Varied product term distribution allows up to
16 product terms per output
■ Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE26V12 is a 28-pin version of the popular
PAL22V10 architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, the
PALCE26V12 offers many unique advantages.
Device logic is automatically configured according to
the user’s design specification. Design is simplified by
design software, allowing automatic creation of a
programming file based on Boolean or state equations.
The software can also be used to verify the design and
can provide test vectors for the programmed device.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be programmed as registered or combinatorial, active high or
active low, with registered I/O possible. The flip-flop can
be clocked by one of two clock inputs. The output
configuration is determined by four bits controlling three
multiplexers in each macrocell.
The PALCE26V12 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced
to sum-of-products form, taking advantage of the
very wide input gates available in PAL devices. The
functions are programmed into the device through
electrically-erasable floating-gate cells in the AND logic
array and the macrocells. In the unprogrammed state,
all AND product terms float HIGH. If both true and
complement of any input are connected, the term will be
permanently LOW.
2-306
Publication# 16072 Rev. E
Issue Date: February 1996
Amendment /0
BLOCK DIAGRAM
I
CLK/I
2
12
PROGRAMMABLE
AND ARRAY
(52x150)
SYNC.
PRESET
8
8
10
12
14
16
ASYNC.
RESET
16
14
12
10
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
8
8
MACRO
MACRO
I/O 10
I/O 11
16072E-1
CONNECTION DIAGRAMS
Top View
DIP
I/O11
I2
3
26
I/O10
CLK2/I3
4
25
I/O9
4
3
2
1 28 27 26
I/O10
27
I/O11
2
I13
I1
CLK1/I0
I13
I1
28
I2
1
CLK2/I3
CLK1/I0
PLCC
I4
5
24
I/O8
I4
I5
6
23
I/O7
I5
6
24
I/O8
VCC
7
22
I/O6
VCC
7
23
I/O7
I6
8
21
GND
I6
8
22
I/O6
I7
9
20
I/O5
I7
9
21
GND
I8
10
19
I/O4
10
20
11
I8
I/O5
I9
18
I/O3
I10
12
17
I/O2
I9
11
19
I/O4
I11
13
16
I/O1
I12
14
15
I/O0
Note:
Pin 1 is marked for orientation.
5
25
I/O9
16072E-2
I/O3
I/O2
I/O1
I/O0
I12
I11
I10
12 13 14 15 16 17 18
16072E-3
PIN DESCRIPTION
CLK
GND
I
I/O
VCC
=
=
=
=
=
Clock
Ground
Input
Input/Output
Supply Voltage
PALCE26V12 Family
2–307
ORDERING INFORMATION
Commercial and Industrial Products
Commercial and industrial programmable logic products are available with several ordering options. The order
number (Valid Combination) is formed by a combination of:
PAL
CE 26 V 12 H
-7
P C /4
FAMILY TYPE
PAL = Programmable Array Logic
OPTIONAL PROCESSING
Blank = Standard Processing
TECHNOLOGY
CE = CMOS Electrically Erasable
PROGRAMMING DESIGNATOR
/4 = First Revision
(May require programmer
update)
NUMBER OF
ARRAY INPUTS
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
I = Industrial (–40°C to +85°C)
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
PACKAGE TYPE
P = 28-Pin 300 mil Plastic
SKINNYDIP (PD3028)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
POWER
H= Half Power (115 mA ICC)
SPEED
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
Valid Combinations
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
PALCE26V12H-20
2–308
JC
PC, JC, PI, JI
/4
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult your local sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
PALCE26V12H-7/10/15/20 (Com’l), H-10/15/20 (Ind)
FUNCTIONAL DESCRIPTION
OE
The PALCE26V12 has fourteen dedicated input lines,
two of which can be used as clock inputs. Unused inputs
should be tied directly to ground or VCC. Buffers for
device inputs and feedbacks have both true and
complementary outputs to provide user-selectable
signal polarity. The inputs drive a programmable AND
logic array, which feeds a fixed OR logic array.
AR CLK 1
P1
Pn
CLK 2
0
1
1
AR
D Q
0
0
Q
SP
0
1
1
0
n = 8,8,10,12,14,16
1
S2
S0
S1
0
SP
1
The OR gates feed the twelve I/O macrocells (see
Figure 1). The macrocell allows one of eight potential
output configurations; registered or combinatorial, active high or active low, with register or I/O pin feedback
(see Figure 2). In addition, registered configurations can
be clocked by either of the two clock inputs.
The configuration choice is made according to the
user’s design specification and corresponding programming of the configuration bits S0–S3 (see Table 1).
Multiplexer controls initially float to VCC (1) through a
programmable cell, selecting the “1” path through the
multiplexer. Programming the cell connects the control
line to GND (0), selecting the “0” path.
Table 1. Macrocell Configuration Table
S3
S1
S0
1
0
0
Output Configuration
Registered Output and Feedback,
Active Low
1
0
1
Registered Output and Feedback,
Active High
1
1
0
Combinatorial I/O, Active Low
1
1
1
Combinatorial I/O, Active High
0
0
0
Registered I/O, Active Low
0
0
1
Registered I/O, Active High
0
1
0
Combinatorial Output, Registered
Feedback, Active Low
0
1
1
Combinatorial Output, Registered
Feedback, Active High
1 = Unprogrammed EE bit
0 = Programmed EE bit
S2
S3*
* When S 3 = 1 (unprogrammed) the feedback is selected by S 1.
When S 3 = 0 (programmed), the feedback is the opposite of
that selected by S 1.
16072E-4
Figure 1. PALCE26V12 Macrocell
Registered or Combinatorial
Each macrocell of the PALCE26V12 includes a D-type
flip-flop for data storage and synchronization. The
flip-flop is loaded on the LOW-to-HIGH edge of the
selected clock input. Any macrocell can be configured
as combinatorial by selecting a multiplexer path that
bypasses the flip-flop. Bypass is controlled by bit S1.
Programmable Clock
The clock input for any flip-flop can be selected to be
from either pin 1 or pin 4. A 2:1 multiplexer controlled by
bit S2 determines the clock input.
Programmable Feedback
A 2:1 multiplexer allows the user to determine whether
the macrocell feedback comes from the flip-flop or
from the I/O pin, independent of whether the output is
registered or combinatorial. Thus, registered outputs
may have internal register feedback for higher speed
(fMAX internal), or I/O feedback for use of the pin as a
direct input (fMAX external). Combinatorial outputs may
have I/O feedback, either for use of the signal in other
equations or for use as another direct input, or register
feedback.
Clock Input
1
CLK1/I0
0
CLK2/I3
PALCE26V12 Family
2–309
The feedback multiplexer is controlled by the same bit
(S1) that controls whether the output is registered or
combinatorial, as on the 22V10, with an additional
control bit (S3) that allows the alternative feedback path
to be selected. When S3 = 1, S1 selects register
feedback for registered outputs (S1 = 0) and I/O
feedback for combinatorial outputs (S1 = 1). When S3 =
0, the opposite is selected: I/O feedback for registered
outputs and register feedback for combinatorial outputs.
Power-Up Reset
Programmable Enable and I/O
The register on the PALCE26V12 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows
direct loading of arbitrary states, thereby making it
unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions
from illegal states can be verified by loading illegal
states and observing proper recovery.
Each macrocell has a three-state output buffer controlled by an individual product term. Enable and disable
can be a function of any combination of device inputs or
feedback. The macrocell provides a bidirectional I/O pin
if I/O feedback is selected, and may be configured as a
dedicated input if the buffer is always disabled. This is
accomplished by connecting all inputs to the enable
term, forcing the AND of the complemented inputs to be
always LOW. To permanently enable the outputs, all
inputs are left disconnected from the term (the
unprogrammed state).
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and
combinatorial outputs. Selection is automatic, based on
the design specification and pin definitions. If the pin
definition and output equation have the same polarity,
the output is programmed to be active high.
Preset/Reset
For initialization, the PALCE26V12 has additional
Preset and Reset product terms. These terms are
connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the
output registers will be loaded with a HIGH or the next
LOW-to-HIGH clock transition. When the Asynchronous
Reset (AR) product term is asserted high, the output
registers will be immediately loaded with a LOW
independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
2–310
All flip-flops power up to a logic LOW for predictable
system initialization. Outputs of the PALCE26V12 will
be HIGH or LOW depending on whether the output is
active low or active high, respectively. The VCC rise must
be monotonic, and the reset delay time is 1000 ns
maximum.
Register Preload
Security Bit
After programming and verification, a PALCE26V12
design can be secured by programming the security bit.
Once programmed, this bit defeats readback of the
internal programmed pattern by a device programmer,
securing proprietary designs from competitors. Programming the security bit disables preload, and the
array will read as if every bit is disconnected. The
security bit can only be erased in conjunction with
erasure of the entire pattern.
Programming and Erasing
The PALCE26V12 can be programmed on standard
logic programmers. It also may be erased to reset a
previously configured device back to its virgin state.
Erasure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE26V12 offers a very high level of built-in
quality. The erasability of the device provides a means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest
programming yields and post-programming functional
yields in the industry.
Technology
The high-speed PALCE26V12 is fabricated with our
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PALCE26V12 Family
D
CLK
AR
Q
D
CLK
SP Q
CLK
AR
Q
SP Q
Registered Active-High Output,
Register Feedback
Registered Active-Low Output,
Register Feedback
D
AR
Q
D
CLK
SP Q
Registered Active-Low I/O
AR
Q
SP Q
Registered Active-High I/O
Registered Outputs
Combinatorial Active-Low I/O
D
CLK
AR
Combinatorial Active-High I/O
Q
D
CLK
SP Q
Combinatorial Active-Low Output,
Register Feedback
AR
Q
SP Q
Combinatorial Active-High Output,
Register Feedback
Combinatorial Outputs
16072E-5
Figure 2. PALCE26V12 Macrocell Configuration Options
PALCE26V12 Family
2–311
LOGIC DIAGRAM
PALCE26V12
0
4
8
12
16
20
24
28
32
36
40
44
48
ASYNCH.
RESET
0
28
I 13
1
1
CLK 1 /I 0
10
D
AR
1
9
11
Q
00
Q
01
SP
0
27
I/O 11
S0
S2
S1
0
2
I1
R 11
1
S3 *
10
10
11
D
AR
01
1
Q
0
18
26
I/O 10
00
Q
SP
S0
S2
0
3
I2
R
S1
10
1
S3 *
19
D ARQ
10
11
00
Q
01
1
0
29
SP
S0
S2
4
0
1
CLK 2 /I 3
25
I/O 9
S1
R9
S3*
30
10
11
D ARQ
1
0
SP
S0
S2
42
0
1
5
I4
24
I/O 8
00
01
Q
S1
R8
S3 *
43
10
11
00
01
D ARQ
1
0
SP
Q
S0
S2
57
0
1
6
I5
23
I/O 7
S1
R7
S3 *
58
10
11
00
01
D ARQ
1
0
Q
SP
S0
S1
S2
74
8
I6
0
1
0
4
8
12
16
20
24
28
32
36
40
44
48
* When S 3 = 1 (unprogrammed) the feedback is selected by S1.
When S 3 = 0 (programmed), the feedback is the opposite of
that selected by S1.
2–312
PALCE26V12 Family
AR CLK1
SP CLK 2
22
I/O 6
R6
S3 *
21
GND
16072E-6
LOGIC DIAGRAM (continued)
PALCE26V12
0
4
8
12
16
20
24
28
32
36
40
44
AR CLK1
SP CLK 2
48
75
10
11
00
01
D ARQ
1
0
SP
Q
20
I/O5
S0
S2
S1
91
0
1
9
I7
R5
S3*
92
10
11
00
01
D ARQ
1
0
SP
Q
S0
S2
106
0
1
10
I8
19
I/O4
S1
R4
S3*
107
10
11
00
01
D ARQ
1
0
SP
Q
S0
S2
119
0
1
11
I9
18
I/O3
S1
R3
S3*
120
10
11
00
01
D ARQ
1
0
130
SP
Q
S0
S2
0
1
12
I10
17
I/O2
S1
R2
S3*
131
10
11
00
01
D ARQ
1
0
139
SP
Q
16
I/O1
S0
S2
13
I11
0
1
S1
R1
S3*
140
10
11
D ARQ
1
0
148
SP
15
I/O 0
00
01
Q
S0
S2
14
I12
0
1
SYNCH
PRESET
149
0
4
8
12
16
20
24
28
32
36
40
44
R0
S1
S3*
48
* When S 3 = 1 (unprogrammed) the feedback is selected by S1.
When S 3 = 0 (programmed), the feedback is the opposite of
that selected by S1.
16072E-6
(concluded)
PALCE26V12 Family
2–313
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . . . . . –0.6 V to +7.0 V
Industrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
VOL
Output LOW Voltage
IOL = 16 mA
VIN = VIH or VIL
VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
IIH
IIL
Max
2.4
Unit
V
0.4
2.0
V
V
0.8
V
Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2)
10
µA
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–170
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-7/10
VCC = Max, f = 0 MHz
115
mA
H-7/10
140
mA
150
mA
ICC
(Static)
Commercial Supply Current
ICC
(Dynamic)
ICC
(Dynamic)
Industrial Supply Current
–30
VIN = 0 V, Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
H-10
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2–314
PALCE26V12H-7/10 (Com’l), H-10 (Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
COUT
Parameter Description
Test Conditions
Typ
Input Capacitance
VIN = 0 V
VCC = 5.0 V
5
Output Capacitance
VOUT = 0 V
TA = +25°C
f = 1 MHz
8
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol
-7
Parameter Description
Min
-10
Max
Min
7.5
Max
Unit
10
ns
tPD
Input or Feedback to Combinatorial Output
tS1
Setup Time from Input or Feedback
3.5
5
ns
tS2
Setup Time from SP to Clock
4.5
5
ns
tH
Hold Time
0
0
ns
tCO
Clock to Output
6
9
ns
tAR
Asynchronous Reset to Registered Output
11
13
ns
tARW
Asynchronous Reset Width
6
8
ns
tARR
Asynchronous Reset Recovery Time
5
8
ns
tSPR
Synchronous Preset Recovery Time
5
8
ns
LOW
3.5
4
ns
HIGH
3.5
4
ns
tWL
Clock Width
tWH
fMAX
Maximum
Frequency
(Notes 3 and 4)
External Feedback
1/(tS + tCO)
105.3
71.4
MHz
Internal Feedback (fCNT)
1/(tS + tCF)
125
105
MHz
tEA
Input to Output Enable Using Product Term Control
8
10
ns
tER
Input to Output Disable Using Product Term Control
7.5
10
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE26V12H-7/10 (Com’l), H-10 (Ind)
2–315
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . . . . . –0.6 V to +7.0 V
lndustrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless
otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
VOL
Output LOW Voltage
IOL = 16 mA
VIN = VIH or VIL
VCC = Min
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
VIL
Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
V
IIH
Input HIGH Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
10
µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–10
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
10
µA
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–10
µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
–160
mA
ICC
(Static)
Commerical Supply Current
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15/20
VCC = Max, f = 0 MHz
105
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-15
VCC = Max, f = 15 MHz
150
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20
VCC = Max
130
mA
VIN = 0 V, Outputs Open (IOUT = 0 mA) H-20
VCC = Max, f = 15 MHz
150
mA
ICC
(Dynamic)
ICC
(Static)
ICC
(Dynamic)
Industrial Supply Current
Min
Max
2.4
V
0.4
2.0
–30
Unit
V
V
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V
has been chosen to avoid test problems caused by tester ground degradation.
2–316
PALCE26V12H-15/20 (Com’l, Ind)
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
Parameter Description
Test Conditions
Input Capacitance
VIN = 0 V
Typ
VCC = 5.0 V
Unit
5
TA = +25°C
COUT
Output Capacitance
VOUT = 0 V
pF
f = 1 MHz
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol
-15
Parameter Description
Min
-20
Max
Min
15
Max
Unit
20
ns
tPD
Input or Feedback to Combinatorial Output
tS
Setup Time from Input, Feedback, or SP to Clock
10
13
ns
tH
Hold Time
0
0
ns
tCO
Clock to Output
10
12
ns
tAR
Asynchronous Reset to Registered Output
20
25
ns
tARW
Asynchronous Reset Width
15
20
ns
tARR
Asynchronous Reset Recovery Time
15
20
ns
tSPR
Synchronous Preset Recovery Time
10
13
ns
LOW
8
10
ns
HIGH
8
10
ns
tWL
Clock Width
tWH
fMAX
Maximum
Frequency
(Notes 3 and 4)
External Feedback
1/(tS + tCO)
50
40
MHz
Internal Feedback (fCNT)
1/(tS + tCF)
58.8
43
MHz
tEA
Input to Output Enable Using Product Term Control
15
20
ns
tER
Input to Output Disable Using Product Term Control
15
20
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE26V12H-15/20 (Com’l, Ind)
2–317
SWITCHING WAVEFORMS
Input or
Feedback
VT
tS
Input or
Feedback
tH
VT
VT
Clock
tCO
tPD
Combinatorial
Output
Registered
Output
VT
VT
16072E-8
16072E-7
Combinatorial Output
Registered Output
VT
Input
tWH
tER
Clock
VT
tEA
VOH - 0.5V
Output
VT
VOL + 0.5V
tWL
16072E-10
Clock Width
Input to Output Disable/Enable
16072E-9
tARW
Input Asserting
Asynchronous
Reset
Input Asserting
Synchronous
Preset
VT
tAR
Registered
Outputs
VT
tS
tSPR
Clock
VT
tARR
Clock
tH
VT
VT
tCO
Registered
Outputs
VT
16072E-11
Asynchronous Reset
Synchronous Preset
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns–5 ns typical.
2–318
16072E-12
PALCE26V12 Family
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1
Output
Test Point
R2
CL
16072E-13
Specification
tPD, tCO
tEA
tER
S1
CL
R1
Closed
Z → H: Open
Z → L: Closed
50 pF
H → Z: Open
L → Z: Closed
5 pF
300 Ω
PALCE26V12 Family
R2
Com’l: H-15/20
Ind: H-20
390 Ω
Com’l: H-7/10
Ind: H-10/15
300 Ω
Measured
Output Value
1.5 V
1.5 V
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
2–319
TYPICAL ICC CHARACTERISTICS FOR THE PALCE26V12H-7/10
VCC = 5.0 V, TA = 25°C
150
125
100
ICC (mA)
75
50
25
0
0
10
20
30
40
50
Frequency (MHz)
16072E-14
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector,
half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
2–320
PALCE26V12 Family
ENDURANCE CHARACTERISTICS
The PALCE26V12 is manufactured using our advanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
Symbol
tDR
N
Parameter
Min Pattern Data Retention Time
Min Reprogramming Cycles
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
Test Conditions
Min
Unit
Max Storage Temperature
10
Years
Max Operating Temperature
20
Years
Normal Programming Conditions
100
Cycles
PALCE26V12 Family
2–321
the state of the input and pulls the voltage away from the
input threshold voltage where noise can cause oscillations. For an illustration of this configuration, see below.
Bus-Friendly Inputs
The PALCE26V12H-7/10 (Com’l) and H-10/15 (Ind)
inputs and I/O loop back to the input after the second
stage of the input buffer. This configuration reinforces
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION*
VCC
100 kΩ
VCC
ESD
Protection
Input
VCC
VCC
VCC
100 kΩ
Preload
Circuitry
Feedback
Input
16072E-15
Output
*
Device
Rev. Letter
PALCE26V12H-7
PALCE26V12H-10
PALCE26V12H-15
2–322
C
Topside Marking:
CMOS PLDs are marked on top of the package in the
following manner:
PALCE xxxx
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
PALCE26V12 Family
ROBUSTNESS FEATURES
The PALCE26V12 has some unique features that make
it extremely robust, especially when operating in high
speed design environments. Input clamping circuitry
limits negative overshoot, eliminating the possibility of
false clocking caused by subsequent ringing. A special
noise filter makes the programming circuitry completely
insensitive to any positive overshoot that has a pulse
width of less than about 100 ns.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION*
VCC
VCC
> 50 kΩ
ESD
Protection
and
Clamping
Programming
Pins only
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Typical Input
VCC
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload
Circuitry
Typical Output
*
Device
Rev. Letter
PALCE26V12-15
PALCE26V12-20
B
Feedback
Input
16072E-16
Topside Marking:
CMOS PLDs are marked on top of the package in the
following manner:
PALCE xxxx
Datecode (4 numbers) LOT ID (3 characters) – – (Rev. Letter)
The Lot ID and Rev. letter are separated by two spaces.
PALCE26V12 Family
2–323
POWER-UP RESET
The power-up reset feature ensures that all flip-flops will
be reset to LOW after the device has been powered up.
The output state will depend on the programmed
configuration. This feature is valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide
Parameter
Symbol
range of ways VCC can rise to its steady state, two
conditions are required to ensure a valid power-up
reset. These conditions are:
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter Description
Max
Unit
tPR
Power-Up Reset Time
1000
ns
tS
Input or Feedback Setup Time
tWL
Clock Width LOW
See Switching
Characteristics
VCC
4V
Power
tPR
Registered
Active-Low
Output
tS
Clock
tWL
Power-Up Reset Waveform
2–324
PALCE26V12 Family
16072E-17
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
PALCE26V12
Parameter
Symbol
Typ
Parameter Description
SKINNYDIP
PLCC
Unit
θjc
Thermal impedance, junction to case
19
18
°C/W
θja
Thermal impedance, junction to ambient
65
55
°C/W
200 lfpm air
59
48
°C/W
400 lfpm air
54
44
°C/W
600 lfpm air
50
39
°C/W
800 lfpm air
50
37
°C/W
θjma
Thermal impedance, junction to ambient with air flow
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of
the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at
a constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE26V12H-15/20
2–325