AN058 Designing a Stable COT Converter with Desired Load and Line Regulation Designing a Stable COT Converter for a Desired Load and Line Regulation Application Note Prepared by Wei Yuan / Li Liu January 2012 AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION ABSTRACT This application note discusses the relationship between stability and the ramp added to the feedback pin for MPS’s Constant-On-Time (COT) control. It also describes how the ramp influences the load and line regulation, and discusses ramp designs that both optimize stability and the load and line regulation. Getting a Desired Load and Line Regulation Based on FB Ramp Compensation COT control operates without the need for traditional complicated loop design and has a fast transient response. To realize stability, add a ramp to the FB pin with an appropriate downward slope; the FB ramp stems either from the ESR of the output capacitor, or from the external RC compensation shown in dashed lines in Figure 1. The ramp provides a value of inequality between the average FB value and VREF, and varies with changes to the input line or load. The ramp must be large enough to eliminate jitter even at the sub-harmonic level, though not so large that the load and line regulation degrade. L Vout Ic HS R4 Vin R1 C4 Driver LS ESR Cout FB R2 Ton Vref Figure 1: Circuit Diagram of COT Control This application note describes how the FB ramp affects the load and line, and also provides a solution for optimal ramp design. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION INDEX Abstract ................................................................................................................................................. 2 How to Get a Desired Load and Line Regulation Based on the FB Ramp Compensation ............... 2 Introduction ............................................................................................................................................ 4 COT Control Introduction ................................................................................................................ 4 Relationship between FB Ramp and Jitter ...................................................................................... 4 Relationship between FB Ramp and Stability ................................................................................. 5 Relationship between FB Ramp and Load Regulation .................................................................... 6 Relationship between FB Ramp and Input Line Regulation ............................................................ 7 Design Guide For Different Output Capacitors ....................................................................................... 9 Larger ESR Output Capacitors ....................................................................................................... 9 Smaller ESR Ceramic Output Capacitors ..................................................................................... 10 Design example ................................................................................................................................... 13 AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 3 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION INTRODUCTION COT Control Introduction Unlike traditional voltage- or current-mode control, COT control provides a way to eliminate the compensation loop. COT control eliminates the error amplifier and produces a PWM signal with a fixed ON time every time the FB falls below VREF. If during the time where VFB <VREF is monotonic or in phase with the inductor ripple, then the system can operate at a fixed frequency based on the ton setting. One easy and popular way to sense the inductor current is to use a output capacitor with an appropriate ESR value so the ESR×ΔIL (inductor current ripple) dominates the VOUT ripple, which then transfers to FB through the feedback resistors. FB turns on with a fixed ON time immediately when VOUT falls and remains OFF while VFB>VREF this kind of control produces a fast transient without delays from the compensation loop and internal clock. L Vout Ic HS R1 Driver LS Vin FB ESR VREF Cout FB R2 PWM IL ton Vref VOUT Figure 2: COT Buck Circuit Diagram and Operational Signal Diagram Relationship between FB Ramp and Jitter COT control depends on the ramp on FB crossing VREF to stabilize the system, so the ramp on FB should be large enough to reduce the jitter induced by the FB noise. Figure 3 shows jitter reduction with COT control. The noise on the downward VFB slope affects the time before the highside PWM turns on, where a large ramp slope leads to smaller jitter. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 4 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION RAMP2 RAMP1 FB Noise PWM Jitter1 Jitter2 Figure 3: Ramp Slope and Jitter Performance One major factor that affects jitter and stability is the downward slope when the FB ramp crosses VREF. However, the FB ramp largely results from the ESR sensing the inductor ripple or from the external RC components therefore increasing the ramp amplitude increases the downward slope to reduce jitter. Relationship between FB Ramp and Stability A too-small ramp causes more problem than just jitter: a 90° phase delay between the ESR ripple and capacitor ripple makes the combined FB ripple non-monotonic if the capacitor ripple dominates the ramp ripple. Figure 4 compares system operation with either ESR or capacitor ripple dominanating the system. For instance, if the ESR ripple is large enough, it dominates the ramp on FB and the time for the FB downward slope to cross REF remains at the same point. Conversely, if the ESR ripple is too small, then the capacitor ripple dominates the FB ripple, the sub-harmonics become noticeable for nonmonotonic FB ripple. FB Ramp with enough ESR FB Ramp with Small ESR Duty Duty ESR ripple Tdelay ESR ripple Cap ripple Cap ripple FB ripple FB ripple REF REF ESR ripple dominates (100μF/10mΩ) Cap ripple dominates (100μF/1mΩ) Figure 4: FB Ramp and Stability AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 5 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION Relationship between FB Ramp and Load Regulation Because COT control turns on the PWM signal every time VFB crosses VREF—which means VREF is just equal to the minimum value of VFB, and the average value of VFB(VFB(AVG)) does not equal to VREF— VFB(AVG) equals the sum of VREF and the average value of the ramp. COT control provides a seamless transient from the quasi-fixed–frequency CCM mode to pulse-frequency modulation (PFM) mode when the load decreases. During PFM mode, the switching frequency decreases when the load decreases, meaning that the shape of the FB ramp also varies with the load and causes variation in the average value on FB. Figure 5 shows the variation on the FB ramp with different loads. FB VFB(AVG) CCM Ref FB Light Load VFB(AVG) Ref FB Ultra Light Load VFB(AVG) Ref Figure 5: FB Ramp Variations with Different Loads The FB ramp changes as the load changes from critical CCM mode to no-load; as the load decreases, VFB(AVG) decreases. So we are here mention the load regulation due to the VFB(AVG) change from no load to critical CCM load, the load regulation drop in the CCM mode when the load increase is not included here, and may not relate to this discussion. Generally, the relationship between the VFB(AVG) and the VOUT could be simplified as: VOUT = R1 + R2 VFB(AVG) R2 (1) So the ΔVOUT when the load changes from CCM to no-load condition could be estimated as): ∆VOUT = R1 + R2 R1 + R2 ∆VFB(AVG) ≈ k VRAMP R2 R2 (2) Where k is difference between VFB(AVG) during CCM versus PFM—usually around 0.25. Reducing R1 and R2 reduces k. VRAMP is the amplitude of the FB ramp. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 6 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION If ESR dominates the FB ramp, then, = VRAMP R2 1− D ⋅ ⋅ VOUT ⋅ t sw R1 + R2 L RESR (3) If the external ramp from R4 and C4 dominates the FB ramp, then VRAMP = 1− D ⋅ Vo ⋅ t sw R4 * C4 (4) Where tSW is the switching period, D is the duty cycle period, and L, RESR, R4, C4 refer to components in Figure 1. Based on equation (2), better load regulation requires a small ramp on FB. Figure 6 provides a comparison between load regulation when different VRAMP values. Load Regulation(vs.Ramp) Load Reg(%) 1 Vramp=21mV 0.5 0 PFM CCM -0.5 -1 Vramp=51mV -1.5 -2 0 500 1000 1500 2000 Io(mA) Figure 6: Load Regulation with Different Ramp Values: VIN=12V, VOUT=5V, L=4.7μH, fSW=530kHz, IOUT=1.5A, COUT=2×22μF (Ceramic) Relationship between FB Ramp and Input Line Regulation MPS’s COT control provides quasi-fixed–frequency operation in CCM mode; i.e., the switching frequency remains unchanged with VIN, but the FB ramp (and subsequently, VFB(AVG)) changes as the inductor current changes. As shown in Figure 5, the largest value of VFB(AVG) during CCM, hence, the worst case for input line regulation occurs CCM. The difference between VFB(AVG) and VREF can be derived from equations (5), (3), and (4) with different output capacitors. VFB(AVG) - VREF ≈ AN058 Rev. 1.1 5/12/2014 1 VRAMP 2 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (5) 7 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION Based on equations (3) and (4), when VIN increases, VFB(AVG) increases as the duty cycle decreases for VOUT to increase according to equation (2). Figure 7 the FB ramp varying with VIN in CCM mode. FB Lower Vin VFB(avg) Ref FB Higher Vin VFB(avg) Ref Figure 7: Variation of the FB ramp with VIN VOUT vs. VIN in CCM mode could be expressed as equations (6) and (7) with different output capacitors R1 + R2 1 R1 + R2 1 ∆D ∆VOUT_ESR = ∆VFB(AVG) ≈ ∆VRAMP =⋅ ⋅ VOUT ⋅ t sw R2 2 R2 2 L RESR ∆VOUT_RC ≈ ∆D 1 R1 + R2 1 R1 + R2 ∆VRAMP =⋅ ⋅ ⋅ VOUT ⋅ t sw 2 R2 2 R2 R4 ⋅ C4 (6) (7) Where ΔVOUT_ESR represents changes in VOUT with different ESR output capacitors, and ΔVOUT_RC represents changes in VOUT based on external RC compensation with ceramic capacitors. ΔD = duty cycle change due to the VIN change. Generally, a smaller FB ramp results in better line regulation. Figure 8 compares line regulations with different VRAMP using external ramp compensation with ceramic output capacitors. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 8 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION Line Reg(%) Line Regulation(vs.Vramp) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 Vramp=24mV Vramp=51mV Vramp=108mV 7 9 11 13 15 17 19 Vin(V) Figure 8: Variation of the FB ramp with VIN (VIN=7-19V, VOUT =5V, L=4.7μH, fSW=720kHz, IOUT=1.5A, COUT=22μF×2/Ceramic) DESIGN GUIDE FOR DIFFERENT OUTPUT CAPACITORS The previous section describes key considerations in the ramp design: stabilizing the system requires the largest VRAMP possible. However, desired load and line regulation requires trading off between the stability and the load and line regulation. Since the ramp results from the ESR of the output capacitors or from the external compensation when ESR is insufficiently large, this design guide is separated into two parts: Large ESR Output Capacitors, and the Small ESR Ceramic Output Capacitors. LARGE ESR OUTPUT CAPACITORS Capacitors with large ESR, such as POSCAPs, usually have a capacitance larger than 100µF, meaning that the ESR ripple dominates the output ripple, the ramp on FB is related to the inductor current, and no external compensation is need. Figure 9 shows an equivalent circuit in CCM without an external ramp circuit. SW VOUT L FB R1 ESR POSCAP R2 Figure 9: Simplified Circuit in PWM Mode without External Ramp Compensation AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 9 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION To realize the stability without an external ramp , select an ESR value as follows: D 1 + MAX ) ⋅ t SW 2 ≥ Q⋅π COUT ( RESR (8) Where Q is usually set around 0.7 to 1, DMAX is the maximum duty cycle during the operation: In case VOUT is fixed while VIN varies, the maximum duty cycle can be found at the lowest VIN The limitation due to the load and line regulation can be expressed as: RESR ≤ ∆VOUT_LOAD L⋅ ⋅ k ⋅ (1-DMIN ) ⋅ t sw VOUT (9) 2 ⋅ L ⋅ ∆VOUT_LINE ∆D ⋅ t sw VOUT (10) RESR ≤ Where k is usually set around 0.25, DMIN is the minimum duty cycle during the operation, and ΔD= DMAX-DMIN. In addition, ∆VOUT_LINE VOUT ∆VOUT_LOAD VOUT is the acceptable maximum peak-to-peak load-line regulation, and is the acceptable maximum peak-to-peak input line regulation. In some extreme cases when the differences between (8) and the minimum values of (9) and (10) are negative, other parameters must change to increase the difference by: 1. Increasing L, 2. Increasing fSW, or 3. Selecting an output capacitor with a larger capacitance while keep the ESR almost the same. SMALL ESR CERAMIC OUTPUT CAPACITORS Selecting a small ESR capacitor as an output capacitor requires an external RC compensator to form a ramp on FB using R4 and C4, as shown in Figure 10. R9 acts as the noise filter resistance to filter the high frequency noise—usually set around 0Ω-1kΩ. To ensure that the FB ramp is not substantially affected by R9, select R9 to be much smaller than R1//R2. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 10 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION SW VOUT L R4 FB C4 R1 R9 Ceramic R2 Figure 10: Simplified Circuit in PWM Mode with external components For stability, R4 and C4 should meet: D 1 + MAX ) ⋅ t SW IOUT ⋅ 10-3 Ω 1 2 ≥ Q⋅π + R4 ⋅ C4 2 ⋅ L ⋅ COUT VOUT ⋅ t SW ⋅ (1 − DMAX ) ( (11) Where IOUT is the full load output current, and Q=[0.7 to 1]. The limitation due to the load and line regulation on R4 and C4 is: ∆VOUT _LOAD 1 R2 ⋅ ≤ ⋅ R4 ⋅ C4 k ⋅ (R1 + R2) ⋅ t sw ⋅ (1-DMIN ) VOUT (12) ∆VOUT_LINE 1 2 ⋅ R2 ⋅ ≤ ⋅ R4 ⋅ C4 (R1 + R2) ⋅ ∆D ⋅ t sw VOUT (13) Where k is usually set around 0.25, DMIN is the minimum duty cycle during the operation, ΔD= DMAX-DMIN, ∆VOUT_LOAD VOUT is the acceptable maximum peak-to-peak load line regulation, and ∆VOUT_LINE VOUT is the acceptable maximum peak-to-peak input line regulation. Choose a minimum value between (12) and (13), then an appropriate range for R4 and·C4 is then defined by (11). Besides meeting the requirements in equations (11)-(13), C4 should also meet the following: 1 2π × fSW × C4 < 1 R1× R2 × + R9 5 R1 + R2 (14) Thus allowing C4 and R4 to be selected separately. Once C4 is selected, select R4 from the smaller end of its available range for better stability and smaller jitter, or a larger R4 for better transient, lightload performance, and the load and line regulation. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 11 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION If the range for R4 and C4 selection is small or even negative, then make flowing changes to improve the range: 1) Increase L or COUT 2) Increase fSW 3) Reduce R1 and R2 if the actual load regulation is poor for the ultra light load condition drop AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 12 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION DESIGN EXAMPLE • Typical input voltage: VIN =12V • Maximum input voltage: VIN_MAX=19V • Minimum input voltage: VIN_MIN=9V • Output voltage: VOUT = 5V • Maximum output current: IOUT = 6A • Output Capacitors: COUT=22μF×3/Ceramic • Inductance: L = 4.7μH • Switching frequency: fSW = 500kHz • Duty cycle: DMAX=0.556@ VIN =9V, DMIN=0.263@ VIN =19V • Reference voltage: VREF=0.815V • Maximum peak-to-peak Load Regulation: • Maximum peak-to-peak Line Regulation: 1) ∆VOUT_LOAD VOUT ∆VOUT_LINE VOUT = 1.5% = 2% Selecting R1, R2 and R9 Since this application note only focuses on selecting ramp parameters, refer to relevant datasheets for feedback resistor design and VOUT selection. The initial calculations usually cannot provide absolute feedback resistor calculations, but the ratio set by the VOUT and VREF is enough to design the external ramp compensation R4 and C4, assuming R1=51.3kΩ, R2=10kΩ, and R9=0.5kΩ. 2) Determining RC Constraints Based on the Stability Requirement Based on the previous case, VIN ranges from 9V-19V, hence the maximum duty cycle (DMAX) occurs at VIN=9V (according to equation (11)). Set Q=0.7, so that R4 and·C4 satisfies: 1 ≥ 3.71⋅ 10 3 (s -1) R4 ⋅ C4 3) RC Constraint Based on the Load Regulation Requirement From equation (12), the minimum value occurs during the shortest duty cycle, so R4·C4 should meet following requirements at the maximum input voltage. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 13 AN058 –DESIGNING A STABLE COT CONVERTER FOR DESIRED LOAD AND LINE REGULATION 1 ≤ 6.15 ⋅ 10 3 (s -1) R4 ⋅ C4 4) RC Constraint Based on the Input Line Regulation Requirement R4 and·C4 are constrained by the maximum input line regulation. Based on equation (13), R4 and C4 must meet: 1 ≤ 10.3 ⋅ 10 3 (s -1) R4 ⋅ C4 5) Determining the Minimum C4 Value from Equation (14): C4 ≥ 6) 5 = 177pF 2π ⋅ fsw ⋅ (R1//R2 + R9) Combined with requirements from step 2) - 5), R4=739kΩ1.22MΩ if C4=220pF R4=492kΩ816kΩ if C4=330pF Choose a smaller R4 within the range if the load and line regulation requirements are met. 7) Once the R4 and C4 are selected, refine R1 and R2 based on the related datasheets. Select typical values of VIN=12V,R4=492kΩ,C4=330pF, R2=10kΩ, R9=0.5kΩ for: R1 = R2 VFB(AVG) VOUT − VFB(AVG) R2 − R4 + R9 = 56.2kΩ NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN058 Rev. 1.1 5/12/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 14

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