NJU3714A 12-BIT SERIAL TO PARALLEL CONVERTER PACKAGE OUTLINE GENERAL DESCRIPTION The NJU3714A is a 12-bit serial to parallel converter especially applying to MPU outport expander. It can operate from 2.4V to 5.5V. The effective outport assignment of MPU is available as the connection between NJU3714A and MPU using only 4 lines. The serial data synchronizing with 5MHz or more clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data latches. Furthermore, the NJU3714A outputs the serial data from SO terminal through the shift register. Therefore, it connects with other SIPO ICs like as NJU3711A in cascade for expanding the parallel conversion outputs. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. NJU3714AV PIN CONFIGURATION FEATURES 12-Bit Serial In Parallel Out Cascade Connection Hysteresis Input 0.5V typ at 5V Operating Voltage 2.4 to 5.5V Maximum Operating Frequency 5MHz Output Current 25mA at 5V, 5mA at 3V C-MOS Technology Package Outline SSOP20 P5 P6 P7 P8 VSS P9 P10 P11 P12 SO 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD P4 P3 P2 P1 VSS CLR STB CLK DATA NJU3714AV BLOCK DIAGRAM P1 DATA Latch Circuit Shift Register P2 CLK P3 P11 P12 SO STB CLR Ver.2012-03-15 Controller Circuit -1- NJU3714A TERMINAL DESCRIPTION No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 -2- SYMBOL P5 P6 P7 P8 VSS P9 P10 P11 P12 SO DATA CLK STB CLR VSS P1 P2 P3 P4 VDD I/O O O O O O O O O O I I I I O O O O - FUNCTION Parallel Conversion Data Output Terminals GND Parallel Conversion Data Output Terminals Serial Data Output Terminal Serial Data Input Terminal Clock Signal Input Terminal Strobe Signal Input Terminal Clear Signal Input Terminal GND Parallel Conversion Data Output Terminals Power Supply Terminal (2.4 to 5.5V) Ver.2012-03-15 NJU3714A NJU3555 FUNCTIONAL DESCRIPTION (1) Reset When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion output are "L" level. Normally, the CLR terminal should be "H" level. (2) Data Transmission In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal. When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latches. Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore, the clock signal should be controlled for data order. (3) Cascade Connection The serial data input from DATA terminal is output from the SO terminal through internal shift register unrelated with the CLR and STB status. Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure to protect the noise. CLK STB CLR X X L H H L H L H OPERATION All of latches are reset (the data in the shift register is no change). All of parallel conversion outputs are "L". The serial data into the DATA terminal are inputted to the shift register. In this stage, the data in the latch is not changed. The data in the shift register is transferred to the latch. And the data in the latch is output from the parallel conversion output terminals. When the clock signal is inputted into the CLK terminal in state of the STB="L" and CLR="H", the data is shifted in the shift register and latched data is also changed in accordance with the shift register. Note 1) X: Don’t care Ver.2012-03-15 -3- NJU3714A TIMING CHART CLK CLR STB DATA P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 SO -4- Ver.2012-03-15 NJU3714A NJU3555 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage Range VDD -0.5 ~ +7.0 V Input Voltage Range VI VSS-0.5 ~ VDD+0.5 V Output Voltage Range VO VSS-0.5 ~ VDD+0.5 V Output Current IO ±25 mA Output Short Current IOS (SO Terminal) (Note 5) Output Short Current IOSD (P1~P8 Terminals) (Note 5) Power Dissipation VO=7V, VI=0V 10 (max) VO=0V, VI=7V -10 (max) VO=7V, VI=0V 20 (max) VO=0V, VI=7V -20 (max) PD (Note 6) 675 (SSOP) (Note 6) mA mA mW Operating Temperature Range Topr -25 ~ +85 °C Storage Temperature Range Tstg -65 ~+150 °C Note 2) All voltage are relative to VSS=0V reference. Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also Note 4) Note 5) Note 6) recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. To stabilize the IC operation, place decoupling capacitor between VDD and VSS. VDD=7V, VSS=0V, less than 1 second per pin. EIA/JEDEC Standard Test Board (76.2 x 114.3 x 1.6mm, 2layers, FR-4) mounting. DC ELECTRICAL CHARACTERISTICS (VDD=2.4~5.5V, VSS=0V, Ta=25°C, unless otherwise noted) CONDITION MIN TYP MAX UNIT PARAMETER SYMBOL Operating Voltage VDD Operating Current IDDS VIH=VDD, VIL=VSS High-level Output Voltage VOH IOH=-0.4mA Low-level Output Voltage VOL IOL=+3.2mA High-level Input Voltage 2.4 - 5.5 V - - 0.1 mA VDD-0.4 - VDD V VSS - 0.4 V VIH 0.7VDD - VDD V Low-level Input Voltage VIL VSS - 0.3VDD V Input Leakage Current ILI -10 - 10 µA VDD-1.5 - VDD VDD-1.0 - VDD VDD-0.5 - VDD VDD-0.5 - VDD VSS - 1.5 VSS - 0.8 VSS - 0.4 VSS - 0.5 SO Terminal VI=0~VDD IOH=-25mA High-level Output Voltage (Note 7) VOHD VDD=5V IOH=-15mA IOH=-10mA VDD=3V P1~P12 Terminals IOH=-5mA IOL=+25mA Low-level Output Voltage (Note 7) VOLD VDD=5V IOL=+15mA IOL=+10mA VDD=3V IOL=+5mA P1~P12 Terminals V V Note 7) Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating operation should be required. Ver.2012-03-15 -5- NJU3714A SWITCHING CHARACTERISTICS (VDD=2.4~5.5V, VSS=0V, Ta=25°C, unless otherwise noted) CONDITION MIN TYP MAX UNIT PARAMETER SYMBOL Set-Up Time tSD DATA-CLK 20 - - ns Hold Time tHD CLK-DATA 20 - - ns Set-Up Time tSSTB STB-CLK 30 - - ns Hold Time tHSTB CLK-STB 30 - - ns tpd O CLK-SO - - 70 ns tpd PCK CLK-P1~P12 - - 100 ns tpd PSTB STB-P1~P12 - - 80 ns tpd PCLR CLR-P1~P12 - - 80 ns 5 - - MHz Output Delay Time Maximum Operating Frequency fMAX Note 8) COUT=50pF -6- Ver.2012-03-15 NJU3714A NJU3555 SWITCHING CHARACTERISTICS TEST WAVEFORM fMAX CLK tSD DATA tHD STB tSSTB tHSTB CLK tpd O SO CLK tpd PCK L STB P1~P12 CLK H STB tpd PSTB P1~P12 CLR DATA tpd PCLR H P1~P12 Ver.2012-03-15 -7- NJU3714A APPLICATION CIRCUIT (1) MPU P1 P2 DATA P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 CLK NJU3714A STB CLR SO APPLICATION CIRCUIT (2) (Combined with NJU3711A) MPU P1 P2 DATA CLK STB P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 NJU3714A CLR SO DATA CLK STB CLR NJU3711A P1 P2 P3 P4 P5 P6 P7 P8 MOTOR DRIVER M [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -8- Ver.2012-03-15