PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator Block Diagram Pin Configuration VDDIO_26M PD_26M 2 Oscillator OutX_26M X2_26M 26 MHz Crystal1 or TCXO Clock input X1_26M X1/TCXO_IN VDD Out_32K Oscillator 16 15 OUT2_26M GND VDD 2 14 OUT1_26M 3 13 VDDIO_26M 12 GND OE_32K 4 X1_32K 5 17 6 7 8 9 VDDIO_32K 32.768KHz Crystal2 18 OUT_32K X1_32K 1 VDD32K_OSC VDDIO_32K OE_32K VDD_32K VDD X2_32K 20 19 X2_26M PD The PI6C4022 contains two very low phase oscillator circuits with associated circuitry to drive external loads. Power down circuitry allows one or both oscillators to be turned off to minimize power consumption. GND Description • Independent 26MHz and 32.768kHz oscillators • Outputs are weakly pulled down when OE = LOW • Glitch-free outputs on start-up, release from power down, or when OE pin is set to HIGH (on) state. • No internal pull-ups on logic inputs • 10μA 32kHz supply current max • 26MHz input can be over-driven with external oscillator, TCXO, etc • Core runs from 1.5V to 1.8V • One 26MHz output option available • 3x3mm 20-pad QFN VDD26M_OSC Features 11 10 PD_26M External load capacitors are required GND PD 1. SaRonix-eCera FL2600057 2. SaRonix-eCera 32S12 08-0303 1 GND X2_32K PS9015A 11/18/08 PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator Pin Description Pin Number 1, 3 2, 10, 12, 17 4 Symbol VDD GND OE_32K I/O Type Power Power Input 5 X1_32K Input 6 X2_32K Output 7 8 9 11 VDD32K_OSC OUT_32K VDDIO_32K PD_26M Power Outpuy Power Input 13 14, 15 VDDIO_26M OUT1_26M, OUT2_26M Power Output 16 PD Input 18 19 20 VDD26M_OSC X2_25M X1/TCXO_IN Ouput Input Description Core power supply Ground pins Output Enable for 32 kHz oscillator. High enables output. Low tri-states the output with a 1uA pull down current. There is no pull-up or pull-down resistor on this logic input. 32kHz OSC input with a 1pF on-chip Xtal load capacitance 32kHz OSC input with a 10pF on-chip Xtal load capacitance 32kHz OSC VDD supply 32 kHz buffer output 32 kHz buffer supply Power down for 26MHz oscillator and output. A low tri-states the 26MHz outputs while providing a 1 uA pull-down. The logic pin has no internal pull-up or pull-down resistor. VDD supply of the two 26MHz buffers 26MHz output Power down. A low puts the entire chip in power down. There is no internal pull-up or pull-down resistor VDD supply of 26MHz OSC 26MHz OSC output pin 26MHz OSC output pin. This pin should be AC driven for TCXO input. Total Cload of 10pF is integrated into the oscillator. Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature...........................................................–65°C to +150°C VDDO,VDD Voltage................................................................–0.5V to +2.5V Output Voltage (max 2.5V) .......................................... –0.5V to VDD+0.5V Input Voltage (max 2.5V) ............................................. –0.5V to VDD+0.5V 08-0303 2 Note: Stresses greater than those listed under MAXIMUM RAT INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PS9015A 11/18/08 PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator Characteristics (Over Operating Range: VDD=VDDIO=1.5 to 1.8V, TA = -40° to 85°C) Test Conditions(1) Parameters Description VDD Min. Typ. Max. Core Supply 1.5 1.8 VDDIO I/O Supply Voltage 1.5 1.8 VIH Input HIGH Voltage Logic HIGH level 0.7 × VDD VDD+0.3 VIL Input LOW Voltage Logic LOW level -0.3 0.35 × VDD Input Current VDD = Max, VIN = VDD or GND I pin IL 15 Units V μA CLX1_32K X1_32 pin internal load capacitance 1 pF CLX2_32K X2_32 pin internal load capacitance 10 pF CL_26 26MHz X1/X2 pin internal load capacitance 10 pF IDD Total supply current for entire IC 5 mA Max. Units Note: 1. No runt or short pulses. Output is internally gated such that first clock out meets all specifications. 32kHz Characteristics (Over Operating Range: VDD=VDDIO=1.5 to 1.8V, TA = -40° to 85°C) Parameters Description Test Conditions(1) Min. .75 x VDD Typ VOH Output High Voltage VDD = Min., IOH = -3mA VOL Output Low Voltage VDD = Min., IOL = 3mA .25 x VDD fOUT Output Frequency Synthesis Error 32.768 0 kHz tDC Output Duty Cycle 55 % 7.5 ns tR/tF CLKn Rise/Fall Time 1 @ VDDO/2 45 20% to 80%, CL = 10pF tDIS,tEN Output Enable/Disable Time 10 ms tstart32 32KHz start-up time 500 ms Max. Units 26 0 MHz 2 ns Note: 1. No runt or short pulses. Output is internally gated such that first clock out meets all specifications. 26MHz Characteristics (Over Operating Range: VDD=VDDIO=1.5 to 1.8V, TA = -40° to 85°C, CL = 10pF) Parameters Description Test Conditions(1) fOUT Output Frequency Synthesis Error tr,tf Rise/Fall Time 20% to 80% VOH Output High Voltage IOH = 8mA VOL Output LOW Voltage IOL = -8mA tDC Output Duty Cycle @ VDDO/2 tDIS,tEN Power Up/Down Time PN Phase Noise Power PN Phase Noise Power TPP Tskew 08-0303 Min. Typ .75 x VDD V .25 x VDD V 55 % 10 ms 1 kHz Offset -120 dBc/Hz 10 kHz Offset -135 dBc/Hz Peak-to-Peak Jitter (100K samples) 40 ps Skew between 26MHz outputs 500 ps 3 45 PS9015A 11/18/08 PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator Phase Jitter (26MHz, 100Hz to 1MHz ≈ 181fs (typical) ) 26 Waveforms Duty Cycle – tDC Output to Output Skew – tSK(O) tPW VDDO VOH BCLKx VDDO/2 VDDO/2 0V VOL tSK(O) BCLKy tSK(O) VOH tPZL tPERIOD tDC = (tPW / tPERIOD ) x 100% VDDO/2 VOL 08-0303 4 PS9015A 11/18/08 PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator AC Test Circuit Load Note: VDD = VDDO = 1.5V to 1.8V VDD VDD 10pF GND 26MHz Crystal Characteristic for SaRonix-eCera FL2600057 Parameters Description OSCMODE Mode of Oscillation FREQ Frequency ESR Equivalent Series Resistance CLOAD Load Capacitance CSHUNT Shunt Capacitance DRIVE Drive Level Min Typ Max. Units Fundamental 26 MHz 100 12 Ohm pF 7 pF 0.1 μW Max. Units 32kHz Crystal Characteristic for SaRonix-eCera 32S12 Parameters Description OSCMODE Mode of Oscillation FREQ Frequency ESR Equivalent Series Resistance CLOAD Load Capacitance DRIVE Drive Level 08-0303 Min Typ Fundamental 32.768 kHz 50 12.5 pF 0.1 5 kOhm PS9015A μW 11/18/08 PI6C4022 Very Low Phase Noise, Dual Frequency LVCMOS Clock Oscillator Package Mechanical: 20-Lead QFN (ZL) DATE: 09/24/08 DESCRIPTION: 20-Lead, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZL20 REVISION: -- DOCUMENT CONTROL #: PD-2083 08-0479 PI6C4022 Ordering Information(1,2,3) Ordering Code PI6C4022ZLE Package Code Package Description ZL Pb-Free and Green 20-Lead QFN Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0303 6 PS9015A 11/18/08