PI3PCIE3412

PI3PCIE3412
3.3V, PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch, with Single Enable
Features
Description
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Pericom Semiconductor’s PI3PCIE3412 is an 8 to 4 differential
channel multiplexer/demultiplexer switch. This solution can
switch 2 full PCI Express® 3.0, lanes to one of two locations. Using a unique design technique, Pericom has been able to
minimize the impedance of the switch such that the attenuation
observed through the switch is mininal. The unique design
technique also offers a layout targeted for PCI Express signals,
which minimizes the channel to channel skew as well as channel
to channel crosstalk as required by the PCI Express specification.
PI3PCIE3412 can also be used for application up to 12Gbps
4 Differential Channel, 2:1 Mux/DeMux
PCI Express® 3.0 Performance, 8.0Gbps
Bi-directional Operation
Low Bit-to-Bit Skew, 10ps max
Low channel-to-channel skew, 20ps max
Low Crosstalk: -35dB@4 GHz
High Off Isolation: -22dB@4 GHz (8.0Gbps)
Low insertion loss: -1.3dB@4 GHz (8.0Gbps)
Return loss: -21dB@4 GHz
Support for DP1.2 - HBR2, HBR, RBR
Supply Voltage 3.3V
Packaging (Pb-free & Green): – 42-contact, TQFN (ZH42)
Application
Routing of PCI Express 3.0, DP1.2, USB3.0, SAS2.0, SATA3.0,
XAUI, RXAUI signals with low signal attenuation.
Pin Configuration (Top-side view)
A0+
B0+
A0-
B0-
A1+
B1+
A1-
B1-
VDD
GND
VDD
GND
Block Diagram
GND
A0+
A0GND
VDD
A1+
A1VDD
SEL
GND
A2+
A2VDD
GND
A3+
A3GND
C0+
C0C1+
C1-
A2+
B2+
A2-
B2-
A3+
B3+
A3-
B3C2+
C2C3+
C3-
SEL
Truth Table
SEL
AN to BN
L
AN to CN
H
13-0046
42 41 40 39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
B0+
B0B1+
B1C0+
C0C1+
C1VDD
B2+
B2B3+
B3C2+
C2C3+
C3-
18 19 20 21
VDD
GND
VDD
GND
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
www.pericom.com04/15/13
PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Pin Description
Pin #
Pin Name
I/O
Description
2
A0+
3
A0–
I/O
Signal I/O, Channel 0, Port A
6
A1+
7
A1–
I/O
Signal I/O, Channel 1, Port A
11
A2+
12
A2–
I/O
Signal I/O, Channel 2, Port A
15
A3+
16
A3–
I/O
Signal I/O, Channel 3, Port A
38
B0+
37
B0−
I/O
Signal I/O, Channel 0, Port B
36
B1+
35
B1−
I/O
Signal I/O, Channel 1, Port B
29
B2+
28
B2−
I/O
Signal I/O, Channel 2, Port B
27
B3+
26
B3−
I/O
Signal I/O, Channel 3, Port B
34
C0+
33
C0–
I/O
Signal I/O, Channel 0, Port C
32
C1+
31
C1–
I/O
Signal I/O, Channel 1, Port C
25
C2+
24
C2–
I/O
Signal I/O, Channel 2, Port C
23
C3+
22
C3−
I/O
Signal I/O, Channel 3, Port C
9
SEL
I
Operation mode Select
(when SEL=0: A→B, when SEL=1: A→C
5, 8, 13,18, 20, 30,
40, 42
VDD
Pwr
3.3V ±10% Positive Supply Voltage
Pwr
Power ground
1, 4, 10,14, 17, 19, 21,
GND
39, 41, Center Pad
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .....................................................–65°C to +150°C
Supply Voltage to Ground Potential ................................–0.5V to +4.6V
Channel DC Input Voltage ................................................. –0.5V to 1.5V
DC Output Current ....................................................................... 120mA
Power Dissipation ............................................................................ 0.5W
SEL DC Input Voltage ....................................................... –0.5V to 4.6V
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
VDD
3.3V Power Supply
IDD
Total current from VDD 3.3V supply
VI/O-DIF
Differential Voltage (differential pins)
VI/O-CM
Common Mode Voltage (differiential pins)
TCASE
Case temperature range for operation within spec.
Min
Typ
Max
Units
3.0
3.3
3.6
V
0.15
1
mA
1.6
Vppd
0
0.8
V
-40
85
Celsius
SEL = 0V or VDD
DC Electrical Characteristics for Switching over Operating Range Test Conditions(1)
Parameters Description
Min
Typ(1) Max
Units
VIH - SEL
Input HIGH Voltage, SEL Input
2
3.6
VIL - SEL
Input LOW Voltage, SEL Input
0
0.8
VIK
Clamp Diode Voltage
VDD = Max., IIN = –18mA
IIH
Input HIGH Current, SEL
VDD = Max., VIN = VDD
±5
IIL
Input LOW Current, SEL
VDD = Max., VIN = 0V
±5
IIN - SEL
Input Leakage Current, SEL Input
VIN = VIH - SEL Max or VIL - SEL Min
–10
+10
IIH
Input HIGH Current, A X, BX, CX
VDD = Max., VIN = 1.5V
–10
+10
IIL
Input LOW Current, A X, BX, CX
VDD = Max., VIN = 0V
–10
+10
IOZH
HighZ HIGH Current, BX, CX
VDD = Max., VIN = 1.5V
–10
+10
µA
IOZL
HighZ LOW Current, BX, CX
VDD = Max., VIN = 0V
–10
+10
µA
CI/O-ON
ON state I/O capacitance
RON
ON state resistance
–0.7
VDD = 3.3V, IO = 8mA, VIN = 0.8V
Note:
1. Typical values are at VDD = 3.3V, TA = 25°C ambient and maximum loading.
V
–1.2
µA
µA
µA
1.5
pF
5
Ω
Switching Characteristics
Parameters
Description
tPZH, tPZL
Min.
Typ.
Max.
Line Enable Time - SEL to AN, BN, CN
2
20
25
tPHZ , tPLZ
Line Disable Time - SEL to AN, BN, CN
0.5
5
25
tb-b
Bit-to-bit skew within the same differential pair
5
10
ps
tch-ch
Channel-to-channel skew
20
ps
13-0046
Test Conditions
3
Units
ns
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Dynamic Electrical Characteristics
Parameter
Typ.(1)
Max.
f= 50MHz - 1.25GHz
-0.8
-1
Differential Insertion Loss
f=1.25GHz - 2.5GHz
-1.0
-1.2
(VIN = -10dBm, DC = 0V)
f=2.5GHz - 4GHz
-1.3
-1.6
f=5GHz
-1.8
-2.2
Description
DDIL
DDILOFF
Test Conditions
Differential Off Isolation
DDRL
Differential Return Loss
DDNEXT
Near End Crosstalk
VI F
Max Signal Frequency Range
BW
Min.
f= 50MHz - 1.25GHz
-26.3
-32.9
f=1.25GHz - 2.5GHz
-21.4
-26.7
f=2.5GHz - 4GHz
-17.6
-22
f=5GHz
-16
-20
f= 50MHz - 1.25GHz
-20
-25
f=1.25GHz - 2.5GHz
-18.4
-23
f=2.5GHz - 4GHz
-16.8
-21
f=5GHz
-9.6
-12
f= 50MHz - 1.25GHz
-34.1
-42.6
f=1.25GHz - 2.5GHz
-30.5
-38.1
f=2.5GHz - 4GHz
-28.1
-35.1
f=5GHz
-27.2
-34
Insertion loss 1.5dB,
VIN=0.623Vpp, DC=0V
4.0
Insertion loss 1.5dB,
VIN=0.623Vpp, DC=0.9V
4.0
Insertion loss 3dB,
VIN=0.623Vpp, DC=0V
8.0
Insertion loss 3dB,
VIN=0.623Vpp, DC=0.9V
8.0
Units
dB
dB
dB
dB
GHz
-3dB Bandwidth
8.2
GHz
Notes:
1. Guaranteed by design. Typical values are at VDD = 3.3V , Ta = 25°C ambient and maximum loading.
+
+
BALANCED
PORT1
–
BALANCED
PORT1
+
+
50
–
–
50
BALANCED
– PORT2
+
–
DUT
BALANCED
PORT2
DUT
Diff. Insertion Loss and Return Test
Circuit
13-0046
Diff. Off Isolation Test Circuit
4
BALANCED
PORT1
BALANCED
PORT2
+
+ 50
–
– 50
+
+ 50
–
– 50
DUT
Diff. Near End Xtalk Test Circuit
www.pericom.com04/15/13
PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Differential Insertion Loss
Differential Return Loss
13-0046
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Differential Off Isolation
Differential Crosstalk
13-0046
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
5.0 Gbps RX signal eye with PI3PCIE3412
5.0 Gbps RX signal eye without PI3PCIE3412
8.0 Gbps RX signal eye without PI3PCIE3412
13-0046
8.0 Gbps RX signal eye with PI3PCIE3412
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Test Circuit for Electrical Characteristics(1-5)
Switch Positions
3.0V
VDD
200-ohm
Pulse
Generator
VIN
D.U.T
VOUT
4pF
CL
RT
Test
Switch
tPLZ , tPZL
3.0V
tPHZ , tPZH
GND
Prop Delay
Open
200-ohm
Notes:
1. CL = Load capacitance: includes jig and probe capacitance.
2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
5. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
SEL
VDD/2
VDD/2
VDD
0V
Output 1
tPZL
tPLZ
0.75V
1.5V
VOL + 0.15V
tPHZ
tPZH
1.35V
0.75V
VOL
1.5V
VOL
Output 2
Voltage Waveforms Enable and Disable Times
13-0046
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PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
DP1.2 Application
5
3
4
2
C101
C102
C103
C104
C105
C106
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
DP Source 1
1u_0805
D
4.7u_0805
3V3_1
1
At least 1pc 4.7uF and 4pc 0.1uF
decoupling capacitors are
recommended.
Each decoupling capacitor should
be connected to PCB power plane
via shortest path.
D
3V3_1
3V3_1
DP_LANEx
50
DP_LANEx#
C
Same goes for
other 3 lanes
GND
A0+
A0GND
VDD
A1+
A1VDD
SEL
GND
A2+
A2VDD
GND
A3+
A3GND
AUX_N1
AUX_P1
43
42
41
40
39
U101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
(0 - 1.2V)
HEATGND
VDD
GND
VDD
GND
Vbias_TX
VDD
GND
VDD
GND
50
DP
TX
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
B0+
B0B1+
B1C0+
C0C1+
C1VDD
B2+
B2B3+
B3C2+
C2C3+
C3-
C111
0.1u_0402
C112
0.1u_0402
C113
0.1u_0402
C114
0.1u_0402
C115
0.1u_0402
C116
0.1u_0402
C117
0.1u_0402
C118
0.1u_0402
C107
0.1u_0402
C108
1u_0805
C109
C110
0.1u_0402
0.1u_0402
3V3_1
18
19
20
21
C119
DP_AUX
50
AUX
TX
AUX_N2
AUX_P2
VDD and GND pins should be
shorted to PCB power planes
via shortest paths.
(0 - 1.2V)
50
B
DP_AUX#
5V_1
U102
AUX_P1
AUX_P2
DP_AUX
AUX_N1
AUX_N2
DP_AUX#
DP_HPD
1
2
3
4
5
6
7
8
IN
S1A
S2A
DA
S1B
S2B
DB
GND
VDD
#EN
S1D
S2D
DD
S1C
S2C
DC
C123
0.1u_0402
C124
0.1u_0402
C125
0.1u_0402
C126
0.1u_0402
C127
0.1u_0402
C128
5V_1 and 3V3_1 should be
employed at the same time.
AUX
RX
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
16
15
14
13
12
11
10
9
0.1u_0402
C120
1u_0805
C121
C122
0.1u_0402
0.1u_0402
0.1u_0402
C129
0.1u_0402
C130
0.1u_0402
LCD_VCC
LCD_VCC
LCD_VCC
H_GND
AUX_CH_N
AUX_CH_P
H_GND
Lane0_P
Lane0_N
H_GND
Lane1_P
Lane1_N
H_GND
Lane2_P
Lane2_N
H_GND
Lane3_P
Lane3_N
H_GND
NC
LCD_VCC
LCD_Self_Test
LCD_GND
LCD_GND
LCD_GND
LCD_GND
HPD
BL_GND
BL_GND
BL_GND
BL_GND
BL_ENABLE
BL_PWM_DIM
NC
NC
BL_PWR
BL_PWR
BL_PWR
BL_PWR
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HPD1
C
4Lane eDP Source Receptacle
PI3PCIE3412
Vbias_TX
3V3_1
J101
3V3_1
J102
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LCD_VCC
LCD_VCC
LCD_VCC
H_GND
AUX_CH_N
AUX_CH_P
H_GND
Lane0_P
Lane0_N
H_GND
Lane1_P
Lane1_N
H_GND
Lane2_P
Lane2_N
H_GND
Lane3_P
Lane3_N
H_GND
NC
LCD_VCC
LCD_Self_Test
LCD_GND
LCD_GND
LCD_GND
LCD_GND
HPD
BL_GND
BL_GND
BL_GND
BL_GND
BL_ENABLE
BL_PWM_DIM
NC
NC
BL_PWR
BL_PWR
BL_PWR
BL_PWR
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HPD2
B
4Lane eDP Source Receptacle
HPD1
HPD2
DP_HPD
PI5V330
A
C131
A
0.1u_0402
Title
PI3PCIE3412 4Lane eDP 1:2 Application Circuit with
0-1.2Vbias
SEL_GPIO1
Size
Date:
5
13-0046
4
3
9
2
Document Number
Tuesday, March 06, 2012
Rev
A
Sheet
1
of
4
1
www.pericom.com04/15/13
PI3PCIE3412
PCI Express® 3.0 2-Lane,
2:1 Mux/DeMux Switch with Single Enable
Packaging Information
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220.
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DATE: 11/14/12
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH42
DOCUMENT CONTROL #: PD-2035
REVISION:D
12-0529
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Description
PI3PCIE3412ZHE
ZH
Pb-free & Green, 42-contact TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
13-0046
All trademarks are property of their respective owners.
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