PI6C20800

PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Features
Description
• Eight Pairs of Differential Clocks
PI6C20800 is a high-speed, low-noise differential clock buffer
designed to be a companion to PI6C410B. The device distributes
the differential SRC clock from PI6C410B to eight differential
pairs of clock outputs either with or without PLL. The input
SRC clock can be divided by 2 when SRC_DIV# is LOW. The
clock outputs are controlled by input selection of SRC_STOP#,
PWRDWN# and SMBus, SCLK and SDA. When input of either
SRC_STOP# or PWRDWN# is LOW, the output clocks are
Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs
must be Tristated.
• Low skew < 50ps
• Low Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• 100-200 MHz PLL Mode Operation
• 100-400 MHz Bypass Mode Operation
• Packaging (Pb-Free & Green):
— 48-Pin SSOP (V)
— 48-Pin TSSOP (A)
Block Diagram
Pin Configuration
OE_INV
OE [0:7]
SRC_STOP#
PWRDWN#
Output
Control
SCLK
SDA
SMBus
Controller
OUT0
OUT0#
OUT1
OUT1#
OUT2
OUT2#
PLL/BYPASS# OUT3
OUT3#
OUT4
OUT4#
SRC_DIV# SRC
SRC#
PLL_BW#
SRC_DIV#
VDD
VSS
SRC
SRC#
OE_0
OE_3
OUT0
OUT0#
VSS
VDD
OUT1
OUT1#
OE_1
OE_2
OUT2
OUT2#
VSS
VDD
OUT3
OUT3#
PLL/BYPASS#
SCLK
SDA
OUT5
OUT5#
PLL
DIV
OUT6
OUT6#
OUT7
OUT7#
LOCK
12-0205
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
OUT7
OUT7#
OE_INV
VDD
OUT6
OUT6#
OE_6
OE_5
OUT5
OUT5#
VSS
VDD
OUT4
OUT4#
PLL_BW#
SRC_STOP#
PWRDWN#
VSS
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Pin Descriptions
Type
Pin #
SRC_DIV#
Input
1
3.3V LVTTL input for selecting input frequency divide by 2,
active LOW.
SRC & SRC#
Input
4, 5
0.7V Differential SRC input from PI6C410 clock synthesizer
OE [0:7]
Input
6, 7, 14, 15, 35, 36,
43, 44
Pin Name
OE_INV
Descriptions
3.3V LVTTL input for enabling outputs, active HIGH.
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins. When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
Input
40
Output
8, 9, 12, 13, 16 17,
20, 21, 29, 30, 33, 34,
37, 38, 41, 42
PLL/BYPASS#
Input
22
3.3V LVTTL input for selecting fan-out of PLL operation.
SCLK
Input
23
SMBus compatible SCLOCK input
SDA
I/O
24
SMBus compatible SDATA
IREF
Input
46
External resistor connection to set the differential output current
SRC_STOP#
Input
27
3.3V LVTTL input for SRC stop, active LOW
PLL_BW#
Input
28
3.3V LVTTL input for selecting the PLL bandwidth
PWRDWN#
Input
26
3.3V LVTTL input for Power Down operation, active LOW
LOCK
Output
45
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
VDD
Power
2, 11, 19, 31, 39
3.3V Power Supply for Outputs
VSS
Ground
3, 10, 18, 25, 32
Ground for Outputs
VSS_A
Ground
47
Ground for PLL
VDD_A
Power
48
3.3V Power Supply for PLL
OUT[0:7] & OUT[0:7]#
0.7V Differential outputs
Serial Data Interface (SMBus)
PI6C20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
1
1
0
0/1
Data Protocol(1)
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start bit
Slave
Addr
R/W
Ack
Register
offset
Ack
Byte
Count
=N
Ack
Data
Byte 0
Ack
Data
Byte N
-1
Ack
Stop
bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
12-0205
2
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Data Byte 0: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Pin
0
SRC_DIV#
0 = Divide by 2
1 = Normal
RW
1 = x1
OUT[0:7], OUT[0:7]#
NA
1
PLL/BYPASS#
0 = Fanout
1 = PLL
RW
1 = PLL
OUT[0:7], OUT[0:7]#
NA
2
PLL Bandwidth
0 = HIGH Bandwidth,
1 = LOW Bandwidth
RW
1 = Low
OUT[0:7], OUT[0:7]#
NA
3
TBD
NA
4
TBD
NA
5
TBD
NA
6
SRC_STOP#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
7
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:7], OUT[0:7]#
NA
Type
Power Up Condition
Output(s) Affected
Pin
0
RW
1 = Enabled
OUT0, OUT0#
NA
1
RW
1 = Enabled
OUT1, OUT1#
NA
RW
1 = Enabled
OUT2, OUT2#
NA
RW
1 = Enabled
OUT3, OUT3#
NA
RW
1 = Enabled
OUT4, OUT4#
NA
RW
1 = Enabled
OUT5, OUT5#
NA
6
RW
1 = Enabled
OUT6, OUT6#
NA
7
RW
1 = Enabled
OUT7, OUT7#
NA
Data Byte 1: Control Register
Bit
Descriptions
2
OUTPUTS enable
1 = Enabled 0 = Disabled
3
4
5
12-0205
3
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Data Byte 2: Control Register
Bit
Type
Power Up Condition
Output(s) Affected
Pin
0
RW
0 = Free running
OUT0, OUT0#
NA
1
RW
0 = Free running
OUT1, OUT1#
NA
RW
0 = Free running
OUT2, OUT2#
NA
RW
0 = Free running
OUT3, OUT3#
NA
RW
0 = Free running
OUT4, OUT4#
NA
RW
0 = Free running
OUT5, OUT5#
NA
6
RW
0 = Free running
OUT6, OUT6#
NA
7
RW
0 = Free running
OUT7, OUT7#
NA
Type
Power Up Condition
Output(s) Affected
Pin
Type
Power Up Condition
Output(s) Affected
Pin
0
R
0
NA
NA
1
R
0
NA
NA
2
R
0
NA
NA
R
0
NA
NA
R
0
NA
NA
5
R
1
NA
NA
6
R
0
NA
NA
7
R
0
NA
NA
2
3
4
5
Descriptions
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
Data Byte 3: Control Register
Bit
Descriptions
0
RW
1
RW
2
RW
3
TBD
4
RW
RW
5
RW
6
RW
7
RW
Data Byte 4: Pericom ID Register
Bit
Descriptions
3
Pericom ID
4
12-0205
4
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Functionality
PWRDWN#
OUT
OUT#
SRC_Stop#
OUT
OUT#
1
Normal
Normal
1
Normal
Normal
0
IREF × 2 or Float
LOW
0
IREF × 6 or Float
LOW
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
12-0205
5
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Current-mode output buffer characteristics of OUT[0:7], OUT[0:7]#
VDD
(3.3V ± 5%)
Slope ~ 1/Rs
RO
IOUT
ROS
Iout
0V
VOUT = 0.85V max
0.85V
Figure 9. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol
Minimum
Maximum
RO
3000Ω
N/A
ROS
unspecified
unspecified
VOUT
N/A
850mV
Current Accuracy
Symbol
Conditions
Configuration
IOUT
VDD = 3.30 ±5%
RREF = 475Ω 1%
IREF = 2.32mA
Load
Nominal test load for given
configuration
Min.
Max.
-12%
INOMINAL
+12%
INOMINAL
Note:
1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
Reference R, Iref = VDD/(3xRr)
Output Current
VOH @ Z
100Ω
(100Ω differential ≈ 15% coupling ratio)
RREF = 475Ω 1%,
IREF = 2.32mA
IOH = 6 x IREF
0.7V @ 50
12-0205
6
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Absolute Maximum Ratings(1) (Over operating free-air temperature range)
Symbol
VDD_A
Parameters
Min.
Max.
3.3V Core Supply Voltage
-0.5
4.6
VDD
3.3V I/O Supply Voltage
-0.5
4.6
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
-0.5
Ts
Storage Temperature
-65
VESD
4.6
ESD Protection
150
2000
Units
V
°C
V
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Parameters
VDD_A
Min.
Max.
3.3V Core Supply Voltage
3.135
3.465
VDD
3.3V I/O Supply Voltage
3.135
3.465
VIH
3.3V Input HIGH Voltage
2.0
VDD + 0.3
VIL
3.3V Input LOW Voltage
VSS – 0.3
0.8
IIK
Input Leakage Current
0 < VIN < VDD
-5
+5
VOH
3.3V Output HIGH Voltage
IOH = -1mA
2.4
VOL
3.3V Output LOW Voltage
IOL = 1mA
IOH
Output HIGH Current
IOH = 6 x IREF,
IREF = 2.32mA
CIN
Logic Input Pin Capacitance
COUT
Output Pin Capacitance
6
LPIN
Pin Inductance
7
IDD
Power Supply Current
VDD = 3.465V, FCPU = 200MHz
250
ISS
Power Down Current
Driven outputs
60
ISS
Power Down Current
Tristate outputs
12
TA
Ambient Temperature
12-0205
Condition
VDD
0.4
12.2
15.6
1.5
0
7
5
70
PS8746G
Units
V
µA
V
mA
pF
nH
mA
°C
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
AC Switching Characteristics(1,2,3) (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
FIN
Trise / Tfall
∆Trise /
∆Tfall
Parameters
Min
Max.
Units
PLL Mode
100
200
MHz
Bypass Mode
100
400
MHz
Rise and Fall Time (measured between 0.175V to 0.525V)
175
700
Notes
2
ps
Rise and Fall Time Variation
125
Tskew
Output-to-Output Skew
50
VHIGH
Voltage HIGH
VOVS
Max. Voltage
VUDS
Min. Voltage
-300
VLOW
Voltage LOW
-150
+150
Vcross
Absolute crossing poing voltages
250
550
2
140
2
∆Vcross
TDC
Tjcyc-cyc
660
ps
850
2
3
2
1150
Total Variation of Vcross over all edges
Duty Cycle
45
Jitter, Cycle-to-cycle (PLL Mode, Measurement for differential
waveform)
mV
55
%
50
ps
2
3
Jitter, Cycle-to-cycle (BYPASS mode as additive jitter)
Notes:
1. Test configuration is RS = 33.2Ω, Rp = 49.9Ω, and 2pF.
2. Measurement taken from Single Ended waveform. 3. Measurement taken from Differential waveform.
Configuration Test Load Board Termination
Rs
33Ω
5%
OUT
TLA
PI6C20800
Rs
33Ω
5%
OUT#
TLB
475Ω
1%
12-0205
Rp
49.9Ω
1%
Rp
49.9Ω
1%
8
2pF
5%
2pF
5%
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Packaging Mechanical: 48-Pin SSOP (V)
DATE: 09/27/11
Notes:
1. All dimensions are in inches
2. JEDEC outline : MO-118 AA.
3. Dimensions E and D do not include mold protrusion.
DESCRIPTION: 48-Pin, 300-Mil Wide, SSOP
PACKAGE CODE: V (V48)
DOCUMENT CONTROL #: PD-1401
REVISION:F
11-0197
12-0205
9
PS8746G
05/14/12
PI6C20800
1:8 Clock Driver for Intel
PCI Express® Chipsets
Packaging Mechanical: 48-Pin TSSOP (A)
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
.496 12.6
See Note 3
.047
1.20 Max
SEATING PLANE
1
.004 0.09
.008 0.20
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
.007
.010
.0197
BSC
0.50
0.45 .018
0.75 .030
.002
.006
0.05
0.15
0.17
0.27
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.15mm per side.
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
.319
BSC
8.1
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Ordering Information(1,2)
Ordering Code
Package Code
Package Description
PI6C20800VE
V
48-pin, 300-mil wide, SSOP, Pb-Free and Green
PI6C20800AE
A
48-pin, 240-mil wide, TSSOP, Pb-Free and Green
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
12-0205
All trademarks are property of their respective owners.
10
PS8746G
05/14/12