PERICOM PI6C20400H

PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Features
Description
• Four Pairs of Differential Clocks
Pericom Semiconductors PI6C20400 is a high-speed, low-noise
differential clock buffer designed to be companion to PI6C410B.
The device distributes the differential SRC clock from PI6C410B
to four differential pairs of clock outputs either with or without
PLL. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is low, the output
clocks are Tristated. When PWRDWN# is low, the SDA and
SCLK inputs must be Tristated.
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Packaging:
- 28-Pin SSOP (H) & 28-Pin TSSOP (L)
- Pb-Free and Green Option (HE and LE)
Block Diagram
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
SCLK
SDA
Pin Configuration
Output
Control
OUT0
OUT0#
OUT0
OUT1#
SMBus
Controller
OUT2
OUT2#
PLL/BYPASS#
OUT3
OUT3#
SRC
SRC#
PLL_BW#
VDD
SRC
SCR#
VSS
VDD
OUT0
OUT0#
OE_0
OUT1
OUT1#
VDD
PLL/BYPASS#
SCLK
SDA
PLL
DIV
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD_A
VSS_A
IREF
OE_INV
VDD
OUT3
OUT3#
OE_3
OUT2
OUT2#
VDD
PLL_BW#
SRC_STOP#
PWRDWN#
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Pin Descriptions
Type
Pin Name
Pin No
Description
SRC & SRC#
Input
2, 3
0.7V Differential SRC input from PI6C410 clock synthesizer
OE_0 & OE_3
Input
8, 21
3.3V LVTTL input for enabling outputs, active high.
OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
OE_INV
Input
25
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted.
OUT[0:3] & OUT[0:3]#
Output
6, 7, 9, 10, 19, 20,
22, 23
0.7V Differential outputs
PLL/BYPASS#
Input
12
3.3V LVTTL input for selecting fan-out of PLL operation.
SCLK
Input
13
SMBus compatible SCLOCK input
SDA
I/O
14
SMBus compatible SDATA
IREF
Input
26
External resistor connection to set the differential output current
SRC_STOP#
Input
16
3.3V LVTTL input for SRC stop, active low
PLL_BW#
Input
17
3.3V LVTTL input for selecting the PLL bandwidth
PWRDWN#
Input
15
3.3V LVTTL input for Power Down operation, active low
VDD
Power
1, 5, 11, 18, 24
3.3V Power Supply for Outputs
VSS
Ground
4
Ground for Outputs
VSS_A
Ground
27
Ground for PLL
VDD_A
Power
28
3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C20400 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
1
1
0
0/1
Data Protocol
1 bit
7 bits
1
1
8 bits
1
8 bits
1
8 bits
1
Start
bit
Slave
Addr
R/W
Ack
Register
offset
Ack
Byte
Count
=N
Ack
Data
Byte 0
Ack
…
8 bits
1
1 bit
Data
Byte N
-1
Ack
Stop
bit
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
2
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 0: Control Register
Bit
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
0
Outputs Mode
0 = Divide by 2
1 = Normal
RW
1 = Normal
OUT[0:3], OUT[0:3]#
NA
1
PLL/BYPASS#
0 = Fanout
1 = PLL
RW
1 = PLL
OUT[0:3], OUT[0:3]#
NA
2
PLL Bandwidth
0 = High Bandwidth,
1 = Low Bandwidth
RW
1 = Low
OUT[0:3], OUT[0:3]#
NA
3
TBD
NA
4
TBD
NA
5
TBD
NA
6
SRC_STOP#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
7
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
NA
Type
Power Up Condition
Output(s) Affected
Source
Pin
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
1 = Enabled
OUT0, OUT0#
NA
RW
1 = Enabled
OUT1, OUT1#
NA
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
1 = Enabled
OUT2, OUT2#
NA
RW
1 = Enabled
OUT3, OUT3#
NA
Data Byte 1: Control Register
Bit
Descriptions
0
1
2
3
4
5
6
7
3
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 2: Control Register
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
0 = Free running
OUT0, OUT0#
NA
RW
0 = Free running
OUT1, OUT1#
NA
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
0 = Free running
OUT2, OUT2#
NA
RW
0 = Free running
OUT3, OUT3#
NA
Type
Power Up Condition
Output(s) Affected
Source
Pin
Type
Power Up Condition
Output(s) Affected
Pin
0
R
0
NA
NA
1
R
0
NA
NA
2
R
0
NA
NA
R
0
NA
NA
R
0
NA
NA
5
R
1
NA
NA
6
R
0
NA
NA
7
R
0
NA
NA
Bit
0
1
2
3
4
5
6
7
Data Byte 3: Control Register
Bit
Descriptions
0
RW
1
RW
2
RW
3
4
TBD
RW
RW
5
RW
6
RW
7
RW
Data Byte 4: Pericom ID Register
Bit
3
4
Descriptions
Pericom ID
4
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Functionality
PWRDWN#
OUT
OUT#
SRC_Stop#
OUT
OUT#
1
Normal
Normal
1
Normal
Normal
0
IREF × 2 or Float
Low
0
IREF × 6 or Float
Low
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
5
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]#
VDD
(3.3V ± 5%)
Slope ~ 1/Rs
RO
IOUT
ROS
Iout
0V
VOUT = 0.85V max
0.85V
Figure 9. Simplified diagram of current-mode output buffer
Differential Clock Buffer characteristics
Symbol
Minimum
Maximum
RO
3000Ω
N/A
ROS
unspecified
unspecified
VOUT
N/A
850mV
Current Accuracy
Symbol
Conditions
Configuration
IOUT
VDD = 3.30 ±5%
RREF = 475Ω 1%
IREF = 2.32mA
Load
Nominal test load for given
configuration
Min.
Max.
-12%
INOMINAL
+12%
INOMINAL
Note:
1. INOMINAL refers to the expected current based on the configuration of the device.
Differential Clock Output Current
Board Target Trace/Term Z
Reference R, Iref = VDD/(3xRr)
Output Current
VOH @ Z
100Ω
(100Ω differential ≈ 15% coupling ratio)
RREF = 475Ω 1%,
IREF = 2.32mA
IOH = 6 x IREF
0.7V @ 50
6
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
VDD_A
Parameters
Min.
Max.
3.3V Core Supply Voltage
-0.5
4.6
VDD
3.3V I/O Supply Voltage
-0.5
4.6
VIH
Input High Voltage
VIL
Input Low Voltage
-0.5
Storage Temperature
-65
Ts
VESD
4.6
ESD Protection
150
2000
Units
V
°C
V
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Parameters
VDD_A
Condition
Min.
Max.
3.3V Core Supply Voltage
3.135
3.465
VDD
3.3V I/O Supply Voltage
3.135
3.465
VIH
3.3V Input High Voltage
2.0
VDD + 0.3
VIL
3.3V Input Low Voltage
VSS – 0.3
0.8
IIK
Input Leakage Current
0 < VIN < VDD
-5
+5
VOH
3.3V Output High Voltage
IOH = -1mA
2.4
VOL
3.3V Output Low Voltage
IOL = 1mA
IOH
Output High Current
IOH = 6 x IREF,
IREF = 2.32mA
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
6
LPIN
Pin Inductance
7
IDD
Power Supply Current
VDD = 3.465V, FCPU = 200MHz
200
ISS
Power Down Current
Driven outputs
40
ISS
Power Down Current
Tristate outputs
12
TA
Ambient Temperature
VDD
0.4
12.2
15.6
3
0
7
5
70
PS8744A
Units
V
μA
V
mA
pF
nH
mA
°C
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
AC Switching Characteristics (VDD = 3.3±5%, VDD_A = 3.3±5%)
Symbol
Parameters
Min
Max.
Units
Notes
175
700
ps
2
Trise / Tfall
Rise and Fall Time (measured between 0.175V to 0.525V)
ΔTrise /
ΔTfall
Rise and Fall Time Variation
125
ps
2
Rise/Fall Matching
20
%
2
±250
ps
6.5
ns
Tpd
PLL Mode
Non-PLL Mode
2.5
Tskew
Output-to-Output Skew
50
ps
3
Tjitter
Cycle – Cycle Jitter
50
ps
3
VHIGH
Voltage High including overshoot
660
1150
mV
2
VLOW
Voltage Low including undershoot
-300
mV
2
Vcross
Absolute crossing point voltages
250
550
mV
2
ΔVcross
Total Variation of Vcross over all edges
140
mV
2
TDC
Duty Cycle
55
%
3
45
Notes:
1. Test configuration is Rs = 33.2Ω, Rp = 49.9Ω, and 2pF.
2. Measurement taken from Single Ended waveform.
3. Measurement taken from Differential waveform.
Configuration Test Load Board Termination
Rs
33Ω
5%
OUT
TLA
PI6C20400
Rs
33Ω
5%
OUT#
TLB
475Ω
1%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
8
2pF
5%
2pF
5%
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Packaging Mechanical: 28-Pin, 209-mil wide, 0.65mm pitch SSOP (H)
Packaging Mechanical: 28-Pin, 173-mil wide, 0.65mm pitch TSSOP (L)
28
.169
.177
4.3
4.5
.004
.008
1
.378
.386
9.6
9.8
0.45
0.75
0.09
0.20
.018
.030
.252
BSC
6.4
.047
1.20
Max
SEATING
PLANE
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
.006
0.05
0.15
9
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Ordering Information
Ordering Code
PI6C20400H
PI6C20400HE
PI6C20400L
PI6C20400LE
Package Code
H
HE
L
LE
Package Description
28-pin, 209-mil wide, SSOP
28-pin, 209-mil wide, SSOP, Pb-Free and Green
28-pin, 173-mil wide, TSSOP
28-pin, 173-mil wide, TSSOP, Pb-Free and Green
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
10
PS8744A
06/23/05