PI6LC4833 Clock Generator for Power PC Features Description ÎÎ2.5/3.3V supply voltage The PI6LC4833 implements Pericom's advanced LC VCO technology and is specifically designed for Power PC network processor (Freescale MPC8548, MPC8572, AMCC 460, AMI732). This high performance device is optimized to generate CPU core/ PCI clock, high performance PCIe Gen1/2 Clock, SRIO, Gigabit Ethernet’s MAC and PHY clock. All outputs are generated from 25MHz external clock input or crystal. ÎÎ4 HCSL 100/125/200/250MHz outputs with OE ÎÎ2 LVCMOS 33/50/66/100MHz selectable outputs ÎÎ5 LVCMOS 25MHz or 125MHz outputs ÎÎ1 LVPECL 312.5MHz, 156.25MHz or 125MHz output ÎÎ1 CMOS 156.25MHz or 125MHz output ÎÎ1 LVPECL 125MHz or 25MHz output ÎÎ25MHz crystal or differential input Application ÎÎ0.5ps (typ) RMS integrated phase noise design at 3.3V ÎÎRouter/Switch operation ÎÎOLT, BSC, WLAN, Wireless gateway ÎÎ1.0ps (typ) RMS integrated phase noise design at 2.5V ÎÎWireless operation ÎÎPLL Bypass mode for test ÎÎIndustrial Temperature -40°C to 85°C ÎÎTQFN - 56 package Pin Configuration (56-Pin TQFN) IREF QA0+ QA0VCCA QA1+ QA1- GND QA2+ QA2VCCA QA3+ QA3- GND VDDA1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 OC-B FB0 1 2 41 FA1 FA0 FB1 3 40 OC-A VCCB 4 39 SS1 QB0 5 38 SS0 QB1 6 37 PLL_BYPS VDD_OSC 7 X1 8 GND 36 VSEL_33 35 VCCC1 X2 9 34 QC1 IN+ 10 33 VCCC0 IN- 11 32 IN_Sel 12 31 QC0+ OC-R 13 30 SEL_FREQ3 Sel_Freq2 14 29 QC-C 15 16 17 18 19 20 21 22 23 24 25 26 27 28 QD1 VccD QD2 Sel_Freq1 QD0- QD0+ GND VDD_PLL2 VDDA2 Qref2 VCCR Qref1 Qref0 VccR All trademarks are property of their respective owners. QC0- 11-0074 1 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Block Diagram FB0 FB1 SS1 SS0 I ref F A1 F A0 QA3+ QA3QA2+ QA2QA1+ QA1QA0+ QA0- IN_Sel Divider X1 X2 PLL-BYPS Divider QB0 /QB1 MUX IN+ IN- Ring PLL1 OSC PLL-BYPS Diff LC PLL2 Sel-Freq3 PLL_BYPS Divider OC_A PLL-BYPS QDO+ QDOQD1 IN1 IN2 OC_B QCO+ QCOQC1 Divider S QD2 S OC_C PLL-BYPS OC_R IN1 VSEL_33 Qref0 Qref1 IN2 Qref2 S PLL-BYPS Sel-Freq1 Sel-Freq2 All trademarks are property of their respective owners. 11-0074 2 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Pinout Table Pin Number Pin Name I/O Type Description 44, 45, 47, 48, 50, 51, 53, 54 QA0+, QA0-, QA1+, QA1-, Output QA2+, QA2-, QA3+, QA3- 100/125/200/250MHz HCSL Outputs 5, 6 QB0, QB1 Output 33/50/66/100MHz LVCMOS Outputs 8 X1 Input Crystal Input Pin 9 X2 Output Oscillator Output Pin 10, 11 IN+, IN- Input HCSL/LVPECL/LVDS Inputs Low: X1 and X2 are selected. 12 IN_Sel Input High: IN+ and IN- are selected. The pin has an internal pull-up resistor of 100kΩ. Low: Output buffers are switched to the PLL. 37 PLL_BYPS Input High: Output buffers are switched to the input mux. The pin has an internal pull-down resistor of 100kΩ. 40, 1, 29, 13 OC_A, OC_B, OC_C, Input OC_R Low: Outputs are enabled. High: High impedance mode is selected. The pin has an internal pull-down resistor of 100kΩ. 7 VDD_OSC Power Power for crystal OSC core 21 VDDA2 Power Power for LC PLL2 46, 52, 4, 33, 35, VccA, VccB, VccC0, VccC1 28, 15, 19 VccD, VccR Power Power for output buffers (QA, QB, QC , QD, Qref) 56 VDDA1 Power Power for Ring PLL1 20, 49, 55 GND Power Ground includes external paddle (EPAD). 34, 31, 32 QC1, QC0+ / QC0- Output 125MHz/156.25MHz/312.5MHz LVCMOS and LVPECL 16, 17, 18, 23, 24, 26, 27 Qref0, Qref1, Qref2 , QD0+/QD0-. QD1, QD2 Output 25MHz or 125MHz LVCMOS, or LVPECL (QD0+/QD0-) 42, 41 FA1, FA0 Input QA Bank Output Frequency Selection (see function table). This pin has a built-in pull-down resistor of 100kΩ. 3, 2 FB1, FB0 Input QB Bank Output Frequency Selection (see function table). This pin has a built-in pull-up resistor of 100kΩ. Low: QD 25MHz Output 25 Sel_Freq1 Input High: QD 125MHz Output This pin has a built-in pull-up resistor of 100kΩ. 22 VDD_PLL2 Power Power for PLL2 Core Low: Qref 25MHz Output 14 Sel_Freq2 Input High: 125MHz Output This pin has a built-in pull-down resistor of 100kΩ. All trademarks are property of their respective owners. 11-0074 3 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Pin Number Pin Name I/O Type Description Low: QC 156.25MHz Output High: 125MHz Output 30 Sel_Freq3 Input Floating: Output 312.5MHz (QC1 is HiZ if floating) This pin has a built-in pull-up resistor of 150kΩ and pull-down resistor of 100kΩ. 39, 38 SS1, SS0 Input 43 IREF Input 36 VSEL_33 Input Spread Selection Pin for QA and QB This pin has a built-in pull-up resistor of 100kΩ (see function table). External resistor connection for internal current reference Low: 2.5V mode, High: 3.3V mode This pin has a built-in pull_up resistor of 100kΩ Function Table Output Buffer Frequency (MHz) Selection Pin QA0+/-, QA1+/-, QA2+/-, QA3+/- HCSL x4 100, 125, 200, 250 FA1, FA0 QB1, QB0 CMOS x2 33.3333, 50, 66.6667, 100 FB1, FB0 QC0+/- LVPECL x1 125, 156.25, 312.5 QC1 CMOS x1 125, 156.25, HiZ QD0+/- LVPECL x1 25, 125 QD2 , QD1 CMOS x2 25, 125 Qref2 , Qref1, Qref0 CMOS x3 25, 125 Sel_Freq3 Sel_Freq1 Sel_Freq2 FB1 FB0 QB0 QB1 Output 0 0 33.33MHz 33.33MHz LVCMOS 0 1 66.66MHz 66.66MHz LVCMOS 1 0 100MHz 100MHz LVCMOS 1 1 50MHz 50MHz LVCMOS FA1 FA0 QA0+ /QA0- QA1+ /QA1- QA2+ /QA2- QA3+ /QA3- 0 0 100MHz 100MHz 100MHz 100MHz 0 1 125MHz 125MHz 125MHz 125MHz 1 0 200MHz 200MHz 200MHz 200MHz 1 1 250MHz 250MHz 250MHz 250MHz All trademarks are property of their respective owners. 11-0074 4 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Sel_Freq3 QCx Output_Freq 0 QCx 156.25MHz 1 QCx 125MHz QC0 312.5MHz QC1 HiZ Sel_Freq1 QD0+, QD0- QD2, QD1 Output_Freq 0 LVPECL LVCMOS 25MHz 1 LVPECL LVCMOS 125MHz Sel_Freq2 Qref2, Qref1, Qref0 Output_Freq 0 LVCMOS 25MHz 1 LVCMOS 125MHz SS1 SS0 Spread % 0 0 +/- 0.25 0 1 -0.5 1 0 -0.75 1 1 No spread NC Note: The SS1 and SS0 pins control the spread ratio of both QA and QB. All trademarks are property of their respective owners. 11-0074 5 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature............................................................–65°C to +155°C Operating Temperature ...................................................... –40°C to +85°C Supply Voltage...........................................................................-0.5V to 4.6V ESD Protection (HBM)........................................................................ 2000V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol Parameter Test Conditions Min. Typ. Max. Units VDD_xx OSC, A1, A2, PLL2 2.5V 2.375 - 2.625 V Vcc_x QA, QB, QC , QD,Qref 2.5V 2.375 - 2.625 V VDD_xx OSC, A1, A2, PLL2 3.3V 3.135 - 3.465 V Vcc_x QA, QB, QC , QD,Qref 3.3V 3.135 - 3.465 V IDD Total Power Supply Current - - - 360 mA IDDA1, 2 Individual Analog PLL Current, VDDA1,2 - - - 50 mA PDiss Power Dissipation - - - 1250 mW TA Operating Temperature - -40 - +85 ºC Min. Typ. Max. Units LVCMOS DC Electrical Characteristics (Over Operating Conditions) Symbol Parameter Test Conditions VIH Input High Voltage 2 - VDD+0.3 V VIL Input Low Voltage -0.3 - 0.8 V VOH Output High Voltage IOH = -8mA VDD -0.4 - - V VOL Output Low Voltage IOL = 8mA - - 0.4 V IIH Input High Current VIN = VDD - - 45 µA IIL Input Low Current VIN = 0V -45 - - µA IN-, IN_SEL, FB1, FB0, Sel_Freq1, SS1, SS0, VSEL_33 100 - kΩ Sel_Freq3 150 IN+, PLL_BYPS, OC_A, OC_B, OC_C, OC_R, FA1, FA0, Sel_ Freq2, Sel_Freq3 100 - kΩ R PU Internal Pull Up Resistance R DN Internal Pull Down Resistance ZO Output Impedance All trademarks are property of their respective owners. kΩ VDD = 2.5V - 22 - Ω VDD = 3.3V - 17 - Ω 11-0074 6 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC LVCMOS AC Characteristics (Over Operating Conditions) Symbol Parameter Test Conditions Min. Typ. Max. Units ferror Frequency Synthesis Error - - - 0 ppm Tr /Tf Output Rise/Fall time 20% to 80%, CL =10pF - - 3 ns TDC Output Duty Cycle tDC =tH/tCY, tH =High Pulse Width, tCY =Output Cycle Time, at VDD/2 47 - 53 % 33.33MHz - 70 110 ps 66.67MHz - 80 110 ps 50MHz - 70 100 ps 100MHz - 80 110 ps 25MHz - 80 100 ps - 70 100 ps 33.33MHz - 90 140 ps 66.67MHz - 110 130 ps 50MHz - 100 120 ps 100MHz - 100 120 ps 25MHz - 90 120 ps - 90 130 ps - 0.5 - ps - 1 - ps P-0.1 06/14/11 VDD = 3.3V, QB, SS1= SS0 = 1 VDD = 3.3V, QD, QC1, Qref tjit(CC) 125MHz/ 156MHz Jitter, Cycle-to-Cycle VDD = 2.5V, QB, SS1= SS0 = 1 VDD = 2.5V, QD, QC1, Qref 125MHz/ 156MHz 3.3V Operation QD, QC , Qref (125MHz), 12k~20MHz Jitter RMS Phase Jitter SS1= SS0 = 1 2.5V Operation QD, QC , Qref (125MHz), 12k~20MHz SS1= SS0 = 1 All trademarks are property of their respective owners. 11-0074 7 www.pericom.com PI6LC4833 Clock Generator for Power PC Differential DC Input Characteristics (Over Operating Conditions) Symbol IIH IIL Parameter Input High Current, INInput High Current, IN+ Input Low Current, INInput Low Current, IN+ Test Conditions VIN = VDD =3.465V VIN = 0V Min. Typ. Max. Units - - 5 µA - - 45 µA -45 - - µA -5 - - µA VCOMMON Common Mode Voltage Range - 0.2 - VDD 0.925V V VPK Peak-to-Peak Input Voltage Swing - 0.15 - 1.3 V Min. Typ. Max. Units 1. V IL should not be less than -0.3V 2. Common mode voltage is defined as the cross point of the differential signal HCSL DC Electrical Characteristics (Over Operating Conditions) Symbol VOH Parameter Test Conditions Output High Voltage All frequencies except at 250MHz 660 - 850 mV Only at 250MHz 600 - 850 mV VOL Output Low Voltage - - - 150 mV VCROSS Absolute Crossing Point Voltages - 250 - 550 mV ΔVCROSS Total Variation of VCROSS Overall Edges - - - 140 mV IOH Output High Current with 475Ohm resistor. Connected between IREF pin and GND - 15 - mA All trademarks are property of their respective owners. 11-0074 8 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC HCSL AC Switching Characteristics (1, 2, 3) (Over Operating Conditions) Symbol Parameter Test Conditions Min. Typ. Max. Units ferror Frequency Synthesis Error - - - 0 ppm Tr /Tf Output Rise/Fall time (measured between 0.175V to 0.525V)2 - 175 - 700 ps ΔTr /ΔTf Rise and Fall Time Variation2 - - - 125 ps Tskew Output-to-Output Skew3 - - - 50 ps TDC Output Duty Cycle - 47 - 53 % SS1= SS0 = 1 - - 3.1 ps SS1= SS0 = 1, Low Frequency - - 3.0 ps SS1= SS0 = 1, High Frequency - 0.5 1.0 ps PSRR Power Supply Noise Rejection Ratio with 20mVp-p Input Sine Wave 100kHz to 600kHz2 - - -50 - dBc PLLLBW PLL Loop Bandwidth - - 350 - kHz Min. Typ. Max. Units 3 >1.5MHz-50MHz RMS jitter applying PCIe G2 jitter mask 3 JHF-RMS Using PCIe G3 jitter mask 3 1. Test configuration is Rs=33Ω, Rp=49.9Ω, and 2pF 2. Measurement taken from Single-Ended Waveform 3. Measurement taken from Differential Waveform LVPECL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameter Test Conditions VPP Output peak-peak Voltage - 0.4 - 1 V VOH Output High Voltage - VDD −1.2 - VDD −0.7 V VOL Output Low Voltage - VDD −1.85 - VDD −1.55 V Min. Typ. Max. Units LVPECL AC Switching Characteristics (Over Operating Conditions) Symbol Parameter Test Conditions Tr /Tf Rise/Fall time 20% to 80%, Differential - - 475 ps TDC Duty Cycle Differential 47 - 53 % JPhase RMS Phase Jitter from 12kHz 20MHz At 3.3V with SS1= SS0 = 1 - 0.5 - ps At 2.5V with SS1= SS0 = 1 - 1 - ps P-0.1 06/14/11 All trademarks are property of their respective owners. 11-0074 9 www.pericom.com PI6LC4833 Clock Generator for Power PC HCSL Output Buffer Characteristics VDD (3.3V ± 5%) Slope ~ 1/Rs RO IOUT ROS Iout VOUT = 0.85V max 0V 0.85V Simplified Diagram of Current-Mode Output Buffer HCSL Output Buffer Characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified N/A 850mV VOUT All trademarks are property of their respective owners. 11-0074 10 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Configuration Test Load Board Termination for HCSL Output Rs 33Ω 5% Rs 33Ω 5% Device 475Ω 1% Rp 49.9Ω 1% TLA Clock TLA Clock# 2pF 5% Rp 49.9Ω 1% 2pF 5% Configuration Test Load Board Termination for LVPECL Output VDD ZO = 50Ω TLA 0.1µF Device L = 0 ~ 10in 0.1µF 100Ω TLA ZO = 50Ω 150Ω All trademarks are property of their respective owners. 150Ω 11-0074 11 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Application Notes Crystal circuit connection The following diagram shows PI6LC4833 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 27pF SaRonix-eCera CG2500003 Crystal�(CL�=�18pF) XTAL_OUT C2 33pF Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf All trademarks are property of their respective owners. 11-0074 12 www.pericom.com P-0.1 06/14/11 PI6LC4833 Clock Generator for Power PC Packaging Mechanical: 56-Pin TQFN (ZB) DATE: 10/05/10 Notes: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-137 AE 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area (mesh stencile design is recommended). DESCRIPTION: 56-Pin, Thin Fine Pitch Quad Flat No-lead, TQFN PACKAGE CODE: ZB (ZB56) DOCUMENT CONTROL #: PD-2008 REVISION: G Ordering Information Ordering Code Package Code Package Type Operating Temperature PI6LC4833ZBIE ZB Pb-free & Green, 56-pin 315-mil wide TQFN -40°C + 85°C 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 All trademarks are property of their respective owners. 11-0074 13 www.pericom.com P-0.1 06/14/11