PI6C4911505-07

PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Features
Description
ÎÎ5 LVPECL outputs
The PI6C4911505-07 is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. The device has 2 selectable clock inputs that can accept most differential clock sources.
This device is ideal for systems that need to distribute low jitter
clock signals to multiple destinations.
ÎÎUp to 1.5GHz output frequency
ÎÎUltra low additive phase jitter: < 0.03 ps
(typ) (differential
156.25MHz, 12KHz to 20MHz integration range)
ÎÎTwo selectable inputs
ÎÎLow delay from input to output (Tpd typ. 1.2ns)
Applications
ÎÎSeparate Input output supply voltage for level shifting
ÎÎNetworking systems including switches and Routers
ÎÎ2.5V / 3.3V power supply
ÎÎHigh frequency backplane based computing and telecom
ÎÎIndustrial temperature support
platforms
ÎÎTSSOP-20 package
Pin Configuration (20-Pin TSSOP)
Block Diagram
nEN
Pulldown
D
Q
LE
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
15-0037
1
Q0
1
20
VDD
nQ0
2
19
nEN
Q1
3
18
VDD
nQ1
4
17
nCLK1
Q2
5
16
CLK1
nQ2
6
15
NC
Q3
7
14
nCLK0
nQ3
8
13
CLK0
Q4
9
12
CLK_SEL
nQ4
10
11
VEE
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Pinout Table
Pin #
Pin Name
Q0
1, 2
nQ0
Q1
3, 4
nQ1
Q2
5, 6
nQ2
Q3
7, 8
nQ3
Q4
9, 10
nQ4
Type
Description
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
Output
LVPECL output clock
11
VEE
Power
Negative power supply
12
CLK_SEL
Input
Clock input source selection pin
Input
Differential clock input
-
No Connect
Input
Differential clock input
CLK0
13, 14
nCLK0
15
NC
CLK1
16, 17
nCLK1
18, 20
VDD
Power
Power supply
19
nEN
Input
Synchronizing clock enable. When LOW, clock
outputs enabled. When HIGH, Q outputs are forced
low, nQ outputs forced high.
15-0037
2
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Function Table
Table 1: Input select function
CLK_SEL
Function
0
CLK0, nCLK0
1
CLK1, nCLK1
Table 2: Output Mode select function
Outputs
nEN
Q0:Q4
nQ0:nQ4
1
Disabled; LOW
Disabled; HIGH
0
Enabled
Enabled
Table 3: Input select function
Input
Output
Device Mode
CLK0 / CLK1
nCLK0 / nCLK1
Q0:Q4
nQ0:nQ4
LOW
HIGH
LOW
HIGH
Diff. -> Diff., Non-Inverting
HIGH
LOW
HIGH
LOW
Diff. -> Diff., Non-Inverting
LOW
Biased, Figure 1
LOW
HIGH
S-E -> Diff., Non-Inverting
HIGH
Biased, Figure 1
HIGH
LOW
S-E -> Diff., Non-Inverting
Biased, Figure 1
LOW
HIGH
LOW
S-E -> Diff., Inverting
Biased, Figure 1
HIGH
LOW
HIGH
S-E -> Diff., Inverting
3
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15-0037
PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Storage temperature....................................................-55 to +150ºC
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Supply Voltage to Ground Potential (VDD).............. -0.5 to +4.6V
Inputs (Referenced to GND).............................. -0.5 to VDD+0.5V
Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V
Soldering Temperature (Max of 10 seconds).....................+260ºC
Latch up...................................................................................200mA
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
VDD
Supply Voltage
IDD
Power Supply Current
TA
Ambient Operating Temperature
Test Condition
Min.
Typ.
Max.
3.0
3.3
3.6
2.375
2.5
2.625
Outputs unloaded
-40
Units
V
120
mA
85
°C
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
IIH
Input High current: CLK0, CLK1
IIL
Min.
Max.
Units
Input = VDD
150
uA
Input High current: nCLK0, nCLK1
Input = VDD
150
uA
Input Low current: CLK0, CLK1
Input = GND
-5
uA
Input Low current: nCLK0, nCLK1
Input = GND
-150
uA
CIN
Input capacitance
VIH
Input high voltage
VIL
Input low voltage
-0.3
VID
Input Differential Amplitude PK-PK
0.15
VCM
Common model input voltage
15-0037
Typ.
4
PF
VDD+0.3
VEE+0.5
4
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V
V
VDD -0.85
V
VDD-0.85
V
PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
DC Electrical Specifications - LVCMOS Inputs
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
Input High current
Input = VDD
150
uA
IIL
Input Low current
Input = GND
-150
VIH
Input high voltage
VDD =3.3V
2.0
3.765
V
VIL
Input low voltage
VDD =3.3V
-0.3
0.8
V
VIH
Input high voltage
VDD =2.5V
1.7
VDD+0.3
V
VIL
Input low voltage
VDD =2.5V
-0.3
0.7
V
uA
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
VOH
Output High voltage
VOL
Output Low voltage
Conditions
Min.
VDD =3.3V
2.1
2.6
VDD =2.5V
1.3
1.6
VDD =3.3V
1.3
1.8
Max.
Units
V
V
0.5
VDD =2.5V
15-0037
Typ.
5
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1.0
PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
FOUT
Clock output frequency
LVPECL
1500
MHz
Tr
Output rise time
From 20% to 80%
150
ps
Tf
Output fall time
From 80% to 20%
150
ps
TODC
Output duty cycle
Frequency<650MHz, LVPECL input
used
48
VPP
Output swing Single-ended
Frequency<650MHz
400
Tj
Buffer additive jitter RMS
Differential clock input
TSK
Output Skew
TPD
Propagation Delay
TP2P Skew
Part to Part Skew
52
%
mV
0.03
ps
35
ps
1200
ps
150
ps
Configuration Test Load Board Termination for LVPECL
VDD
ZO = 50Ω
TLA
L = 0 ~ 10in
Device
100Ω
TLA
ZO = 50Ω
150Ω
15-0037
150Ω
6
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Application information
Suggest for Unused Inputs and Outputs
LVCMOS Input Control Pins
Differential Clock Trace Routing
It is suggested to add pull-up=4.7k and pull-down=1k for LVCMOS pins even though they have internal pull-up/down but
with much higher value (>=50k) for higher reliability design.
Always route differential signals symmetrically, make sure
there is enough keep-out space to the adjacent trace (>20mil.). In
156.25MHz XO drives IC example, it is better routing differential trace on component side as the following.
Differential +IN/-IN Input Pins
They can be left floating if not used. Connect them 1k to GND is
optional for the additional protection.
GND
0.1uf
Vcc
Keep out board vias
2
150
3
4
GND
Outputs
156.25M XO
All unused outputs are suggested to be left open and not connected to any trace. This can lower the IC power supply power.
150
*100
5
6
*100 is optional if IC has
GND
REF_IN+
REF_INVDD
Clock IC Device
Power Decoupling & Routing
IC routing for XO drive
VDD Pin Decoupling
Clock timing is the most important component in PCB design,
so its trace routing must be planned and routed as a first priority in manual routing. Some good practices are to use minimum
vias (total trace vias count <4), use independent layers with good
reference plane and keep other signal traces away from clock
traces (>20mil.) etc.
As general design rule, each VDD pin must have a 0.1uF decoupling capacitor. For better decoupling, 1uF can be used. Locating the decoupling capacitor on the component side has better
decoupling filter result as shown below.
14
GND
13
12
0.1uF
11 VDD
0.1uF
GND
VDD
VDD
GND
10
9
8
Decouple cap.
on comp. side
Clock IC Device
Placement of Decoupling caps
15-0037
7
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
LVPECL and LVDS Input Interface
CMOS Clock DC Drive Input
LVPECL and LVDS DC/ AC Input
LVCMOS clock has voltage Voh levels such as 3.3V, 2.5V, 1.8V.
CMOS drive requires a Vcm design at the input: Vcm= ½
(CMOS V) as shown below 7. Rs =22 ~33ohm typically.
LVPECL and LVDS clock input to this IC is connected as shown
below.
LVPECL/ LVDS Input
CMOS DC Input Vcm Design
15-0037
8
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Device LVPECL Output Terminations
LVPECL Output Popular Termination
LVPECL Output AC Thevenin Termination
The most popular LVPECL termination is 150ohm pull-down
bias and 100ohm across at RX side. Please consult ASIC datasheet if it already has 100ohm or equivalent internal termination. If so, do not connect external 100ohm across as shown in
below. This popular termination’s advantage is that it does not
allow any bias through from Vcc. This prevents Vcc system noise
coupling onto clock trace.
LVPECL AC Thevenin terminations require a 150ohm pulldown before the AC coupling capacitor at the source as shown
below. Note that pull-up/down resistor value is swapped compared to previous figure. This circuit is good for short trace
(<5in.) application only.
LVPECL Output AC Thenvenin Termination
LVPECL Output Popular Termination
LVPECL Output Drive HCSL Input
LVPECL Output Thevenin Termination
Using the LVPECL output to drive a HCSL input can be done
using a typical LVPECL AC Thenvenin termination scheme.
Use pull-up/down 450/60ohm to generate Vcm=0.4V for the
HCSL input clock. This termination is equivalent to 50Ohm
load as shown.
Figure below shows LVPECL output Thevenin termination
which is used for shorter trace drive (<5in.), but it takes Vcc bias
current and Vcc noise can get onto clock trace. It also requires
more component count. So it is seldom used today.
LVPECL Thevenin Output Termination
15-0037
LVPECL Output Drive HCSL Termination
9
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
LVPECL Output V_swing Adjustment
It is suggested to add another cross 100ohm at TX side to tune
the LVPECL output V_swing without changing the optimal
150ohm pull-down bias. This form of double termination can
reduce the V_swing in ½ of the original at the RX side. By fine
tuning the 100ohm resistor at the TX side with larger values like
150 to 200ohm, one can increase the V_swing by > 1/2 ratio.
Phase Jitter
Phase noise is short-term random noise attached on the clock
carrier and it is a function of the clock offset from the carrier, for example dBc/[email protected] which is phase noise power
in 1-Hz normalized bandwidth vs. the carrier power @10kHz
offset. Integration of phase noise in plot over a given frequency
band yields RMS phase jitter, for example, to specify phase jitter
<=1ps at 12k to 20MHz offset band as SONET standard specification.
PCIe Ref_CLK Jitter
PCIe reference clock jitter specification requires testing via the
PCI-SIG jitter tool, which is regulated by US PCI-SIG organization. The jitter tool has PCIe Serdes embedded filter to calculate
the equivalent jitter that relates to data link eye closure. Direct
peak-peak jitter or phase jitter test data, normally is higher than
jitter measure using PCI-SIG jitter tool. It has high-frequency
jitter and low-frequency jitter spec. limit. For more information, please refer to the PCI-SIG website: http://www.pcisig.com/
specifications/pciexpress/
LVPECL Output V_swing Adjustment
Device Thermal Calculation
LVPECL V_swing Adjustment using Rs
Figure below shows the JEDEC thermal model in a 4-layer PCB.
Another way to control V_swing is by adding serial Rs. Rs value
is tunable between 22 to 33 ohm depending on application. This
method may reduce the clock drive PCB trace in slower Tr/Tf .
JEDEC IC Thermal Model
Important factors to influence device operating temperature are:
1) The power dissipation from the chip (P_chip) is after subtracting power dissipation from external loads. Generally it can be
the no-load device Idd
LVPECL V_swing Adjustment using Rs
Clock Jitter Definitions
2) Package type and PCB stack-up structure, for example, 1oz
4 layer board. PCB with more layers and are thicker has better
heat dissipation
Total jitter= RJ + DJ
Random Jitter (RJ) is unpredictable and unbounded timing noise
that can fit in a Gaussian math distribution in RMS. RJ test values are directly related with how long or how many test samples
are available. Deterministic Jitter (DJ) is timing jitter that is predictable and periodic in fixed interference frequency. Total Jitter
(TJ) is the combination of random jitter and deterministic jitter:
, where is a factor based on total test sample count. JEDEC std.
specifies digital clock TJ in 10k random samples.
15-0037
10
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Thermal calculation example
To calculate Tj and Tc of PI6CV304 in an SOIC-8 package:
Step 1: Go to Pericom web to find Ja=157 C/W, Jc=42 C/W
http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics/
3) Chassis air flow and cooling mechanism. More air flow M/s
and adding heat sink on device can reduce device final die junction temperature Tj
The individual device thermal calculation formula:
Tj =Ta + Pchip x Ja
Tc = Tj - Pchip x Jc
Step 2: Go to device datasheet to find Idd=40mA max.
Ja ___ Package thermal resistance from die to the ambient air
in C/W unit; This data is provided in JEDEC model simulation.
An air flow of 1m/s will reduce Ja (still air) by 20~30%
Jc ___ Package thermal resistance from die to the package case
in C/W unit
Tj ___ Die junction temperature in C (industry limit <125C
max.)
Step 3: P_total= 3.3Vx40mA=0.132W
Step 4: If Ta=85C
Tj= 85 + Ja xP_total= 85+25.9 = 105.7C
Tc= Tj + Jc xP_total= 105.7- 5.54 = 100.1C
Note:
The above calculation is directly using Idd current without subtracting the load power, so it is a conservative estimation. For
more precise thermal calculation, use P_unload or P_chip from
device Iee or GND current to calculate Tj, especially for LVPECL
buffer ICs that have a 150ohm pull-down and equivalent 100ohm
differential RX load.
Ta ___ Ambiant air température in C
Tc ___ Package case temperature in C
Pchip___ IC actually consumes power through Iee/GND current
Thermal Information
Symbol
Description
QJA
Junction-to-ambient thermal resistance
QJC
Junction-to-case thermal resistance
15-0037
Condition
Still air
84.0 OC/W
17.0 OC/W
11
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PI6C4911505-07 Rev B
03/24/15
PI6C4911505-07
High Performance 1:5 LVPECL Fanout Buffer
Packaging Mechanical: 20-Pin TSSOP (L)
DATE: 05/03/12
DESCRIPTION: 20-pin, 173mil Wide TSSOP
Notes:
1. Refer JEDEC MO-153F/AC
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1311
REVISION: F
12-0373
Ordering Information(1-3)
Ordering Code
Package Code
Package Description
PI6C4911505-07LIE
L
20-pin, TSSOP, Pb-Free and Green
Notes:
1. 1Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
15-0037
12
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PI6C4911505-07 Rev B
03/24/15