PI6C2510A 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Phase-Lock Loop Clock Driver with 10-Clock Outputs Features Description • High-Performance Phase-Lock Loop Clock Distribution that meets 100/134 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications • Allows Clock Input to have Spread Spectrum modulation for EMI reduction • Zero Input-to-Output delay: Distribute One Clock Input to one bank of ten outputs, with an output enable. The PI6C2510A family is a low-skew, low-jitter, phase-lock loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable. • Same pinout as TI CDC2510/2510A • Low jitter: Cycle-to-Cycle jitter ±100ps max. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC • Wide Clock Frequency Range: • Packaging -24-pin TSSOP (L) The PI6C2510A is designed to meet PC100 SDRAM Registered DIMM Specification, for heavy load applications. For test purposes, the PLL can be bypassed by strapping AVCC to ground. The PI6C2510A family has the same pinouts as TI’s CDC2510A/ 2510B, with enhanced rise/fall times, and allowing a Spread Spectrum clock input. Product Pin Configuration Logic Block Diagram AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC G FB_OUT G 10 CLK_IN FB_OUT PLL FB_IN 1Y[0:9] AVCC 1 2 3 4 5 6 7 8 9 10 11 12 24-Pin L 24 23 22 21 20 19 18 17 16 15 14 13 CLK_IN AVCC VCC 1Y9 1Y8 GND GND 1Y7 1Y6 1Y5 VCC FB_IN Functional Table Inputs Outputs G CLK_IN 1Y[0:9] FB_OUT X L L L L H L H H H H H 08-0298 1 PS8306C 11/13/08 PI6C2510A Phase-Lock Loop Clock Driver with 10 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Functions Pin Name Pin No. Type CLK_IN 24 I Reference Clock input. CLK_IN allows spread spectrum of 0.5% underspread. FB_IN 13 I Feedback input. FB_IN provides the feedback signal to the internal PLL G 11 I Output bank enable. When G is LOW, outputs 1Y[09] are disabled to a logic low state. When G is HIGH, all outputs 1Y[0:9] are enabled. FB_OUT 12 O Feedback output. FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs 1Yx, 2Yx. 1Y[0:9] 3 , 4 , 5 , 8 , 9 , 15 16,17,20,21 O Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. AVCC 23 Power Analog power supply. AVCCcan be also used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC 2 , 10 , 14 , 2 2 Power Power supply. GND 6,7,18,19 Ground Ground 08-0298 De s cription 2 PS8306C 11/13/08 PI6C2510A Phase-Lock Loop Clock Driver with 10 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Specifications Absolute maximum ratings over operating free-air temperature range. Symbol Parame te r M in. VI Input voltage range VO Output voltage range M a x. Units VCC +0.5 V –0 . 5 VI_DC DC input voltage +5.0 IO_DC DC output current 100 mA Power Maximum power dissipation at TA =55oC in still air 1.0 W TSTG Storage temperature 15 0 o –65 C Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Parame te r Te s t Conditions ICC VI = VCC or GND; IO = 0 CI VI = VCC or GND VCC M in. Typ. M a x. 3.6V mA 4 3.3V CO Units pF VO = VCC or GND 6 Recommended Operating Conditions Symbol Parame te r M in. M a x. 3. 6 VCC Supply voltage 3 VIH High level input voltage 2 VIL Low level input voltage VI Input voltage 0 VCC TA Operating free- air temperature 0 70 Units V 0. 8 oC Electrical characteristics over recommended operating free-air temperature range. Pull Up/Down Currents of PI6C2510A/PI2510A-134, VCC = 3.0V: Symbol IOH Parame te r Condition M in. M a x. Pull- up current VOUT = 2.4V –1 9 Pull- up current VOUT = 2.0V –3 2 Pull- down current VOUT = 0.8V 28 Pull- down current VOUT = 0.55V 19 Units mA IOL 08-0298 3 PS8306C 11/13/08 PI6C2510A Phase-Lock Loop Clock Driver with 10 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Specifications Timing requirements over recommended ranges of supply voltage and operating free-air temperature. Symbol Parame te r M in. M ax. Units Fclock Clock frequency (PI6C2510A) 25 12 5 Fclock Clock frequency (PI6C2510A- 134) 25 13 4 DCYI Input clock duty cycle 40 60 % 1 ms Stabilization Time after power up MHz Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF Parame te r To (Output) From (Input) tphase error, with and without 0.5% spread spectrum CLK_IN↑ at 100 MHz and 66 MHz Jitter, cycle- to- cycle, with and without 0.5% spread spectrum Any Output or FB_OUT in CLKn, at 100 MHz and 66 MHz Skew, at 100 MHz and 66 MHz Any Y or FB_OUT VCC = 3.3V ±0.30V, 0-70°C Units M in. Typ. M a x. FB_IN↑ –150 +150 Output or FB_OUT in CLKn+1 –100 +100 ps 200 Any Y or FB_OUT Duty cycle 45 55 tR, rise- time, 0.4V to 2.0V 1. 0 tF, fall- time, 2.0V to 0.4V 1. 1 % ns Note: These switching parameters are guaranteed, but not production tested. 08-0298 4 PS8306C 11/13/08 PI6C2510A Phase-Lock Loop Clock Driver with 10 Clock Outputs 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Mechanical Information: Plastic 24-pin Thin Shrink Small-Outline Package (L package). DOCUMENT CONTROL NO. PD - 1312 24 REVISION: E DATE: 03/09/05 .169 .177 4.3 4.5 .004 .008 1 .303 .311 7.7 7.9 0.45 0.75 1 .047 1.20 Max .0256 BSC 0.65 .007 .012 0.19 0.30 .002 .006 SEATING PLANE 0.09 0.20 .018 .030 .252 BSC 6.4 0.05 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AD DESCRIPTION: 24-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L Ordering Information Orde r Code Package Code Package D e s cription PI6C2510ALE L Pb- free & Green, 24- pin TSSO P Notes: 1. 2. 3. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ Number of transistors = TBD E = Pb-free and Green Pericom Semiconductor Corporation • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 08-0298 5 PS8306C 11/13/08