ETC PI6C2510-133E

PI6C2510-133E
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Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
Product Features
Product Description
•
•
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phaselocked loop (PLL) clock driver, distributing high-frequency clock
signals for SDRAM and server applications. By connecting the
feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be
nearly zero. This zero-delay feature allows the CLK_IN input clock
to be distributed, providing one clock input to one bank of ten
outputs, with an output enable.
•
•
•
•
•
•
Operating Frequency up to 150 MHz
Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
Zero Input-to-Output delay: Distribute one Clock Input
to one Bank of Ten outputs, with an output enable.
Low jitter: Cycle-to-Cycle jitter ±75ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V VCC
Package: Plastic 24-pin TSSOP (L)
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AVCC to ground.
Logic Block Diagram
Product Pin Configuration
G
10
CLK_IN
PLL
FB_IN
AGND
VCC
Y0
Y1
Y2
GND
GND
Y3
Y4
VCC
G
FB_OUT
Y[0:9]
FB_OUT
AVcc
1
2
3
4
5
6
7
8
9
10
11
12
24-Pin
L
24
23
22
21
20
19
18
17
16
15
14
13
CLK_IN
AVCC
VCC
Y9
Y8
GND
GND
Y7
Y6
Y5
VCC
FB_IN
Functional Table
Inputs
Outputs
G
Y[0:9]
FB_OUT
L
L
CLK_IN
H
CLK_IN
CLK_IN
1
PS8505
11/13/00
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
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Pin Functions
Pin Name
Pin Numbe r
Type
De s cription
CLK_IN
24
I
Reference Clock input. CLK_IN allows spread spectrum.
FB_IN
13
I
Feedback input. FB_IN provides the feedback signal to the internal PLL
G
11
I
Output bank enable. When G is LOW, outputs Y[0:9] are disabled to
a logic low state. When G is HIGH, all outputs Y[0:9] are enabled.
FB_OUT
12
O
Feedback output. FB_OUT is dedicated for external feedback.
FB_OUT has an embedded series- damping resistor of the same
value as the clock outputs Y[0:9].
Y[0:9]
3,4,5,8,9,15
16 , 17 , 2 0 , 2 1
O
Clock outputs. These outputs provide low- skew copies of
CLK_IN. Each output has an embedded series- damping resistor.
AVCC
23
Power
Analog power supply. AVCC can be also used to bypass the PLL for
test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK_IN buffered directly to the device outputs.
AGND
1
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VCC
2,10,14,22
Power
Power supply
GND
6,7,18,19
Ground
Ground
2
PS8505
11/13/00
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
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DC Specifications
Absolute maximum ratings over operating free-air temperature range.
Symbol
Parame te r
VI
Input voltage range
VO
Output voltage range
M in.
M ax.
Units
VCC + 0.5
- 0.5
V
VI_DC
DC input voltage
+5.0
IO_DC
DC output current
100
mA
Power
Maximum power dissipation at TA = 55oC in still air
1.0
W
TSTG
Storage temperature
150
oC
- 65
Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
Parame te r
Te s t Conditions
ICC
VI = VCC or GND; IO = 0
CI
VI = VCC or GND
VCC
M in.
Typ.
3.6V
M ax.
Units
10
µA
4
3.3V
CO
pF
VO=VCC or GND
6
Recommended Operating Conditions
Symbol
Parame te r
M in.
M a x.
3.6
VCC
Supply voltage
3.0
VIH
High level input voltage
2.0
VIL
Low level input voltage
VI
Input voltage
TA
Operating free- air temperature
Units
V
0.8
0.0
VCC
0
70
o
C
Electrical characteristics over recommended operating free-air temperature range
Pull Up/Down Currents of PI6C2510-133E, VCC = 3.0V
Symbol
IOH
IOL
Parame te r
Condition
M in.
M ax.
Pull- up current
VOUT = 2.4V
- 13.6
Pull- up current
VOUT = 2.0V
- 22
Pull- down current
VOUT = 0.8V
19
Pull- down current
VOUT = 0.55V
13
3
Units
mA
PS8505
11/13/00
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
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AC Specifications
Timing requirements over recommended ranges of supply voltage and operating free-air temperature.
Symbol
FCLK
Parame te r
M in.
M ax.
Units
Input clock frequency
25
150
MHz
Input clock duty cycle
40
60
%
1
ms
Stabilization Time after power up
Switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL=30pF
Parame te r
From
To
VCC = 3.3V ±0.3V, 0-70°C
M in.
Typ.
Units
M ax.
tphase error, with and without
spread spectrum
CLK_IN↑ at 133 MHz
FB_IN↑
–150
+150
Jitter, cycle- to- cycle,
with and without spread
spectrum
Any Output or FB_OUT
in CLK n at 133 MHz
Output or
FB_OUT in
CLKn + 1
–75
+75
Skew, at 133 MHz
Any Y or FB_OUT
ps
15 0
Any Y or
FB_OUT
Duty cycle
45
50
tr, rise- time, 0.4V to 2.0V
1.0
tf, fall- time, 2.0V to 0.4V
1.1
55
%
ns
Note: These switching parameters are guaranteed, but not production tested.
4
PS8505
11/13/00
PI6C2510-133E
Low-Noise, Phase-Locked Loop
Clock Driver with 10 Clock Outputs
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Package Mechanical Information
Plastic 24-pin Thin Shrink Small-Outline Package (L package)
24
.169
.177
1
4.3
4.5
.303
.311
7.7
7.9
.004
.008
.047
1.20
Max
.007
.012
0.19
0.30
.0256
BSC
0.65
.002
.006
0.45
0.75
SEATING
PLANE
0.09
0.20
.018
.030
.252
BSC
6.4
0.05
0.15
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
Ordering Information
Part Numbe r
Ope rating Fre q. Range
Orde ring P/N
PI6C2510- 133E
25 MHz - 150 MHz
PI6C2510- 133EL
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5
PS8505
11/13/00