Passive Delay Line Design Considerations Operating Specifications - Passive Delays Pulse Overshoot (Pos) ............................................ 5% to 10%, typical Pulse Distortion (S) ................................................................ 3% typical Working Voltage .................................................... 25 VDC maximum Dielectric Strength ................................................. 100VDC minimum Insulation Resistance ................................ 1,000 MΩ min. @ 100VDC Temperature Coefficient ..................................... 70 ppm/OC, typical Bandwidth (fC) ............................................................... 0.35/tr approx. Operating Temperature Range ................................... -55O to +125OC Storage Temperature Range ........................................ -65O to +150OC A Passive Delay Line is a special purpose Low Pass Filter designed to delay (phase shift) the input signal by a specified increment of time, and is composed of series inductors and shunt capacitors with values dictated by the line impedance. Lt/N Ct/N Ct/2N Reflections: Loading at taps should be at least 10 times the characteristic impedance to minimize reflections due to transmission line effects. The reflected voltage due to a tap loaded by a resistance, RL, is given by Ct/2N Reflection (%) = 1 - (1 / (1 + Zo/2RL)) Figure 1A. Passive Delay Line Schematic Diagram. In certain applications, mismatches can be used to achieve pulse-shaping requirements. There are three basic rules relating to reflections: Design: This LC network may be used to pass either analog or digital signals whose bandwidth is compatible with the intended range of operation for the delay line. A specific delay and impedance, determine the required LC values of the network: Td = ( Lt x Ct ) ZO = ( Lt / Ct ) 1) No reflections at either terminal of a line which is terminated with its characteristic impedance. Td = Total Delay ( ns ) Figure 2A. Lt = Total Line Inductance ( µH ) 2) A reflection, equal in amplitude and of same polarity to the impinging signal, will occur at the input of a line which is open circuited. ( Rt = infinite, see figures below.) Ct = Total Line Capacitance ( pF ) tr = PW > 2xTd Open: Rt = PW < Td tr o2 - tr i2 2xTd .35 / tr N 3) A reflection, equal in amplitude and of opposite polarity to the impinging signal, will occur at the input of a line which is short circuited. ( Rt = 0, see figures below.) PW > 2xTd Short: Rt = 0 PW < Td (Td / tr)1.36 Attenuation: The output voltage attenuation of a delay line has several contributing factors: 2xTd 2xTd 2xTd Figure 4A. Internal D.C. resistance (DCR) Dielectric and ground plane losses Loading effects at taps Impedance mismatches at terminations Frequency limitations (BW) of delay line Circuit Considerations: To assure delay accuracy and prevent signal distortion, care should be taken to properly integrate the passive delay line into the circuit design. A board trace can load a tap with several picofarads of capacitance which will increase delay, rise time, distortion and attenuation. The designer should calculate inductance and capacitance values of the delay line ( Lt , Ct ) to determine if anticipated board loading is significant. For typical passive delay line applications, the following design criteria provide optimum performance: When the delay line is minimally loaded, properly terminated and the input pulse widths are significantly greater than the line's rise time, attenuation is given by: 1. 2. 3. 4. 5. Attenuation (%) = 1 - (Zo / (Zo + DCR)) Series Connection: Passive delay lines of the same impedance can be connected input-to-output (cascaded) to optimize rise time and/or obtain specific delay values. Termination is required only at the output of the final stage. The rise time of the grouped lines is given by tro = 2xTd Figure 3A. An analog delay line's bandwidth (-3dB attenuation) is related to the network's rise time which is dependent upon the total number (N) of LC sections. The delay-to-rise time ratio is the figure of merit, or Quality Factor, used to characterize delay lines. Generally, the greater figure of merit implies higher number of sections, and therefore higher cost. The bandwidth for the network, and number of sections follow these approximations: 1. 2. 3. 4. 5. Rt ZO = Impedance ( Ohms ) Rise Time: The rise time of a delay line is typically measured from the 10% to 90% points of the leading edge of the output pulse. The measured output risetime ( tr o ) is a function of the input rise time ( tr i ) and the true rise time of the delay line ( tr ): BW Rt = Zo The line should be properly terminated. Minimize tap loading. 10 x ZO min. recommended. Minimize trace lengths to delay line. Circuit should have massive ground plane. All common connections should be used. We encourage you to call and discuss the details of your design with one of our application engineers. We offer quick turnaround on samples, and custom versions are available, generally at no cost for existing package configurations. tr i2 + tr 12 + tr 22 + ... tr N2 APP1_PAS 1/98 Rhombus Industries Inc. 2 15801 Chemical Lane, Huntington Beach, CA 92649-1595 Tel: (714) 898-0960 • Fax: (714) 896-0971 TEST PROBE TEST PROBE PULSE GENERATOR R1 Rg IN HIGH BW (350 MHz min.) OSCILLOSCOPE DELAY LINE UNDER TEST R2 CH A CH B TRIG IN EXTERNAL TRIGGER Rg = GENERATOR SOURCE IMPEDANCE = 50 OHMS R1, R2 = INPUT MATCHING PAD RESISTORS Rt = TERMINATING RESISTOR Zo = DELAY LINES CHARACTERISTIC IMPEDANCE (Rg 2 x Zo) (Zo - Rg) INPUT FALL TIME (Tfi): the elapsed time between the 90% and the 10% points on the trailing edge of the input pulse. Figure 5A. Recommended test circuit for Passive Delay Lines 90% Pos INPUT RISE TIME (Tri): the elapsed time between the 10% and the 90% points on the leading edge of the input pulse. 90% INPUT VOLTAGE (Ei): the amplitude of the input pulse. At Ei 50% Eo Pw 10% S LEADING EDGE: that portion of the pulse which rises from zero to peak amplitude. 50% OUTPUT RISE TIME (Tfo): the elapsed time between the 10% and the 90% points on the leading edge of the output pulse. 10% Tri Tfi Tro OUTPUT FALL TIME (Tfo): the elapsed time between the 90% and the 10% points on the trailing edge of the output pulse. Tfo Td Figure 6A. Passive Delay Line Waveform Parameters OUTPUT VOLTAGE (Eo): the amplitude of the output pulse. PULSE DISTORTION (S): the magnitude of the largest peak amplitude of all spurious responses in either a positive or negative direction occurring in the period after the top of the leading edge of the output pulse and before two time delays (for flat input pulse top). VOH VTrh VTrh Ei Eo V Td V Td Pw VTrl VTrl VOL Tfi Tri Td Tro LH Figure 7A. Td Rhombus Industries Inc. Tfo PULSE OVERSHOOT (Pos): the peak amplitude of overshoot occurring at the top of the leading edge of the output pulse (for flat input pulse top). PULSE WIDTH (Pw): the elapsed time between the 50% points on the leading and trailing edge of a pulse. HL TRAILING EDGE: that portion of the pulse which falls from peak amplitude to zero. Active Delay Line Waveform Parameters Specifications subject to change without notice. DELAY TIME (Td): the elapsed time between the respective 50% points on the leading edges of the input and output pulses. IMPEDANCE (Zo): the effective impedance of the delay line which is equal to the value of the terminating impedance which provides a minimum reflection back to the input of the delay line. R1 = {Rg x Zo} / R2 R2 = Attenuation (At): the difference in peak amplitude between input and output pulses. D.C. RESISTANCE (DCR): The D.C. resistance, in ohms, measured between the input and output of a delay line. OUT Rt = Zo GLOSSARY For other values & Custom Designs, contact factory. 3 APP1_PAS 1/98 15801 Chemical Lane, Huntington Beach, CA 92649-1595 Tel: (714) 898-0960 • Fax: (714) 896-0971

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