A CMOS Fast Settling Time Low-Noise Low- Dropout

A CMOS Fast Settling Time Low-Noise LowDropout Regulator with Current Limiter
Praveen Nadimpalli, Dharma Kadam, Bertan Bakkaloglu, Member, IEEE, Wonseok Oh, Member,
Abstract—This paper presents a low-dropout regulator (LDO)
for portable applications with current limiter. To minimize effect
of bandgap noise, novel low pass filter associate with bandgap
reference circuit, which provides highly filtered reference voltage
and fast settling time, is implemented. Dynamically operating
current limiter using decent current comparator limits output
current. Threshold current of current limiter is set to 230mA of
output load current. The proposed LDO with low pass filter and
current limiter has been implemented in a 0.6um n-well CMOS
process. The proposed LDO dissipates 65uA quiescent current at
150mA full load condition and its output noise, PSR, and load
regulation are 407.8nV/√Hz at 100Hz, 51.2dB at 10kHz, and
43mV/150mA respectively. The maximum transient output
voltage variation is within 3.2% of the output voltage with load
step changes of 150 mA and 1µF output capacitor.
Index Terms—low-dropout regulators, reference voltage, noise,
power supply rejection
ow dropout voltage regulator (LDO) is widely demanded
in portable electronics market. These LDOs require
providing strict characteristics such as low noise, high PSR,
and fast settling time. The baseband and analog sections of RF
transceivers, especially transmitter power control DACs and
receive channel ADCs have finite PSR; therefore, at lower
supply rails, they require power supplies which support high
PSR [1]-[3]. In addition of analog sections, noise and crosscoupling on the power supply line for RF circuitry starts
playing a dominant role in an RF transceiver noise budget.
LDOs should provide low noise power line at low frequencies
to RF circuit [4]-[5].
Conventional LDOs utilize highly filtered voltage
references at their inputs and bypass capacitors at their outputs
in order to minimize output noise of voltage reference which
is dominant noise source of LDO. This required large
Manuscript received June 24, 2008.
W. Oh is with the RF Micro Devices, Inc. Chandler, AZ 85226 USA
(corresponding author to provide phone: 480-612-5900; fax: 480-763-2111; email: woh@ rfmd.com).
P. Nadimpalli is with the RF Micro Devices, Inc. Chandler, AZ 85226 USA
(e-mail: PNadimpalli@ rfmd.com).
D. Kadam is with the RF Micro Devices, Inc. Chandler, AZ 85226 USA (email: dkadam@ rfmd.com).
B. Bakkaloglu, is with Arizona State University, Tempe, AZ 85287 USA. (email: [email protected]).
capacitor, especially the capacitor at their inputs is required
gigantic values more than 1µF, which can not be integrated
and it causes to increase board area. It results in high product
cost as well as slow turn-on time [6]-[7].
In power management IC, in order to protect the IC from an
y damage when an overload condition is happened or the
output of the regulator is shorted, current limiting circuits are
required in LDO design [8]-[9]. The current limiter should
provide fast response and less variation over process and
temperature variation. In this paper, we propose bandgap
voltage reference with novel low pass filter, which provides
highly filtered voltage reference and fast turn-on time. To
protect ICs from overflowing current, current limiting circuit
is implemented.
The remainder of the paper is organized as follows.
Bandgap reference with low pass filter is introduced in Section
II. Section III presents the system and circuit level description
of the proposed LDO design with current limiter. Section IV
presents the silicon evaluation results and conclusion is
addressed Section V.
A. Noise Sources of LDOs
Fig. 1 shows a block diagram of a typical LDO regulator,
which consists of an error amplifier, a pass device, a high
resistance feedback network and an output capacitor Co. The
PMOS regulation FET at the output is configured in commonsource configuration. Due to its high transconductance value
and large geometry device, input referred noise of the
regulation FET, Sn,p(f), can be ignored. The input referred
noise power spectral density (PSD) of the error amplifier is
Fig. 1. Block diagram of a typical LDO regulator depicting major noise
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denoted by Sn,e(f), and total output noise of the voltage
reference is defined by Sn,ref(f). Total output noise spectral
density of the LDO system Sn,o(f) is represented by
⎛ R⎞
⎛R ⎞
Sn,o( f ) = Sn,ref ( f ) +Sn,e( f ) ⎜1+ 1 ⎟ +Sn,R2⎜ 1 ⎟ +Sn,R1
⎝ R2 ⎠
⎝ R2 ⎠
From (1), most critical noise contributor of LDO is
reference noise Sn,ref(f) and its flicker (1/f) noise is most
critical noise source of LDO at low frequencies. Assumed that
target spot noise of LDO at 100Hz is 500nV/√Hz at 100Hz
and the desired output voltage of LDO is 2.8V and reference
input voltage is 1.226V. So, LDO needs around 2.284 gain
stage which is implemented by resistor networks (R1 and R2).
Then, LDO itself provides 100nV/√Hz at 100Hz. So, noise of
reference circuit should not exceed 175nV/√Hz at same
frequency. It means that reference circuit requires also low
noise profile at low frequencies.
To suppress noise of LDOs, two popular techniques can be
applied in standard CMOS process. The first scheme is to use
low pass filter following by reference circuit. Using low pass
filter, however, bandgap reference noise can be suppressed by
sufficient filtering in the expense of increasing setting time
and board area due to large filter capacitor. Another method is
to use circuit technique such as chopper stabilization. This
technique provides excellent noise characteristics, but also
generates unwanted characteristic such as ripple voltage due to
chopper switches. In order to suppress ripple voltage, low pass
filter is also required [10]-[12].
B. Bandgap Reference with Low Pass Filter
Bandgap reference circuit provides very stable voltage
reference in regard to both temperature and power supply
variations. In LDO design, voltage reference circuit is one of
most critical block since it is most dominant contributor of
LDO characteristics such as output voltage accuracy and noise
profile in regard to both temperature and process variation. Fig
2 shows the block diagram of proposed reference circuit with
low pass filter. It consists of bandgap voltage reference, buffer,
comparator, and low pass filter composed with MOS
transistors M2~M3 and Cfilter.
The main key operation of proposed reference circuit
depends on comparator which enables low pass filter. The
comparator compared bandgap voltage VBG and delayed
bandgap signal VBG_d. M1 sets the gate voltage of M3 by Vb so
that M3 operates in subthreshold region and generates high
resistance. When VBG is higher than VBG_d, Vc is zero. Then,
Fig. 2. Block diagram of proposed reference circuit with low pass filter.
Fig 3. Block Diagram of Low Dropout Regulator with Current Limiter.
M2 operates in triode region and generate small resistance.
The corner frequency of low pass filter is located at higher
frequencies and it provides fast settling time since total
resistance of M2 and M3 is almost same as that of M2. Then
after a few µsec delay, VBG_d is higher than VBG. Then Vc is
goes to high voltage. M2 operate in sub threshold region. M2
generate very high resistance in order to set the corner
frequency of low pass filter at lower frequencies without
reference voltage variation since both resistance of M2 and
M3 are high value. So, highly filtered reference voltage with
fast setting time is achieved.
The proposed low-noise LDO (LN-LDO) is composed of a
voltage reference, an error amplifier, regulation FET (MP),
and feedback network. In order to protect overflow current,
current limiter is implemented. Fig. 3 shows the block diagram
of the proposed LDO with current limiter. The following
sections describe the building blocks.
A. Low Dropout Regulator
The proposed LN-LDO consists of error amplifier,
regulation FET and feedback network resistor. Fig 4 shows the
schematic of LN-LDO. To achieve fast transient response,
current boost amplifier is utilized to reduce impedance of VPG
node and provide large output swing and large slewing current
which is a function of transient response time. To assure
stability of LN-LDO, external compensation technique is
adopted by using output capacitor associated with ESR to
introduce zero near unity gain frequency.
Fig 4. Schematic of LN-LDO
Fig 6. Schematic of proposed current limiter
Sn _1/ f ( f ) =
Fig 5. Stability response of proposed LN-LDO.
The loop gain LG(s) of LN-LDO is represented by:
LG ( s ) =
V fb ( f )
Vref ( f )
A(0) (1 + s ω z1 )
(1 + s ω ) ⎡⎣1 + s ω
p2 ⎦
ωp =
2π Co ( rdsmp + Resr )
ω z1 =
2π Co Resr
ω p2
A(0) = Ng m1 g mp ( ro 6 ro8 ) rdsmp
Ng m1 g mp ( ro 6 ro8 )
2π Co
R1 + R2
R1 + R2
WLCox f
⎛ µn ⎞ KM 3 LM 1
⎜⎜ ⎟⎟
⎝ µ p ⎠ WM 1LM 3
⎛ µn ⎞ KM 6 LM 1
⎜⎜ ⎟⎟
⎝ µ p ⎠ WM 1LM 6
Form (4), large geometry input devices (M1 and M2) are
utilized to achieve low noise at the output of LDO. In addition,
M3~M6 are also dominant noise source. Therefore, these
devices should be large geometry to reduce noise at low
2π C p ( ro 6 ro8 )
From (2), external compensation scheme using ESR resistor
associated with output capacitor adds a zero (ωz1) close to ωp2.
Therefore, the lineup for the bandwidths are ωp1<ωp2,
GBW<ωz1. The locations of ωp2 and ωz1 and GBW are quite
close each other. Therefore, the stability of the system can be
achieved although phase margin is less than 60deg. The
minimum phase margin of LN-LDO is around 35deg at full
load condition. Fig 5 shows the simulation results of stability
Assuming that reference noise is completely filtered out,
dominant noise source of LDO is an error amplifier which is
CMOS device. Input refereed noise of single CMOS transistor
is well known as following.
S n ( f ) = 4kT
Cox f
KM 1
Cox f (WL )M 1 Cox f
where γ is noise factor, K is a process dependent constant of
device. W, L, and Cox represent the transistor’s width, length
and oxide capacitance, respectively. From (3), dominant noise
source at low frequencies is second part, which is flicker (1/f)
noise. The dominant flicker noise contributor of proposed
LDO is M1~M6 and input referred 1/f noise from these
devices represents as
B. Current Limiter
In power management ICs, LDO requires current limiter to
protect overflow current. As seen Fig 3, the proposed current
limiter senses the current (Isense) which is ratio of output
current. This sensed current is compared to reference current
(Iref), then, generates control signal (VCL). When Isense is
smaller than Iref, VCL goes to high and Mpull-up device is off.
When Isense is larger than Iref, VCL goes to low and Mpull-up turns
on. So, VPG signal goes back to high level to prevent over
current flow. Fig 6 shows the schematic of proposed current
As seen Fig 3, sensing device MPS is much smaller than
pass device MP. These two devices share the gate-source
voltage and operate as current mirror. So, sensing current
(Isense) is L times smaller than load current (Iref). However,
drain-source voltage mismatch causes the variation of sensing
current over load current. To minimize the difference between
Iout and Isense, the current sensing part utilize regulated current
mirror which is composed with M3~M6 devices and two
resistors in Fig 6. This sensing current is copied to one input
(M13) of current comparator and compared with reference
current of other input (M12). Then, the output of comparator
generates control signal (VCL), which controls the pull-up
device (Mpull-up) in Fig. 3. This current comparator gives faster
response with low current consumption than conventional
voltage reference.
The proposed LN-LDO IC is designed and fabricated in a
0.6µm digital CMOS process with three layers of metal. The
LDO is designed to source a nominal output current of
150mA. With the help of highly filtered bandgap reference,
the output noise of the proposed LDO is quite small value
which is able to utilize supply line for RF application. Fast
settling time reference voltage results in fast turn-on time of
LDO. To protect LDO from overflow current, current limiter
is involved.
Fig. 7 shows the turn-on settling time response of proposed
LN-LDO. The achieved turn-on settling time is 45µsec. This
settling time is around 220 times faster than that of RC filter
which utilized off-chip2.2µF filter capacitor.
Output noise and PSR is measured at the full load
condition. The output noise spectral density is measured to be
407.8nV/√Hz at 100Hz. Fig. 8 shows the measured output
noise spectrum. Fig. 9 shows the transient response to 150mA
load current step. The proposed LN-LDO achieves
43mV/150mA load regulation. Transient response time over
full load step is 12µsec for rising load current and 2µsec for
falling load current. The LDO achieves 52.1dB PSR at 10kHz
offset. Fig. 10 shows the PSR response of the LN-LDO at
150mA loading condition. Fig. 11 shows current limiter
operation. Threshold current of current limiter is 230mA. Fig.
12 shows the micrograph of designed LN-LDO. Table 1
shows the summary of the measured performance of proposed
Fig. 9 Measured load regulation of proposed LN-LDO with 150mA load
current step.
Fig. 10. Measured power supply rejection (PSR) of proposed LN-LDO with
150mA load current.
Fig. 7 Turn-on settling time response of proposed LN-LDO with proposed low
pass filter and conventional RC filter.
Fig. 11. Current limiter operation of proposed LN-LDO.
Fig. 8.Measured LDO output noise comparison with proposed low pass filter
and conventional RC filter at 150mA load current.
Fig. 12. Micrograph of the LN-LDO and associated circuits.
Table 1. Summary of the measured performance.
0.6µm CMOS
Chip Area
228 µm X 151 µm
0.01 ohms
Full Load Transient
Response Time
Turn-on Settling Time
Output Noise
407.8nV/√Hz @100Hz
Max. Output Current Imax
Quiescent Current IQ
Current Efficiency
Current Limit
Power Supply Rejection
>[email protected]
A low noise linear low dropout regulator with a fast settling
response voltage reference and current limiter is presented.
The proposed LN-LDO achieve low noise, fast settling time
under the help of highly filtered voltage reference adopting
novel integrated low pass filter. Current limiter protects LDO
from overflow current.
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