SY89482L 3.3V, 622MHz to 694MHz CML Jitter Attenuator with Internal Termination General Description The SY89482L is a 3.3V, fully differential CML jitter attenuator that accepts a noisy clock between 622MHz and 694MHz, and provides an ultra-low jitter of the input clock signal. Output jitter is typically 1psRMS. The SY89482L includes a 1kHz to 10kHz programmable loop bandwidth so it can accommodate different jitter attenuation applications and PLL requirements. The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC-coupled or DCcoupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For ACcoupled input interface applications, an on-board output reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are compatible with 400mV typical swing into 50Ω loads, with rise/fall times guaranteed to be less than 250ps The SY89482L operates at 3.3V ±10% supply and the output can accommodate 1.8V-3.3V operation with the dedicated output supply. The part is guaranteed to operate over the full industrial temperature range (–40°C to +85°C). The SY89482L is part of Micrel’s Precision Edge® product line. Datasheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge® Features Input frequency matched, low-jitter output I/O frequency range: 622MHz – 694MHz Ultra-low phase noise and jitter performance – <2psRMS output jitter gen (12 kHz-20MHz) – Low phase noise: -80dBc/Hz at 1 kHz offset CML-compatible output signal 3-pin input accepts an AC- or DC-coupled differential input (LVDS, LVPECL, and CML) Unique, Auto-Tune circuitry enables precision frequency calibration. Internal source termination to minimize round-trip reflections Programmable loop bandwidth: 1kHz-10kHz Output enable/disable function Includes Loss of Lock (LOL) output pin 1.8V ±5% to 3.3V ±10% output power supply 3.3V ±10% power supply operation Industrial temperature range: –40°C to +85°C Available in 24-pin (4mm x 4mm) QFN package Applications SONET/SDH Communications 10GbE FEC 10GbE LAN PHY High-end Routers Add-Drop MUXes SAS/SATA Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com April 2008 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Functional Block Diagram April 2008 2 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89482LMG QFN-24 Industrial 482L with Pb-Free bar-line indicator NiPdAu Pb-Free SY89482LMGTR(2) QFN-24 Industrial 482L with Pb-Free bar-line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. VDDA FILTERN FILTERP VDDA GNDA VDDO Pin Configuration GNDA VT VREF-AC BW1 REFIN BW0 /REFIN RESET LOL VDDC /EN VDDO /CLKOUT CLKOUT VDDO GND GNDO GND 24-Pin QFN April 2008 3 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Pin Description Pin Number Pin Name 1 VT Input Termination Center-Tap: Each side of the differential input pair terminates to VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” subsection. 2 VREF-AC Reference Output Voltage: This output biases to VDD-1.4V. It is used when AC-coupling the inputs (IN, /IN). Connect VREF-AC directly to the VT pin. Bypass with 0.01uF low ESR capacitors to VDD. Maximum current source or sink is ±0.5mA. See “Input Interface Applications” subsection. 3, 4 REFIN, Differential Input Pair: This input pair is the differential signal input to the device. Input accepts AC- or DC-coupled differential signals as small as 100mV (200mVpp). Each pin of this pair internally terminates with 50Ω to the VT pin. See Figure 2a. /REFIN 12 /EN 6, 13 GND, Exposed Pad 9, 10 CLKOUT, /CLKOUT Pin Function Single-ended Input: This TTL/CMOS input disables and enables the output. It has an internal pull-down and will default to a logic LOW state if left open. When HIGH, the output is forced into the disable state (Q = LOW and /Q = HIGH). The pull-down current is typically 0.5µA. Ground: These are the ground pins for core and input stage. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. CML Differential Output Pair: Differential buffered output copy of the input signal with very low jitter. The output swing is typically 400mV. The output pair is referenced to VDDO. Output pair can be terminated 100Ω across or 50Ω to VBIAS. See “CML Output Termination” subsection. See Figure 2b. 7 GNDO Ground: This is the ground pin for output stage. GNDO and GND must be connected together on the PCB. 8, 11 VDDO CML Output Driver Power Pins: VDDO enables the output stage to operate from a lower supply voltage than the core synthesizer voltage. These outputs can be powered from 1.8V ±5% to 3.3V ±10% power supply. For applications that only require 3.3V reference output operation, VDDO and VDD pins may be connected to a common power supply. Connect both VDDO pins to same power supply. Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VDD pins as possible. 15 RESET Single-ended Input: Reset is active on the Low-to-High edge of the input pulse. It has an internal pull-down and will default to a logic LOW state if left open. Resetting the part starts an auto-tune sequence to provide output frequency closest to input frequency. Calibration setting is lost on power down. The pull-down current is typically 0.5µA. 14 LOL Single-ended Output: This LVTTL/CMOS output asserts HIGH when the PLL is out of phase lock. LOL is asserted if the PLL frequency deviates more than ±1000ppm for more than 5ms. This prevents false triggering. The Loss of Lock pin can be directly connected to /EN. 20, 21 FILTERN, FILTERP Analog Input: These pins provide reference for PLL loop filter. Connect a LOW ESR capacitor across these pins as close to the device as possible, clear from any supply lines or adjacent signal lines. See “External Loop Filter Considerations” for loop filter values. Loop filter capacitor value depends on I/O frequency selection. Loop filter capacitor layout should include a quiet ground plane under the loop filter capacitor and loop filter (FILTERP, FILTERN) pins. Recommend 1206, X5R, 6.3V ceramic type, +/-30%. See “PLL Loop Filter Capacitor Table”. 18, 23 GNDA Ground: This is an analog ground pin for the PLL. Connect to “quiet” ground. It is internally referenced to the VCO. GNDA and Ground must be shorted on the PCB. 19, 22 VDDA Analog Power: Connect to “quiet” 3.3V ±10% power supply. These pins are not internally connected and must be shorted on the PCB. VDDA internally connects to the VCO. Bypass with 0.1µF//0.01µF low ESR capacitors as close to the pin as possible 16, 17 BW0, BW1 5, 24 VDDC April 2008 Single-ended Input: These LVTTL/CMOS inputs determine the loop bandwidth of the jitter reducing PLL. BWSEL0 and BWSEL1 will default to a logic HIGH state if left open with a typical pull-up current of 1.3µA. See “Loop Bandwidth Table.” Positive Power Supply: VDDC pins are connected to core and input stage that connects to a 3.3V ±10% power supply. Bypass with 0.1µF//0.01µF low ESR capacitors as close to the VCC pins as possible. 4 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L BW1 BW0 Nominal Loop Bandwidth (Hz) 0 0 1k 0 1 2k 1 0 5k 1 1 10k Table 1. Loop Bandwidth Table BW Code 00 01 10 11 BW (kHz) 1 2 5 10 Cext (uF) 4.7 1 0.22 0.15 Table 2. PLL Loop Filter Capacitor Table Offset/loop BW 1kHz 2kHz 5kHz 10kHz Units 100Hz offset -50 -55 -70 -75 dBc/Hz 1kHz offset -65 -65 -75 -80 dBc/Hz 10kHz offset -90 -90 -90 -90 dBc/Hz 100kHz offset -115 -110 -110 -115 dBc/Hz Table 3. Typical Phase Noise Performance (622MHz Input, 622MHz Output) April 2008 5 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Absolute Maximum Ratings(1) Operating Ratings(3) Supply Voltage (VDDA,, VDD, VDDO)............. –0.5V to +4.0V Input Voltage (VIN) ..........................–0.5V to VDDC + 0.4V CML Output Voltage (VOUT) .............-0.5V to VDDO + 0.4V CML Output Current (IOUT) Continuous.......................................................50mA Surge .............................................................100mA Current (VT) Source or sink on VT pin .............................±100mA Input Current Source or sink Current on (Ref-IN, /Ref-IN) ..±50mA Current (VREF) Source or sink current on VREF-AC(2) ..............±1.5mA Maximum Junction Temperature........................... 125°C Lead Temperature (soldering, 20sec.) .................. 260°C Storage Temperature (Ts) ....................–65°C to +150°C ESD (Human Body Model)....................................2000V Supply Voltage (VDDA, VDD)................. +3.0V to +3.60V Output Supply Voltage (VDDO).......... +1.71V to +3.60V Ambient Temperature (TA).................. –40°C to +85°C Package Thermal Resistance(4) QFN Still-air (θJA) ...........................................50°C/W Junction-to-board (ψJB) .......................30.5°C/W DC Electrical Characteristics(5) VDD = 3.3V + 10%, GND = 0V; TA = –40°C to +85°C, RL is 100Ω across the output pair, unless otherwise stated. Symbol Parameter VDD Power Supply Voltage Range Condition Min Typ Max Units 3.0 3.3 3.6 V 3.6 V 85 110 mA 100 115 Ω VDDO Output Voltage Range Isy Total Supply Current 1.71 RDIFF_IN Differential Input Resistance (Ref-IN-to-/Ref-IN) VIH Input HIGH Voltage (Ref-IN-to-/Ref-IN) Ref-IN, /Ref-IN 1.2 VCC V VIL Input LOW Voltage (Ref-IN, /Ref-IN) Ref-IN, /Ref-IN 0 VIH–0.1 V VIN Input Voltage Swing (Ref-IN, /Ref-IN) 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing (|Ref-IN – /Ref-IN|) VREF-AC Output Reference Voltage VT_IN Voltage from Input to VT No load, max. VCC 85 Note 6 0.2 V VDD–1.5 VDD–1.4 VDD–1.3 V 1.28 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. Due to the limited drive capability, use for input of the same package only. 3. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA values are determined for a 4-layer board in still-air number, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating. April 2008 6 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L CML Output DC Electrical Characteristics(7) VDDA, VDD =+3.3V ±10%, VDDO = +1.71V to 3.6V, GND and GNDO = 0V, RL = 100Ω across the outputs; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage VOUT Output Voltage Swing VDIFF_OUT Differential Output Voltage Swing ROUT Output Source Impedance Condition Min Typ Max Units RL = 50Ω to VDDO VDDO-0.13 VDDO-0.085 VDDO-0.04 V RL = 50Ω to VDDO VDDO-0.63 VDDO-0.485 VDDO-0.34 V See Figure 3a 300 400 500 mV See Figure 3b 600 800 1000 mV 40 50 60 Ω Typ Max Units LVTTL/CMOS DC Electrical Characteristics(7) VDDC = 3.3V ±10%, GND = 0V, TA = –40°C to + 85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage Condition Min 2 IIN Input Leakage Current 0V < VIN < 3.6V VOH Output High Voltage IOH/IOL < 4 mA VOL Output Low Voltage IOH/IOL < 4 mA V 0.8 V +5 µA 2.4 V 0.4 V IIH Input HIGH Current -1 3 µA IIL Input LOW Current -5 1 µA Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. April 2008 7 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L AC Electrical Characteristics VDDA, VDDC =+3.3V ±10%, GND and GNDO = 0V, RL = 100Ω across the outputs; Input tr/tf < 400ps; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min fRANGE I/O Frequency Range VIN > 100mV, VOUT > 200mV Clock fVCO Internal VCO frequency LOL Maximum I/O frequency PLL out of Lock, ~4ms sustained I/O difference TLOCK Acquisition Lock Time(8) Max Units 622 694 MHz 1244 1388 MHz -1000 1000 ppm Min VCO frequency 450 ms Max VCO frequency 550 ms 400 ps REFIN tr, tf Input Rise/Fall Times 20% to 80% CLKOUT tr, tf Output Rise/Fall Times 20% to 80% 110 RefIn CDuty Input Duty Cycle 40 CLKOut CDuty Output Duty Cycle 48 BW Loop Bandwidth, locked BW1 = 0, BW0 = 0 BW1 = 0, BW0 = 1 Typ 160 250 ps 60 % 50 52 % 750 1000 1250 Hz 1500 2000 2500 Hz BW1 = 1, BW0 = 0 3750 5000 6250 Hz BW1 = 1, BW0 = 1 7500 10000 12500 Hz Notes: 8. Reset Low-to-High to LOL High-to-Low. April 2008 8 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Jitter Characteristics(9) VDDA, VDD =+3.3V ±10%, GND= 0V, RL = 100Ω across the outputs; Input tr/tf < 400ps; TA = –40°C to +85°C, unless otherwise stated. Contact factory for 1kHz and 2kHz Loop Bandwidth Transfer Characteristics. BW Setting: 1kHz, BW1:0 = 00 Symbol JGen Parameter Condition CLKOUT RMS Jitter Generation Min Typ Max 12kHz to 20MHz (Ideal ref input and supply) 1 2 50kHz to 80MHz (Ideal ref input and supply) 1 2 JTOL Jitter Tolerance FBW Jitter Transfer Bandwidth LBW = 1kHz JP Jitter Peaking <1kHz Units psRMS 10 ns 1000 Hz 0.1 dB Typ Max Units BW Setting: 2kHz, BW1:0 = 01 Symbol Parameter Condition Min JGen CLKOUT RMS Jitter Generation 12kHz to 20MHz (Ideal ref input and supply) 1 2 50kHz to 80MHz (Ideal ref input and supply) 1 2 JTOL Jitter Tolerance FBW Jitter Transfer Bandwidth LBW = 2kHz JP Jitter Peaking <1kHz psRMS 10 ns 2000 Hz 0.1 dB Typ Max Units BW Setting: 5kHz, BW1:0 = 10 Symbol Parameter Condition Min JGen CLKOUT RMS Jitter Generation 12kHz to 20MHz (Ideal ref input and supply) 1 2 50kHz to 80MHz (Ideal ref input and supply) 1 2 JTOL Jitter Tolerance FBW Jitter Transfer Bandwidth LBW = 5kHz JP Jitter Peaking <1kHz psRMS 10 ns 5000 Hz 0.1 dB Typ Max Units BW Setting: 10kHz, BW1:0 = 11 Symbol Parameter Condition Min JGen CLKOUT RMS Jitter Generation 12kHz to 20MHz (Ideal ref input and supply) 1 2 50kHz to 80MHz (Ideal ref input and supply) 1 2 JTOL Jitter Tolerance FBW Jitter Transfer Bandwidth LBW = 10kHz JP Jitter Peaking <1kHz psRMS 10 ns 10,000 Hz 0.1 dB Note: 9. 5k and 10k loop bandwidth settings are recommended due to better jitter performance with jitter bandwidth below 12K Hz. The use of 1k and 2k bandwidth settings may be acceptable in certain applications where jitter bandwidth is limited to above 12K Hz. Please contact the factory for additional information. April 2008 9 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. Functional Description Overall Function The SY89482L is designed to accept a high-jitter signal and provide ultra-low jitter CML-compatible clock signal. Unlike normal buffers, SY89482L does not transfer jitter across making it an ideal solution for precision clock applications. LC Voltage Control Oscillator (VCO) The SY89482L uses an extremely low phase noise VCO to prevent jitter at the output. At low frequencies, the PLL produces more phase noise. To offset this additional noise, the LC VCO provides an extremely low phase noise signal that feeds to an output circuit. Unlike many competitive VCOs, this VCO does not require any external components. External Loop Filter Considerations The SY89482L features an external PLL loop filter that allows users to tailor the PLLs behavior. It is recommended that ceramic capacitors with NOP or X7R dielectric be used because they have very low effective series resistance. The SY89482L uses only a single external filter capacitor. All other filter components are on-chip. Internally, the filter has a resistor in series with the external capacitor and a much smaller capacitor in parallel with the series combination of the internal resistor and external capacitor. The selectable PLL bandwidths from 1kHzto-10kHz allows the user to select between different loop filter values. The external capacitor must be placed as close to the device pins as possible. While laying out the board, keep any supply or signal traces lines away from the capacitor. Loop filter capacitor layout should include a quiet ground plane under the loop filter capacitor and loop filter pins. SY89482L Power Supply Filtering Techniques As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VDDA, VDD, and all VDDO pins should be individually connected using via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Power Supply Scheme, Figure 1, below. Figure 1. Power Supply Scheme Auto-Tuning The SY89482L has an auto-tune circuit that enables precision frequency calibration. Auto-tuning is initiated on a LOW to HIGH transition on the RESET input. Auto-tuning is also initiated during power-up. Autotune requires a valid reference input. Jitter Generation Jitter generation is the amount of jitter generated by the part at the output when there is no jitter present at the input clock. While the VCO and PLL are sources of jitter in a synthesizer, the different loop bandwidth options aid in reducing jitter. The SY89482L guarantees less than 2psRMS. See Jitter characteristics subsection. Phase Noise The SY89482L has very low phase noise at 1kHz offset from the center frequency. Phase noise is measured at the output with a jitter-free signal injected at the input. The loop bandwidth settings have a minor impact on the phase noise values. For 10kHz loop bandwidth, Micrel guarantees the phase noise less than -80dBc/Hz. See Phase Noise curve. April 2008 10 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Phase Noise Characteristics April 2008 11 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. Input and Output Stage SY89482L Single-Ended and Differential Swings Figure 3a. Single-Ended Swing Figure 2a. Simplified Differential Input Buffer Figure 3b. Differential Swing Figure 2b. Simplified CML Output Buffer April 2008 12 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Input Interface Applications Figure 4a. CML Interface (DC-Coupled) Figure 4b. CML Interface (AC-Coupled) Figure 4c. LVPECL Interface (DC-Coupled) Option: May connect VT to VCC Figure 4d. LVPECL Interface (AC-Coupled) April 2008 Figure 4e. LVDS Interface 13 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L CML Output Termination Figure 5a. CML DC-Coupled Termination Figure 5b. CML DC-Coupled Termination Figure 5c. CML AC-Coupled Termination April 2008 14 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L Package Information 24-Pin (4mm x 4mm) QFN Packages Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to ground for proper thermal management April 2008 15 M9999-040808-A [email protected] or (408) 955-1690 Micrel, Inc. SY89482L PCB Thermal Consideration for 24-pin QFN Package (Always solder, or equivalent, the exposed pad to the PCB) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2008 Micrel, Incorporated. April 2008 16 M9999-040808-A [email protected] or (408) 955-1690