STMICROELECTRONICS TDA7427AAD

TDA7427A

AM-FM RADIO FREQUENCY SYNTHESIZER
AND IF COUNTER
ON-CHIP REFERENCE OSCILLATOR AND
PROGRAMMABLE IF COUNTER
VHF INPUT AND PRECOUNTER FOR FREQUENCIES UP TO 290MHz (SUITABLE FOR
DAB APPLICATION)
HF INPUT FOR FREQUENCIES UP TO
64MHz (SHORT WAVE BAND)
IN-LOCK DETECTOR FOR SEARCH/STOP
STATION FUNCTION
STAND-BY MODE FOR LOW POWER CONSUMPTION
HIGH CURRENT SOURCE FOR 0.5ms
LOCK-IN TIME
DIGITAL PORT EXTENSION WITH SIX OUTPUTS FOR FLEXIBILITY IN APPLICATION
FULLY PROGRAMMABLE BY I2C BUS
DESCRIPTION
The TDA7427A is a PLL frequency synthesizer
SO28
TSSOP28
ORDERING NUMBERS: TDA7427AAD (TSSOP28)
TDA7427AAD1 (SO28)
with an additional IF counting system that performs all the functions needed in a complete PLL
radio tuning system for conventional and high
speed RDS tuners. The device has dedicated outputs for IN-LOCK detection and Search/Stop station.
BLOCK DIAGRAM
SWITCH
OUT
FM_IN
24
2
PRECOUNTER
:32/33
HFREF
AM_IN
5 BIT PROG.
COUNTER
SWITCH
AM/FM
19
SWITCH
SWM/DIR
25
OSCOUT
ADDR
SCL
SDA
VDD2
VDD1
GNDDIG
IF_AM
IF_FM
3
INLOCK
DETECTOR
SWITCH
LP1/LP2
1
-
28
DOUT1/INLOCK
LP_HC
LP_AM
LP_FM
SWITCH
SWM/DIR
PHASE
COMP
11 BIT PROG
COUNTER
OSCIN
17
CHARGE
PUMP
+
LP_OUT
VDD1
9
10
REF
OSCILLATOR
16 BIT PROG
COUNTER
4
VREF
20
12
13
I2C BUS
INTERFACE
26
GNDAN
27
21
22
SUPPLY
&
POWER-ON
RESET
14 BIT PROG
COUNTER
TIMER
TEST
LOGIC
CONTROL
14
15
SWITCH
AM/FM
PORT EXTENSION
11-21 BIT PROG COUNTER
16
D95AU372D
July 1998
SSTOP
18
5
6
7
8
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
1/21
TDA7427A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD1
Supply Voltage
- 0.3 to + 7
V
VDD2
Supply Voltage
- 0.3 to + 11
V
300
mW
Ptot
Total Power Dissipation
Tstg
Storage Temperature
- 55 to + 150
o
C
Tamb
Ambient Temperature
-40 to + 85
o
C
PIN CONNECTION
LP_FM
1
28
LPOUT
LP_HC
2
27
VDD2
LP_AM
3
26
GND-AN
VREF
4
25
AM_IN
DOUT3
5
24
FM_IN
DOUT4
6
23
N.C.
DOUT5
7
22
GND-DIG
DOUT6
8
21
VDD1
OSCIN
9
20
ADDR
OSCOUT
10
19
HFREF
N.C.
11
18
DOUT2
SCL
12
17
DOUT1/INLOCK
SDA
13
16
SSTOP
IF_AM
14
15
IF_FM
D95AU374C
THERMAL DATA
Symbol
Rth j-amb
2/21
Parameter
Thermal Resistance Junction-Ambient
TSSOP28
160
SO 28
65
Unit
o
C/W
TDA7427A
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17*
17*
18
19
20
21
22
23
24
25
26
27
28
SYMBOL
LP_FM
LP_HC
LP_AM
VREF
DOUT3
DOUT4
DOUT5
DOUT6
OSCIN
OSCOUT
N.C.
SCL
SDA
IF_AM
IF_FM
SSTOP
DOUT1
INLOCK
DOUT2
HF-REF
ADDR
VDD1
GND-DIG
N.C.
FM_IN
AM_IN
GND-AN
VDD2
LP_OUT
DESCRIPTION
Filter OPAMP input, charge pump output (FM mode)
Filter OPAMP input, charge pump output (high current mode)
Filter OPAMP input, charge pump output (AM mode)
OPAMP reference voltage
Digital Output 3 (open collector)
Digital Output 4 (open collector)
Digital Output 5 (open collector)
Digital Output 6 (open collector)
Reference Oscillator Input
Reference Oscillator Output
Not connected
I 2C bus clock input
I 2C bus data I/O
IF counter HF input
IF counter VHF input
IF counter result output
Digital output 1 (push-pull)
Inlock detector output
Digital Output 2 (open collector)
HF reference pin
I 2C bus address pin
Supply Voltage
Digital ground
Not connected
High frequency input FM
High frequency input AM
Analog ground
Supply Voltage
Filter OPAMP output
* Pin function is selectable by software (see software specification)
3/21
TDA7427A
ELECTRICAL CHARACTERISTICS (Tamb = 25°C; VDD1 = 5V; VDD2 = 10V; fOSC = 4MHz; unless otherwise specified).
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
9.0
11.0
V
4
6
mA
2
3
mA
1
µA
VDD1
Supply Voltage
VDD2
Supply Voltage
IDD1
Supply Current
no output load
2
IDD2
Supply Current
PLL locked
1
IDD1 STB
Supply Current
Standby mode
RF INPUT (AM_IN, FM_IN)
fiAM
Input Frequency AM
Vi = 100mVrms sinusoidal
0.5
64
MHz
fiFM
Input Frequency FM
Vi = 100mVrms sinusoidal
30
200
MHz
30
mVrms
ViMIN
Min Input Voltage AM
0.5 to 16MHz range sinusoidal
ViMAX
Max Input Voltage AM
0.6 to 16MHz range sinusoidal
ViMIN
Min Input Voltage FM
70 to 120MHz range sinusoidal
ViMAX
Max Input Voltage FM
70 to 120MHz range sinusoidal
600
mVrms
30
600
mVrms
mVrms
Zin
Input Impedance FM input
3
4
5
KΩ
Zin
Input Impedance AM input
3
4
5
KΩ
IF COUNTER (IF_AM, IF_FM)
fiAM
Input Frequency range AM
Vi = 100mVrms
0.400
11
MHz
fiAM
Input Frequency range FM
Vi = 100mVrms
10
11
MHz
ViMIN
Min Input Voltage AM IF pin
fin = 455kHz
30
mVrms
30
mVrms
ViMIN
Min Input Voltage FM IF pin
fin = 10.7MHz
ViMAX
Max Input Voltage AM IF pin
fin = 455kHz
600
mVrms
ViMAX
Max Input Voltage FM IF pin
fin = 10.7MHz
600
mVrms
Zin
Input Inpedance FM IF pin
3
4
5
KΩ
Zin
Input Inpedance AM IF pin
3
4
5
KΩ
BUS INTERFACE
Tj
Noise Suppression Time
Constant on SCL, SDA Input
ns
fSCL
SCL Clock Frequency
tAA
SCL Low to SDA Data Valid
300
ns
tbuf
Time the bus must be free for
the new transmission
4.7
µs
START Condition hold time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
4.7
tHD-START
tSU-SDA
Start Condition Setup Time
tHD-DATA
Data Input Hold Time
tSU-DATA
Data Input Setup Time
tR
SDA & SCL Rise Time
tF
SDA & SCL Full Time
tSU-STOP
tDH
4/21
50
400
kHz
µs
1
250
µs
ns
1
0.3
µs
µs
Stop Condition Setup Time
4.7
µs
DATA OUT Time
300
ns
TDA7427A
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
V IL
Input Low Voltage
VIH
Input High Voltage
3
IIN
Input Current
-5
VOUT
Output Voltage SDA
acknowledge
IO = 1.6mA
Typ.
Max.
Unit
1
V
V
0.15
+5
µA
0.4
V
100
ms
OSCILLATOR
tbu
Build Up Time
fout = 4MHz
C in
Internal Capacitance
COUT
Internal Capacitance
fosc = 4MHz
Zin
Input Impedance
fosc = 4MHz
Vin
Input Voltage (for Slave Mode)
fIN = 4 to 13MHz (Sinus)
capacitance coupling
300
fin
Max Input frequency (for Slave
Mode)
VIN = 600mVPP (Sinus)
30
20
pF
20
pF
100
KΩ
VDD
mVpp
MHz
LOOP FILTER (LP_FM, LP_AM, LP_HC, LP_OUT)
IIN
Input Leakage Current (*)
VIN = GND; PDout = Tristate (1)
-1
0.1
1
µA
IIN
Input Leakage Current (*)
VIN = VDD1; PDout = Tristate (1)
-1
0.1
1
µA
0
0.5
V
9.5
10
V
10
30
mA
10
30
mA
V OL
Output Voltage Low
IIN = -0.2mA
VOH
Output Voltage High
IOUT = 0.2mA
IOUT
Output Current Sink
IOUT
Output Current Source
Vout = 0.5 to 9.5V
DOUT1/SSTOP (push-pull outputs)
V OL
Output Voltage Low
IOUT = -0.1mA
VOH
Output Voltage High
IOUT = 0.1mA
0.1
0.2
V
VDD1*0.2
4.9
V
-1
0.1
1
mA
0.2
0.5
V
3
5
mA
DOUT2 to 6 (open collector outputs)
IOUT
Output leakage Current
VOUT = 10V
V OL
Output Voltage Low
IOUT = -1mA
IOUT
Output Current Sink
Vout = 0.5 to 9.5V
1) PD = Phase Detector
(*) LP_FM and LP_HC pins only
5/21
TDA7427A
GENERAL DESCRIPTION
This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning systems. Only a VCO is required to build a complete
PLL system. For auto search/stop operation an IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stage configuration. The first stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit programmable counter.
For LW and MW application, a 16-bit programmable counter is available.
The circuit receives the scaling factors for the programmable counters and the values of the refer2
ence frequencies via a I C bus interface.
The reference frequency is generated by an internal XTAL oscillator followed by the reference divider. The device can operate with XTAL oscillator between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free selectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bits also received via the I2C bus.
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the current values of the charge/pump generator.
IF COUNTER SYSTEM
Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuring cycle times.
The tolerance of the accepted count value is adjustable, to reach an optimum compromise for
search speed and precision of the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter tolerance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-conversion) with 1KHz steps is available.
PLL FREQUENCY SYNTHESIZER
Input Amplifiers
The signals applied on AM and FM inputs are amplified to get a logic level in order to drive the frequency dividers.
The typical input impedance for FM and AM inputs is 4kΩ.
Table 1. Address Organization
MSB
LSB
FUNCTION
SUBAD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PLL CHARGE PUMP
00H
LPIN1/2
CURRH
B1
B0
A3
A2
A1
A0
PLL COUNTER
01H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PLL COUNTER
02H
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PLL REF COUNTER
03H
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PLL REF COUNTER
04H
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
PLL LOCK DETECT
05H
LDENA
INLOCK
D3
D2
D1
D0
PM1
PM0
IFC REF COUNTER
06H
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
IFC REF COUNTER
07H
IFCM1
IFCM0
IRC13
IRC12
IRC11
IRC10
IRC9
IRC8
IFC CONTROL
08H
IFENA
-
-
-
-
EW2
EW1
EW0
IFC CONTROL
09H
IFS2
IFS1
IFS0
CF4
CF3
CF2
CF1
CF0
OSC ADJUST
0AH
-
-
-
OSC4
OSC3
OSC2
OSC1
OSC0
PORT EXTENSION
0BH
-
-
DOUT3
DOUT4
DOUT5
DOUT6
DOUT2
DOUT1
6/21
TDA7427A
Figure 1. FM and AM (SW) operation (swallow mode)
REGISTER
R0 ...R15
OSC IN
fref
PREDIVIDER
:R
fsyn
PD
∆ϕ
TO CHARGE
PUMP
REGISTER
PC0 ...PC4
COUNTER
A
AM IN
REGISTER
PC5 ... P15
PRESCALER
M/M+1
COUNTER
:B
FM IN
D95AU375A
Table 2. Control Register Functions.
REGISTER NAME
FUNCTION
PC
Programmable counter for VCO frequency
RC
Reference counter PLL
IRC
Reference counter IF
IFCM
EW
IFENA
IF counter mode selector
Frequency error window IF counter
Enable IFRC
CF
Center frequency IF counter
IFS
Sampling time IF counter
PM
Stby, FM, AM, AM swallow mode selector
D
LPIN1/2
PLLSTOP
Programmable delay and phase error for lock detector
Loop filter input select
PLL stop
A
Charge pump high current
B
Charge pump low current
LDENA
Lock detector enable
CURRH
Set current high
OSC
Oscillator adjust
DOUT1
Push pull output 5V
DOUT2....6
Open collector output
INLOCK
Lock detector output
7/21
TDA7427A
Figure 2. AM direct mode operation for SW, MW and LW
PREDIVIDER
:R
OSC IN
REGISTER
RC0 ... RC15
AM IN
fref
PHASE
DETECTOR
fsyn
∆ϕ
TO CHARGE
PUMP
REGISTER
PC0 ... PC15
PRESCALER
:C
FM IN
D95AU376A
DIVIDER FROM VCO FREQUENCY TO
REFERENCE FREQUENCY
This divider provides a low frequency fSYN which
phase is compared with the reference frequency
fREF . It is controlled by the registers PC0 to PC4
and PC5 to PC15
OPERATING MODES
Four operating modes are available fo PLL; they
are user programmable with the Mode PM registers (see table below).
PM0
PM1
Operating Mode
0
0
Standby
1
0
AM (swallow)
0
1
AM (direct)
1
1
FM
- Standby mode: in this mode all device functions are stopped. This allows low current
consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V,
and all data registers are set to EFH. The oscillator keeps running.
- FM and AM (SW) Swallow Mode (SW):
in this mode the FM or AM signal is applied to
a 32/33 prescaler, which is controlled by a 5
bit divider ’A’.The 5 bit register (PC0 to PC4)
controls this divider. In parallel the output of
the prescaler is connected to a 11 bit divider
’B’. (PC5 to PC15).
fOSC = (R+1)⋅ fREF
8/21
Dividing range calculation :
fVCO = [ 33 ⋅ A + (B + 1 - A) ⋅ 32 ] ⋅ fREF
fVCO = (32 ⋅ B + A + 32) ⋅ fREF
Important:for correct operationA ≤ 32, B ≥ A,with
A andB variable values of the dividers).
- AM direct mode: the AM signal is applied directly to the 16 bit static divider ’C’. (PC0 to
PC15)
fOSC = (R + 1) ⋅ f REF
Dividing range:
fVCO = (C + 1) ⋅ fREF
THREE STATE PHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
fSYN and fREF. This phase error signal drives the
charge pump current generator (fig. 3)
CHARGE PUMP CURRENT GENERATOR
This stage generates signed pulses of current.
The phase error signal decides the duration and
polarity of those pulses.
The current absolute values are programmable by
A0, A1, A2 registers for high current and B0, B1,
registers for low current.
LOW NOISE CMOS OP-AMP
An internal voltage divider at pin VREF connects
the positive input of the low noise Op-Amp. The
charge pump output connects the negative input.
This internal amplifier in cooperation with external
components can provide an active filter.
TDA7427A
Figure 3. Phase comparator waveforms
Figure 4. IF Counter internal block diagram
IFENA
EW-REGISTER
IF-AM
11-21 BIT COUNTER
CF-REGISTER
IF-FM
OSC
ZD
14 BIT COUNTER
3 BIT COUNTER
IFC-REGISTER
IFS-REGISTER
UP/DOWN COUNTER
DECODE
SSTOP
D95AU377A
9/21
TDA7427A
mode a 1KHz signal is generated. This is followed
by an asynchronous divider to generate different
sampling times (see fig. 4).
The negative input is switchable to three input
pins ( LPIN 1, LPIN 2 and LPIN 3) to increase the
flexibility in application. This feature allows two
separate active filters for different applications
A logical ”1” in the LPIN 1/2 register activates
pin LPIN 1, otherwise pin LPIN 2 is active. While
the high current mode is activated LPIN 3 is
switched on.
Intermediate Frequency Main Counter
This counter is a 11/21 bits synchronous autoreload down-counter. Four bits are programmable
to have the possibility for an adjust to the frequency of the CF filter. The counter length is
automatically adjusted to the chosen sampling
time and the counter mode (AM, FM, AM-UPC).
At the start the counter will be loaded with a defined value which is an equivalent to the divider
value (tsample ⋅ fIF).
If a correct frequency is applied to the IF counter
frequency inputs IF-AM IF-FM, at the end of the
sampling time the main counter is changing its
state from 0 H to 1FFFFFH.
This is detected by a control logic. The frequency
range inside which a successful count results is
detected is adjustable by bits EW 0,1,2.
INLOCK DETECTOR
The charge pump can be switched in low current
mode either via software or automatically by the
inlock detector by setting bit LDENA to ”1”.
The charge pump is forced in low current mode
when a phase difference of 10-40 µsec is
reached.
A phase difference larger then the programmed
values will switch the charge pump immediately in
the high current mode.
Programmable delays are available for inlock detection.
Adjustment of the Measurement Sequence
Time
The precision of the measurements is adjustable
by controlling the discrimination window .
This is adjustable by programming the control
registers EW0...EW2.
The measurement time per cycle is adjustable by
setting the Register IFS0 - IFS2.
IF COUNTER SYSTEM (AM/FM/AM - UPC MODES)
The if counter works in modes controlled by IFCM
register (see table):
IFCM1
IFCM0
FUNCTION
0
0
NOT USED
0
1
FM MODE
1
0
AM MODE
1
1
10.7MHz AM UP
CONVERSION MODE
Adjust of the Frequency Value
The center frequency of the discrimination window is adjustable by the control register ”CF0” to
”CF4”. (see data byte specification).
Typical input impedance for IF inputs is 4KΩ.
A sample timer to generate the gate signal for the
main counter is build with a 14-bit programmable
counter to have the possibility to use any crystal
oscillator frequency. In FM mode 6.25KHz in AM
Port Extension and additional functions
Five digital open collector outputs and one digital
push-pull output are available in application
mode. This digital ports are controlled by the data
bits DOUT1-DOUT6.
Figure 5. I2C Bus timing diagram
tHIGH
tR
tLOW
tR
SCL
tSU-STA
tHD-DAT
tSUBTOP
tSD-DAT
tHD-STA
SDA IN
tAA
tDH
ttxt
SDA OUT
D95AU378
10/21
TDA7427A
ter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the
SDA line to LOW level to indicate it has receive
the eight bits of data correctly.
I2C BUS INTERFACE DESCRIPTION
The TDA7427A supports the I2C bus protocol.
This protocol defines any device that sends data
into the bus as a transmitter and the receiving device as the receiver. The device that controls the
transfer is the master and the device being controlled is the slave. The master always initiates
data transfer and provides the clock to transmit or
receive operations.
Data transfer
During data transfer the TDA7427A samples the
SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA
line must be stable during the SCL LOW to HIGH
transition.
Data Transition
Data transition on the SDA line must only occur
when the clock SCL is low. SDA transitions while
SCL is high will be interpreted as START or
STOP condition.
Device Addressing
To start the communication between two devices,
the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing.
The most significant 6 bits of the slave address
are the device type identifier.
The TDA7427A frequency synthesizer device
type is fixed as ”110001”
The next significant bit is used to address a particular device of the previous defined type connected to the bus. The state of the hardwired A0
pin defines the state of this address bit. So up to
two devices could be connected on the same bus.
The last bit of the instruction defines the type of
operation to be performed:
Start Condition
A start condition is defined by a HIGH to LOW
transition of the SDA line while SCL is at a stable
HIGH level. This START condition must precede
any command and initiate a data transfer onto the
bus. The TDA7427A continuously monitors the
SDA and SCL lines for a valid START and will not
response to any command if this condition has
not been met.
Stop Condition
A STOP condition is defined by a LOW to HIGH
transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminate the communication between the devices and forces the bus interface
of the TDA7427Ainto the initial condition.
- When set to ”1”, a read operation is selected
- When set to ”0”, a write operation is selected
The chip selection is accomplished by setting the
bit of the chip address to the corresponding status
of the A0 input.
All TDA7427A connected to the bus will compare
their own hardwired address with the slave ad-
Acknowledge
Indicates a successful data transfer. The transmitFigure 6. Application with two loop filters
FM VCO
AM VCO
+10V
10µF
AM-FM
IF
100nF
VDD1
VDD2
SCL
CONTROLLER
SDA
19
10nF
10nF
IF_AM
IF_FM
10
1nF
10nF
FM_IN
AM_IN
3.9K
16
11
17
8
9
VDD1
100nF
2
15
3
10µF
Utun
LPOUT
1nF
LP_FM
27K
LP_HC
15K
100K
LP_AM
6.8nF
68nF
VREF
3.3nF
820Ω
1
TDA7427
+5V
20
100nF
6.8nF
4
100nF
13
5
6
OSCIN
14
OSCOUT
4MHz
7
HFREF
12
FM:50KHz
AM:1KHz
INLOCK/DOUT1
SSTOP
DOUT3
10nF
D95AU379B
11/21
TDA7427A
dress being transmitted.
After this comparison, the TDA7427A will generate an ”acknowledge” on the SDA line and will
perform either a read or write operation according
to the state of R/W bit.
following words transmitted to the TDA7427A will
be considered as Data. The internal address will
be automatically incremented. After each word receipt the TDA7427A will answer with an ”acknowledge”.
Write Operation
Following a START condition the master sends a
slave address word with the R/W bit set to ”0”.
The TDA7427A will ”acknowledge” after this first
transmission and wait for a second word (the
word address field).
This 8 bit address field provides an access to any
of the 8 internal addresses. Upon receipt of the
word address the TDA7427A slave device will respond with an ”acknowledge”. At this time, all the
SOFTWARE SPECIFICATION
2
I C Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte (the LSB determines
read/write transmission)
A sub-address byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
1
0
0
0
DATA 1 to DATA n
MSB
C R/W ACK T
T
LSB
T
I
A3 A2 A1 A0 ACK
MSB
LSB
DATA
ACK P
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
C = chip select
T = used for testing (in application mode they have to be ” 0”)
MAX CLOCK SPEED 400kbits/s
CHIP ADDRESS
MSB
1
1
0
0
0
1
C
0
1
LSB
1
FUNCTION
ADDR pin open
ADDR pin connected to VDD
SUBADDRESS
MSB
T3
T2
T1
I
A3
0
0
0
0
0
0
0
0
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
T1, T2, T3 used for testing, in application mode they have to be ”0”
12/21
LSB
A0
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Charge pump control
PLL counter 1 (LSB)
PLL counter 2 (MSB)
PLL reference counter 1 (LSB)
PLL reference counter 2 (MSB)
PLL lockdetector control and PLL mode select
IFC reference counter 1 (LSB)
IFC reference counter 2 (MSB) and IFC mode select
IF counter control 1
IF counter control 2
Oscillator adjust
Port extension
page mode off
page mode enabled
TDA7427A
Data Byte Specification
CHARGE PUMP CONTROL
MSB
D7
LSB
D6
D5
0
D4
FUNCTION
D3
D2
D1
D0
0
0
0
0
High current = 0mA
0
0
0
1
High current = 0.5mA
0
0
1
0
High current = 1.0mA
0
0
1
1
High current = 1.5mA
0
1
0
0
High current = 2.0mA
0
1
0
1
High current = 2.5mA
0
1
1
0
High current = 3.0mA
0
1
1
1
High current = 3.5mA
1
0
0
0
High current = 4.0mA
1
0
0
1
High current = 4.5mA
1
0
1
0
High current = 5.0mA
1
0
1
1
High current = 5.5mA
1
1
0
0
High current = 6.0mA
1
1
0
1
High current = 6.5mA
1
1
1
0
High current = 7.0mA
1
1
1
1
High current = 7.5mA
0
Low current = 0µA
Low current = 50µA
0
1
1
0
Low current = 100µA
1
1
Low current = 150µA
0
Select low Current
1
Select high Current
1
Select loop filter LP_FM
0
Select loop filter LP_AM
LPIN1/2 CURRH
B1
B0
A3
A2
A1
A0
Subaddress = 00H
PLL COUNTER 1 (LSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
LSB = 0
0
0
0
0
0
0
0
1
LSB = 1
0
0
0
0
0
0
1
0
LSB = 2
1
1
1
1
1
1
0
0
LSB = 252
1
1
1
1
1
1
0
1
LSB = 253
1
1
1
1
1
1
1
0
LSB = 254
1
1
1
1
1
1
1
1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
LSB = 255
Bit name
Subaddress = 01H
13/21
TDA7427A
PLL COUNTER 2 (MSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
D0
0
MSB = 0
0
0
0
0
0
0
0
1
MSB = 256
0
0
0
0
0
0
1
0
MSB = 512
1
1
1
1
1
1
0
0
MSB = 64768
1
1
1
1
1
1
0
1
MSB = 65024
1
1
1
1
1
1
1
0
MSB = 65280
1
1
1
1
1
1
1
1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
MSB = 65536
Bit name
Subddress = 02H
Swallow mode: fvco/fsyn = LSB + MSB + 32
Direct mode: fvco/fsyn = LSB + MSB + 1
PLL REFERENCE COUNTER 1 (LSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
LSB = 0
0
0
0
0
0
0
0
1
LSB = 1
0
0
0
0
0
0
1
0
LSB = 2
1
1
1
1
1
1
0
0
LSB = 252
1
1
1
1
1
1
0
1
LSB = 253
1
1
1
1
1
1
1
0
LSB = 254
1
1
1
1
1
1
1
1
LSB = 255
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
Bit name
Subaddress =03H
PLL REFERENCE COUNTER 2 (MSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
D0
0
MSB = 0
0
0
0
0
0
0
0
1
MSB = 256
0
0
0
0
0
0
1
0
MSB = 512
1
1
1
1
1
1
0
0
MSB = 64768
1
1
1
1
1
1
0
1
MSB = 65024
1
1
1
1
1
1
1
0
MSB = 65280
1
1
1
1
1
1
1
1
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
fOSC/fREF = LSB + MSB + 1
14/21
MSB = 65536
Bit name
Subddress = 04H
TDA7427A
LOCK DETECTOR & PLL MODE CONTROL
MSB
D7
LSB
D6
D5
D4
D3
D2
FUNCTION
D1
D0
0
0
PLL standby mode
0
1
PLL AM swallow mode
1
0
PLL AM direct mode
1
1
PLL FM mode
0
0
PD phase difference threshold 10ns
0
1
PD phase difference threshold 20ns
1
0
PD phase difference threshold 30ns
1
1
PD phase difference threshold 40ns
0
0
Not used in application mode
0
1
Activation delay = 4 ⋅ fref
1
0
Activation delay = 6 ⋅ fref
1
1
Activation delay = 8 ⋅ fref
0
Digital output 1 at pin ”dout1/inlock”
1
Inlock information at pin ”dout1/inlock”
0
No lock detector controlled chargepump
1
Lock detector controlled chargepump
LDENA INLOCK
D3
D2
D1
D0
PM1
PM0
Bit name
Subaddress = 05H
IF COUNTER REFERENCE CONTROL 1 (LSB)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
LSB = 0
0
0
0
0
0
0
0
1
LSB = 1
0
0
0
0
0
0
1
0
LSB = 2
1
1
1
1
1
1
0
0
LSB = 252
1
1
1
1
1
1
0
1
LSB = 253
1
1
1
1
1
1
1
0
LSB = 254
1
1
1
1
1
1
1
1
LSB = 255
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
Bit name
Subaddress = 06H
15/21
TDA7427A
IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
MSB = 0
0
0
0
0
0
0
0
1
MSB = 256
0
0
0
0
0
0
1
0
MSB = 512
1
1
1
1
0
1
MSB = 15616
1
1
1
1
1
0
MSB = 15872
1
1
1
1
1
1
MSB = 16128
0
0
NOT USED IN APPLICATION MODE
0
1
IF counter FM mode
1
0
IF counter AM mode
1
1
IF counter AM 10.7MHz upconversion mode
IFCM1 IFCM0 IRC13
IRC12
IRC11
IRC10
IRC9
IRC8
Bit name
D3
D2
D1
D0
0
0
0
don’t use
0
0
1
don’t use
Subaddress = 07H
fosc/ftim = LSB + MSB + 1
IF COUNTER CONTROL 1
MSB
D7
LSB
D6
X
D5
X
D4
X
0
1
1
EW delta f = ±6.25kHz (FM); ±1kHz (AM; AM-UPC)
1
0
0
EW delta f = ±12.5kHz (FM); ±2kHz (AM; AM-UPC)
1
0
1
EW delta f = ±25kHz (FM); ±4kHz (AM; AM-UPC)
1
1
0
EW delta f = ±50Hz (FM); ±8kHz (AM; AM-UPC)
1
1
1
EW delta f = ±100kHz (FM); ±16kHz (AM; AMUPC)
X
don’t use
0
IF counter disabled / stand by
1
FENA
16/21
FUNCTION
IF counter enabled
FR3
FR2
FR1
FR0
EW2
EW1
EW0
Bit name
Subaddress = 08H
TDA7427A
IF COUNTER CONTROL 2
MSB
D7
LSB
D6
D5
FUNCTION
D4
D3
D2
D1
D0
0
0
0
0
0
fcenter = 10.60000MHz (FM) 448KHz (AM) 10.688MHz (AM UPC)
0
0
0
0
1
fcenter = 10.60625MHz (FM) 449KHz (AM) 10.689MHz (AM UPC)
0
0
0
1
0
fcenter = 10.61250MHz (FM) 450KHz (AM) 10.690MHz (AM UPC)
0
0
0
1
1
fcenter = 10.61875MHz (FM) 451KHz (AM) 10.691MHz (AM UPC)
0
0
1
0
0
fcenter = 10.62500MHz (FM) 452KHz (AM) 10.692MHz (AM UPC)
0
0
1
0
1
fcenter = 10.63125MHz (FM) 453KHz (AM) 10.693MHz (AM UPC)
0
0
1
1
0
fcenter = 10.63750MHz (FM) 454KHz (AM) 10.694MHz (AM UPC)
0
0
1
1
1
fcenter = 10.64375MHz (FM) 455KHz (AM) 10.695MHz (AM UPC)
0
1
0
0
0
fcenter = 10.65000MHz (FM) 456KHz (AM) 10.696MHz (AM UPC)
0
1
0
0
1
fcenter = 10.65625MHz (FM) 457KHz (AM) 10.697MHz (AM UPC)
0
1
0
1
0
fcenter = 10.66250MHz (FM) 458KHz (AM) 10.698MHz (AM UPC)
0
1
0
1
1
fcenter = 10.66875MHz (FM) 459KHz (AM) 10.699MHz (AM UPC)
0
1
1
0
0
fcenter = 10.67500MHz (FM) 460KHz (AM) 10.700MHz (AM UPC)
0
1
1
0
1
fcenter = 10.68125MHz (FM) 461KHz (AM) 10.701MHz (AM UPC)
0
1
1
1
0
fcenter = 10.68750MHz (FM) 462KHz (AM) 10.702MHz (AM UPC)
0
1
1
1
1
fcenter = 10.69375MHz (FM) 463KHz (AM) 10.703MHz (AM UPC)
1
0
0
0
0
fcenter = 10.70000MHz (FM) 464KHz (AM) 10.704MHz (AM UPC)
1
0
0
0
1
fcenter = 10.70625MHz (FM) 465KHz (AM) 10.705MHz (AM UPC)
1
0
0
1
0
fcenter = 10.71250MHz (FM) 466KHz (AM) 10.706MHz (AM UPC)
1
0
0
1
1
fcenter = 10.71875MHz (FM) 467KHz (AM) 10.707MHz (AM UPC)
1
0
1
0
0
fcenter = 10.72500MHz (FM) 468KHz (AM) 10.708MHz (AM UPC)
1
0
1
0
1
fcenter = 10.73125MHz (FM) 469KHz (AM) 10.709MHz (AM UPC)
1
0
1
1
0
fcenter = 10.73750MHz (FM) 470KHz (AM) 10.710MHz (AM UPC)
1
0
1
1
1
fcenter = 10.74375MHz (FM) 471KHz (AM) 10.711MHz (AM UPC)
1
1
0
0
0
fcenter = 10.75000MHz (FM) 472KHz (AM) 10.712MHz (AM UPC)
1
1
0
0
1
fcenter = 10.75625MHz (FM) 473KHz (AM) 10.713MHz (AM UPC)
1
1
0
1
0
fcenter = 10.76250MHz (FM) 474KHz (AM) 10.714MHz (AM UPC)
1
1
0
1
1
fcenter = 10.76875MHz (FM) 475KHz (AM) 10.715MHz (AM UPC)
1
1
1
0
0
fcenter = 10.77500MHz (FM) 476KHz (AM) 10.716MHz (AM UPC)
1
1
1
0
1
fcenter = 10.78125MHz (FM) 477KHz (AM) 10.717MHz (AM UPC)
1
1
1
1
0
fcenter = 10.78750MHz (FM) 478KHz (AM) 10.718MHz (AM UPC)
1
1
1
1
1
fcenter = 10.79375MHz (FM) 479KHz (AM) 10.719MHz (AM UPC)
1
1
1
tsample = 160µs (FM mode); 1ms (AM; AM-UPC)
1
1
0
tsample = 320µs (FM mode); 2ms (AM; AM-UPC)
1
0
1
tsample = 640µs (FM mode); 4ms (AM; AM-UPC)
1
0
0
tsample = 1.280ms (FM mode); 8ms (AM; AM-UPC)
0
1
1
tsample = 2.560ms (FM mode); 16ms (AM; AM-UPC)
0
1
0
tsample = 5.120ms (FM mode); 32ms (AM; AM-UPC)
0
0
1
tsample = 10.240ms (FM mode); 64ms (AM; AM-UPC)
0
0
0
IFS2 IFS1 IFS0 CF4
tsample = 20.480ms (FM mode); 128ms (AM; AM-UPC)
CF3
CF2
CF1
CF0 bit same
Subaddress = 09H
17/21
TDA7427A
OSCILLATOR ADJUST
MSB
D7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
D6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
D5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OSC4
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OSC3
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OSC2
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OSC1
D2
D1
LSB
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OSC0
FUNCTION
Cload 1,2 = 3pF
Cload 1,2 = 4.25pF
Cload 1,2 = 5.5pF
Cload 1,2 = 6.75pF
Cload 1,2 = 8pF
Cload 1,2 = 9.25pF
Cload 1,2 = 10.5pF
Cload 1,2 = 11.75pF
Cload 1,2 = 13pF
Cload 1,2 = 14.25pF
Cload 1,2 = 15.5pF
Cload 1,2 = 16.75pF
Cload 1,2 = 18pF
Cload 1,2 = 19.25pF
Cload 1,2 = 20.5pF
Cload 1,2 = 21.75pF
Cload 1,2 = 23pF
Cload 1,2 = 24.25pF
Cload 1,2 = 25.5pF
Cload 1,2 = 26.75pF
Cload 1,2 = 28pF
Cload 1,2 = 29.25pF
Cload 1,2 = 30.5pF
Cload 1,2 = 31.75pF
Cload 1,2 = 33pF
Cload 1,2 = 34.25pF
Cload 1,2 = 35.5pF
Cload 1,2 = 36.75pF
Cload 1,2 = 38pF
Cload 1,2 = 39.25pF
Cload 1,2 = 40.5pF
Cload 1,2 = 41.75pF
Bit name
Subaddress = 0AH
PORT EXTENSION CONTROL
MSB
D7
0
18/21
D6
0
-
D5
D4
D3
LSB
D0
0
1
FUNCTION
CMOS push-pull DOUT1 low
CMOS push-pull DOUT1 high
0
NPN opencollector DOUT2 inactive
1
NPN opencollector DOUT2 active
0
NPN opencollector DOUT6 inactive
1
NPN opencollector DOUT6 active
0
NPN opencollector DOUT5 inactive
1
NPN opencollector DOUT5 active
0
NPN opencollector DOUT4 inactive
1
NPN opencollector DOUT4 active
0
NPN opencollector DOUT3 inactive
1
NPN opencollector DOUT3 active
always ”0” in application mode
DOUT3 DOUT4 DOUT5 DOUT6 DOUT2 DOUT1 Bit name
Subaddress = 0BH
TDA7427A
TSSOP28 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
MAX.
1.20
A1
0.05
A2
0.80
b
0.048
0.15
0.002
1.05
0.031
0.19
0.30
0.007
0.012
c
0.09
0.20
0.0035
0.008
D
9.60
9.80
0.378
1.00
9.70
0.006
0.039
0.041
0.382
E
6.40
0.252
e
0.65
0.026
0.386
E1
4.30
4.40
4.50
0.169
0.173
0.177
L
0.45
0.60
0.75
0.018
0.024
0.030
S
0° (min.) 8° (max.)
E1
A
A2
b
c
A1
e
0.076 mm
0.003 inch
SEATING PLANE
D
Gage Plane
0.25mm
28
15
k
E
Pin 1 identification
14
A1
SEATING PLANE
L
TSSO28M
19/21
TDA7427A
SO28 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
inch
MAX.
TYP.
2.65
MAX.
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
20/21
MIN.
8° (max.)
TDA7427A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
 1998 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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21/21