THC63LVD1027 Application Note Mode setting, System Diagram

THAN0084_Rev.3.00_E
Application Note THAN0084_Rev.3.00_E
THC63LVD1027 Application Note
Mode setting, System Diagram and PCB Design Guide
Date
Revision
Contents
2008/12/03
Rev.1.00_E
New created
2010/03/03
Rev.1.10_E
Caution for LVDS line connection is added
2010/03/11
Rev.1.20_E
Some descriptions are altered.
2010/06/07
Rev.1.30_E
Some descriptions are altered.
2011/09/13
Rev.1.40_E
Some descriptions are altered.
2013/11/07
Rev.3.00_E
Some descriptions are altered.
Copyright©2013 THine Electronics, Inc.
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Contents
1.Mode Setting ........................................................................................................ P.3
2.Signal Flow for Each Setting ............................................................................... P.3
3.Output Control / Fail Safe .................................................................................... P.4
4.Example of System Diagram................................................................................ P.5
5.Note ...................................................................................................................... P.9
6.PCB Design Guide Line ..................................................................................... P.11
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1. Mode Setting
Input/Output
MODE1
MODE0
(Input mode)
(Output mode)
H: Single
H: Single
L: Dual
L: Dual
CLK in
L
L
Hi-z
L
L
Hi-z
H
L
CLK in
L
H
--
H
H
RCLK2+/-
Dual-In/Dual-Out
(Fig.2-1, 3-1)
Distribution
(Fig.2-2, 3-2)
Single-In/Dual-Out
(Fig.2-3, 3-3)
Dual-In/Single-Out
(Fig.2-4, 3-4)
Reserved
2. Signal Flow for Each Setting
Dual-In / Dual-Out
CLK
Frequency
f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
Distribution mode
TA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA Rate
TCLK1+/f
CLK
Frequency
f
RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-
TA2+/CLK
TB2+/Frequency
TC2+/f
TD2+/TE2+/DATA Rate
TCLK2+/f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/RCLK1+/f
TA1+/CLK
TB1+/Frequency
TC1+/f
TD1+/TE1+/DATA Rate
TCLK1+/f
CLK
Frequency
f
Hi-z
Must be
Hi-z
Same Data
RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-
TA2+/CLK
TB2+/Frequency
TC2+/f
TD2+/TE2+/DATA Rate
TCLK2+/f
=TCLK1+/-
Fig2-2
Single-In / Dual-Out
Dual-In / Single-Out
CLK
Frequency
f
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/RCLK1+/f
TA1+/CLK
TB1+/Frequency
TC1+/f/2
TD1+/TE1+/DATA Rate
TCLK1+/f/2
RA2+/RB2+/RC2+/RD2+/RE2+/RCLK2+/-
TA2+/CLK
TB2+/Frequency
TC2+/f/2
TD2+/TE2+/DATA Rate
TCLK2+/f/2
Hi-z
Must be
Hi-z
=TCLK1+/-
Fig2-1
CLK
Frequency
f
TA1+/CLK
TB1+/Frequency
TC1+/2f
TD1+/TE1+/DATA Rate
TCLK1+/2f
CLK
Frequency
f
TA2+/TB2+/TC2+/TD2+/TE2+/TCLK2+/-
RA1+/RB1+/RC1+/RD1+/DATA Rate RE1+/f
RCLK1+/-
RA2+/RB2+/RC2+/RD2+/DATA Rate RE2+/f
RCLK2+/-
Fig2-3
Copyright©2013 THine Electronics, Inc.
Hi-z
Fig2-4
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THAN0084_Rev.3.00_E
3. Output Control / Fail Safe
THC63LVD1027 has a function to control output depending on LVDS input condition.
PD
RCLK1+/-
RCLK2+/-
Output
L
*
*
All Hi-z
H
Hi-z
*
All Hi-z
H
CLK in
CLK in
Refer to p.3 Mode Setting #
H
CLK in
Hi-z
Refer to p.3 Mode Setting #
* : Don’t care
# : If a particular input data pair is Hi-z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting state of Hi-z.
VDD
LVDS input buffer
Internal circuit of THC63LVD1027
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4. Example of System Diagram
4.1) Dual-In/Dual-Out (LVDS Input: 20~85MHz)
THC63LVD1027
RA1-
TA1-
RA1+
TA1+
RB1-
TB1-
RB1+
TB1+
RC1-
TC1-
RC1+
TC1+
100ohm
100ohm
100ohm
100ohm
100ohm
100ohm
RCLK1-
TCLK1-
RCLK1+
TCLK1+
100ohm
100ohm
RD1-
TD1-
RD1+
TD1+
TE1-
RE1+
TE1+
RA2-
TA2-
RA2+
TA2+
RB2-
TB2-
RB2+
TB2+
100ohm
100ohm
100ohm
100ohm
100ohm
100ohm
RC2-
TC2-
RC2+
TC2+
100ohm
100ohm
RCLK2-
TCLK2-
RCLK2+
TCLK2+
100ohm
100ohm
RD2-
TD2-
RD2+
TD2+
100ohm
100ohm
RE2-
TE2-
RE2+
TE2+
100ohm
100ohm
*1
*1
GND
PCB(Transmitter)
GND
GND
VDD
VDD
VDD
JP
RS
GND
PCB(Receiver)
*3
0.1uF x4
VCC(3.3V)
F.Bead
ASIC/FPGA
etc.
LVDS Transmitter
ASIC/FPGA
etc.
RE1-
LVDS Receiver
100ohm
100ohm
GND
VDD
*2
*2
220uF
10uF
VDD
CAP
PD
CAP
MODE1
CAP
0.1uF
0.1uF
0.1uF
MODE0
PCB(THC63LVD1027)
*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.
*3 Place 4 de-coupling capacitors close to each VDD pin one by one.
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Fig3-1
THine Electronics, Inc.
THAN0084_Rev.3.00_E
4.2) Distribution (LVDS Input: 20~85MHz)
RA1-
RA-
TA1100ohm
100ohm
RA1+
TA1+
RB1-
TB1-
RA+
RB100ohm
100ohm
RB1+
TB1+
RB+
RC1-
TC1-
RC-
RC1+
TC1+
100ohm
100ohm
RCLK1-
RC+
TCLK1100ohm
100ohm
RCLK1+
TCLK1+
THC63LVD104S
THC63LVD1027
VCC(2.5V)*3
0.001uF 0.1uF
VCC
GND
LVCC
LGND
PVCC
F.Bead
PGND
DK
R/F
*4
RCLKRCLK+
CLKOUT
/PDWN
RD1-
TD1-
RD-
TD1+
RE1-
TE1-
RE1+
TE1+
100ohm
100ohm
Hi-z
Hi-z
Hi-z
RA2-
RD+ RA6 - RA0
RB6 - RB0
RE- RC6 - RC0
RD6 - RD0
RE+ RE6 - RE0
RA-
TA2100ohm
RA2+
TA2+
RB2-
TB2-
RA+
RB100ohm
TB2+
RB+
RC2-
TC2-
RC-
RC2+
TC2+
RB2+
RCLK2-
TCLK2-
RCLK2+
TCLK2+
100ohm
RC+
THC63LVD104S
LVDS Transmitter
ASIC/FPGA
etc.
RD1+
Hi-z
OE
100ohm
100ohm
7
7
7
7
7
VCC(2.5V)*3
0.001uF 0.1uF
VCC
GND
LVCC
LGND
PVCC
F.Bead
PGND
DK
R/F
*4
RCLK100ohm
RCLK+
CLKOUT
/PDWN
Hi-z
RD2RD2+
Hi-z
RD-
TD2-
100ohm
TD2+
RE2-
TE2-
RE2+
TE2+
100ohm
*1
7
7
7
7
7
*1
GND
GND
GND
PCB(Transmitter)
GND
PCB(Receiver)
VDD
VDD
VDD
JP
*5
RS
VCC(3.3V)
F.Bead
OE
RD+ RA6 - RA0
RB6 - RB0
RE- RC6 - RC0
RD6 - RD0
RE+ RE6 - RE0
0.1uF x4
GND
VDD
*2
*2
220uF
10uF
VDD
CAP
PD
CAP
MODE1
CAP
0.1uF
0.1uF
0.1uF
MODE0
PCB(THC63LVD1027)
*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.
*3 Supply voltage of THC63LVD104S is 2.5V(Typ).
*4 Refer to datasheet.
*5 Place 4 de-coupling capacitors close to each VDD pin one by one.
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Fig3-2
THine Electronics, Inc.
THAN0084_Rev.3.00_E
4.3) Single-In/Dual-Out (LVDS Input: 40~135MHz)
THC63LVD1027
RA1-
TA1-
RA1+
TA1+
RB1-
TB1-
RB1+
TB1+
RC1-
TC1-
RC1+
TC1+
100ohm
100ohm
100ohm
100ohm
100ohm
100ohm
RCLK1-
TCLK1-
RCLK1+
TCLK1+
100ohm
100ohm
RD1-
TD1-
RD1+
TD1+
TE1-
RE1+
TE1+
RA2-
TA2-
RA2+
TA2+
RB2-
TB2-
RB2+
TB2+
100ohm
100ohm
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
100ohm
100ohm
RC2-
TC2-
RC2+
TC2+
RCLK2-
TCLK2-
RCLK2+
TCLK2+
100ohm
100ohm
RD2-
TD2-
RD2+
TD2+
RE2-
TE2-
RE2+
TE2+
100ohm
100ohm
*1
*1
GND
PCB(Transmitter)
GND
GND
VDD
VDD
VDD
JP
RS
GND
PCB(Receiver)
*3
0.1uF x4
VCC(3.3V)
F.Bead
ASIC/FPGA
etc.
LVDS Transmitter
ASIC/FPGA
etc.
RE1-
LVDS Receiver
100ohm
100ohm
GND
VDD
*2
*2
220uF
10uF
VDD
CAP
PD
CAP
MODE1
CAP
0.1uF
0.1uF
0.1uF
MODE0
PCB(THC63LVD1027)
*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.
*3 Place 4 de-coupling capacitors close to each VDD pin one by one.
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Fig3-3
THine Electronics, Inc.
THAN0084_Rev.3.00_E
4.4) Dual-In/Single-Out (LVDS Input: 20~42.5MHz)
THC63LVD1027
RA1-
TA1-
RA1+
TA1+
RB1-
TB1-
RB1+
TB1+
RC1-
TC1-
RC1+
TC1+
100ohm
100ohm
100ohm
100ohm
100ohm
100ohm
RCLK1-
TCLK1-
RCLK1+
TCLK1+
100ohm
100ohm
RD1-
TD1-
RD1+
TD1+
TE1-
RE1+
TE1+
RA2-
TA2-
RA2+
TA2+
RB2-
TB2-
RB2+
TB2+
100ohm
100ohm
Hi-z
100ohm
Hi-z
100ohm
RC2-
TC2-
RC2+
TC2+
Hi-z
100ohm
RCLK2-
TCLK2-
RCLK2+
TCLK2+
Hi-z
100ohm
RD2-
TD2-
RD2+
TD2+
Hi-z
100ohm
RE2-
TE2-
RE2+
TE2+
Hi-z
100ohm
*1
*1
GND
PCB(Transmitter)
GND
GND
VDD
VDD
VDD
JP
GND
PCB(Receiver)
*3
0.1uF x4
RS
VCC(3.3V)
F.Bead
ASIC/FPGA
etc.
LVDS Transmitter
ASIC/FPGA
etc.
RE1-
LVDS Receiver
100ohm
100ohm
GND
VDD
*2
*2
220uF
10uF
VDD
CAP
PD
CAP
MODE1
CAP
0.1uF
0.1uF
0.1uF
MODE0
PCB(THC63LVD1027)
*1 Connect each PCB GND with low impedance cable.
*2 Select the suitable value for the system.
*3 Place 4 de-coupling capacitors close to each VDD pin one by one.
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Fig3-4
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THAN0084_Rev.3.00_E
5. Note
5.1)LVDS input pin connection
When LVDS line is not drived from the previous device, the line is pulled up to 3.3V internally in THC63LVD1027.
This can cause violation of absolute maximum ratings to the previous LVDS Tx device whose operating condition is
lower voltage power supply than 3.3V. This phenomenon may happen at power on phase of the whole system including
THC63LVD1027. One solution for this problem is PD=L control during no LVDS input period because pull-up resistors are cut off at power down state.
If this situation is not avoidable and PD=L is hard to apply, there still is several remedy; therefore please contact to
[email protected]
(for FAE mailing list)
LVDS Tx side PCB
LVDS Rx side PCB
VDD
Low VDD
THC63LVD1027
LVDS Tx
or
LVDS Tx
integrated
device
LVDS input buffer
Internal circuit of THC63LVD1027
5.2)Power On Sequence
Don’t input RCLK#+/- before THC63LVD1027 is on in order to keep absolute maximum ratings.
If it is not avoidable, please contact to
[email protected]
(for FAE mailing list)
5.3)Cable Connection and Disconnection
Don’t connect and disconnect the LVDS cable, when the power is supplied to the system.
5.4)GND Connection
Connect the each GND of the PCB which Transmitter, Receiver and THC63LVD1027 on it.
It is better for EMI reduction to place GND cable as close to LVDS cable as possible.
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5.5)Multi Drop Connection
Multiple counterpart use such as following systems are not recommended.
THC63LVD1027
TCLK1,2-
LVDS Rx
TCLK1,2+
LVDS Rx
5.6)Asynchronous use
Asynchronous use such as following systems are not recommended.
If it is not avoidable, please check if datasheet p.11 tCK12 spec can be kept or not and more further, please contact to
[email protected]
CLKOUT
(for FAE mailing list)
LVDS Tx
RCLK1+/-
LVDS Tx
RCLK2+/-
DATAOUT
IC
THC63LVD1027
CLKOUT
DATAOUT
Asynchronous use such as following systems are not recommended.
If it is not avoidable, please contact to
[email protected]
(for FAE mailing list)
CLKIN
TCLK1+/-
LVDS Rx
DATAIN
IC
THC63LVD1027
TCLK2+/-
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LVDS Rx
DATAIN
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6. PCB Design Guide Line
General Guideline
•
•
•
•
•
Use 4 layer PCB (minimum).
Locate by-pass capacitors close to the device pins to a maximum extent.
Make the loop minimum which is consist of Power line and Gnd line
Use large Gnd plane
Separate VDD power supply for each block via ferrite bead
LVDS Traces
• Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be well
balanced.(Keep all these differential impedance and the length of media as same as possible.).
•
•
•
•
•
Minimize the distance between traces of a pair (S1) to maximize common mode rejection. See following figure.
Place adjacent LVDS trace pair at least twice (>2 x S1) as far away as possible.
Avoid 90 degree bends and sharp angles.
Minimize the number of VIA on LVDS traces.
Match impedance of PCB trace, connector, media (cable) and termination to minimize reflections (emissions) for
cabled applications (typically 100ohm differential mode characteristic impedance).
• Place terminal resister close to the Receiver pins to a maximum extent.
• To plase common mode choke coil is desired for EMI reduction.
S1
> 2 x S1
GND
+Signal
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-Signal
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+Signal
-Signal
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Attentions and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions
in this material. Please note if errors or omissions should be found in this material, we may not
be able to correct them immediately.
3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications
which require very high reliability (including medical equipment directly concerning people's
life, aerospace equipment, or nuclear control equipment). Also, when using this product for the
equipment concerned with the control and safety of the transportation means, the traffic signal
equipment, or various Types of safety equipment, please do it after applying appropriate
measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you
are encouraged to have sufficiently redundant or error preventive design applied to the use of the
product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category
of strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail:[email protected]
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