SM59R04A2 Replace STC12C5A16S2 Application Note SM59R04A2 替換 STC12C5A16S2 應用說明 一、 二、 三、 適用產品：SM59R04A2 應用範圍：針對 SM59R04A2 替換 STC12C5A16S2 之應用，僅需對特殊功能暫存器定義 做小幅度修改即可． 功能說明：SM59R04A2、STC12C5A16S2 各個 MCU 規格比較(表 1)： Feature 工作電壓 (V) System clock(MHz) 內部 RC 震盪器 內置復位 低壓復位 Program Flash ( byte) SM59R04A2 2.7~3.6 (4.5~5.5) 1T：up to 25 (1T，2T can change on fly) 有(最大 24MHz) 有(可調復位時間) 有 1-T：up to 37 有 有 有(需增加電路於 P4.6) MDU 有(4 路)，中斷向量 0x2BH 有(4 路，10 位)， 中斷向量 0x43H 有 ADC 有 SPI interface IIC interface KBI interface Port 4.4~4.7(40-pin PDIP) &four I/O type 有 有 有 16K 有 有 256+1024 10 有 有 有(2 個) 有(2 組) STC12C5A16AD 及 STC12C5A16PWM 只有 1 組 有(2 路)，中斷向量 0x3BH 有(2 路，8 位)， 中斷向量與 PCA 共用 無 有 STC12C5A16PWM 沒有 有 無 無 有 有 EEPROM ISP/IAP RAM( byte) Interrupt WDT 16-bit Dual DPTR Timer UART PCA PWM 16K STC12C5A16S2 2.2~3.6 (3.3~5.5) 有 有 256+1024 13 有 有 有(3 個) 有(2 組) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 1 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 四、 特殊功能暫存器比較表： SM59R04A2(表２)： Hex\Bin F8 X000 IICS X001 IICCTL X010 IICA1 X011 IICA2 X100 IICRWD X101 IICS2 X110 X111 Bin/Hex FF F0 E8 E0 D8 B P4 ACC P5 SPIC1 MD0 ISPFAH SPIC2 MD1 ISPFAL P3M0 SPITXD MD2 ISPFD P3M1 SPIRXD MD3 ISPFC P4M0 SPIS MD4 P4M1 MD5 LVC P5M0 TAKEY ARCON SWRES P5M1 F7 EF E7 DF D0 C8 C0 B8 PSW T2CON IRCON IEN1 CCCON CCEN IP1 P0M0 CRCL CCL1 S0RELH P0M1 CRCH CCH1 S1RELH P1M0 TL2 CCL2 PWMD0H P1M1 TH2 CCH2 PWMD0L P2M0 PWMMDH CCL3 PWMD1H P2M1 PWMMDL CCH3 PWMD1L D7 CF C7 BF B0 A8 A0 98 P3 IEN0 P2 S0CON PWMD2H IP0 PWMD2L S0RELL PWMD3H ADCC1 PWMD3L ADCC2 PWMC ADCDH WDTC ADCDL WDTK ADCCS S1CON S1BUF S1RELL B7 AF A7 9F S0BUF IEN2 90 88 80 P1 TCON P0 AUX TMOD SP KBLS TL1 DPH KBE TH0 DPL1 KBF TH1 DPH1 TL0 DPL KBD RCON IFCON PCON 97 8F 87 STC12C5A16S2(表３)： Hex\Bin F8 X000 F0 E8 E0 D8 B ACC CCON D0 C8 C0 B8 PSW P5 P4 IP B0 A8 A0 98 P3 IE P2 SCON 90 P1 X001 CH X010 CCAP0H X011 CCAP1H PCA_PWM0 PCA_PWM1 CL CCAP0L CCAP1L CMOD CCAPM0 CCAPM1 P5M1 WDT_CONTR P5M0 IAP_DATA SADEN X100 X101 X110 X111 F7 EF E7 DF SPSTAT SPCTL SPDAT IAP_ADDRH IAP_ADDRL IAP_CMD IAP_TRIG IAP_CONTR P4SW ADC_CONTR ADC_RES ADC_RESL IP2H P3M1 SADDR P3M0 P4M1 P4M0 IP2 BUS-SPEED SBUF AUXR1 S2CON S2BUF BRT P1ASF P1M1 P1M0 P0M1 P0M0 P2M1 88 TCON TMOD TL0 TL1 80 P0 SP DPL DPH Bin/Hex FF TH0 TH1 D7 CF C7 BF IPH IE2 B7 AF A7 9F P2M0 CLK_DIV 97 AUXR WAKE_CLK 0 8F PCON 87 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 2 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 五、 特殊功能差異說明： 特殊功能 外掛晶振頻率 SM59R04A2 Addr. 最大25MHz STC12C5A16S2 Addr. 最大35MHz (1T及2T模式可於程式運行中切換) IFCON.ITS 8FH.7 参考附件一 內部RC震盪器 內置復位 由1MHz至24MHz共8階可調 5V：11MHz~15.5MHz 参考附件一 3V：8MHz~12MHz 復位時間由4ms至200ms共7階可調 復位時間固定 参考附件二 低壓復位 1. L(3.3V)版復位電壓為2.5V 需增加電路於P4.6 2. C(5V)版復位電壓為3.6V 1. L(3.3V)版復位電壓為1.30V IEN1.IELVI(LVI interrupt enable， B8H.4 interrupt vector at 0x63H) LVC IE.ELVD(LVD interrupt enable， E6H 参考附件二 IAP, ISP, TAKEY EEPROM IFCON.ISPE 2. C(5V)版復位電壓為1.32V A8H.6 interrupt vector at 0x33H) WAKE_CLK0.LVD_WAKE BFH.3 IAP_DATA C2H 8FH.1 IAP_ADDRH C3H ISPFAH E1H IAP_ADDRL C4H ISPFAL E2H IAP_CMD C5H ISPFD E3H IAP_TRIG C6H ISPC E4H IAP_CONTR C7H F7H 参考附件三 輔助記憶體 Embedded 1024B RAM IFCON.EMEN 8FH.1 AUXR.EXTRAM =1, 禁能 =1, 禁能 =0, 致能 (default) =0, 致能(default) 8EH.1 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 3 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 中斷致能及優先 共提供13組中斷源 權設定不同 IEN0 A8H IE A8H IEN1 B8H IE2 AFH IEN2 9AH IP B8H IP A9H IPH B7H IP1 B9H IP2 B5H IP2H B6H C1H 共提供10組中斷源 参考附件四 看門狗1. 時脈源不同 2. 預分頻不同 3. 設定及清除 計時方式不 同 TAKEY F7H WDT_CONTR WDTC B6H 1. 時脈源由外部晶振產生，溢出時 WDTK B7H 間不固定。 2. 由WDT_CONTR[2:0]設定，預分 1. 時脈源由內部250KHz產生，溢出時 頻由2~256分8階。 間固定。 Period = 2. 由WDTC[3:0]設定，預分頻由 (12xPre-scalex32768)/Fosc 1~32768分16階： (XTAL1) Period = 1.02 m sec ~ 33.55 sec 3. 沒有KEY的設計，可直接改 3. 須先設定KEY(TAKEY)後，才可對 WDT_CONTR。 WDTC設定；清除WDT於WDTK寫 入0x55。 参考附件五 Dual DPTR 第二組 UART AUX.DPS 91H.0 AUXR1.DPS =0, select DPTR0 =0, select DPTR0 =1, select DPTR1 =1, select DPTR1 A2H.0 DPL 82H DPL 82H DPH 83H DPH 83H DPL1 84H DPH1 85H IEN2.ES1(UART1 interrupt enable， interrupt vector at 0x83H) 9AH.1 IE2.ES2(UART2 interrupt enable， AFH.0 interrupt vector at 0x43H) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 4 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note AUX.P4UR1 PCA 91H.4 AUXR1.S2_P4 =0, UART1 at P1. =0, UART2 at P1. =1, =1, TxD1 change from P1.3 to P4.3 TxD2 from P1.3 to P4.3 RxD1 change from P1.2 to P4.2 RxD2 from P1.2 to P4.2 A2H.4 S1CON 9BH S2CON 9AH S1RELL 9DH S2BUF 9BH S1RELH BBH BRT 9CH S1BUF 9CH AUXR 8EH IEN0.ET2(Timer 2 interrupt enable， A8H.5 D9H.0 enable，interrupt vector at 0x3BH) interrupt vector at 0x2BH) AUX.P4CC CMOD.ECF (PCA interrupt 91H.6 AUXR1.PCA_P4 A2H.6 =0, PCA at P1. =0, PCA at P1. =1, =1, CC0 change from P1.0 to P4.0 ECI change from P1.2 to P4.1 CC1 change from P1.1 to P4.1 PCA0/PWM0 from P1.3 to P4.2 CC2 change from P1.3 to P4.2 PCA1/PWM1 from P1.4 to P4.3 CC3 change from P1.4 to P4.3 CCON D8H T2CON C8H CMOD D9H CCCON C9H CCAPM0 DAH CCEN C1H CCAPM1 DBH TL2 CCH CH E9H TH2 CDH CL F9H CRCL CAH CCAP0L EAH CRCH CBH CCAP0H FAH CCL1 C2H CCAP1L EBH CCH1 C3H CCAP1H FBH CCL2 C4H PCA_PWM0 F2H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 5 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note CCH2 C5H CCL3 C6H CCH3 C7H PCA_PWM1 F3H 参考附件六 PWM IEN1.IEPWM(PWM interrupt enable， A9H.0 D9H.0 enable，interrupt vector at 0x3BH) interrupt vector at 0x43H) PWMC CMOD.ECF (PCA interrupt 91H.6 AUXR1.PCA_P4 A2H.6 PWMD0H =0, PCA at P1. PWMD0L =1, PWMD1H PCA0/PWM0 from P1.3 to P4.2 PWMD1L PCA1/PWM1 from P1.4 to P4.3 PWMD2H CCON D8H PWMD2L CMOD D9H PWMD3H B5H CCAPM0 DAH PWMD3L BCH CCAPM1 DBH PWMMDH BDH CH E9H PWMMDL BEH CL F9H 参考附件七 BFH CCAP0L EAH B1H CCAP0H FAH B2H CCAP1L EBH B3H CCAP1H FBH B4H PCA_PWM0 F2H CEH PCA_PWM1 F3H CFH MDU PCON.MDUF 87H.6 ARCON EFH MD0 E9H MD1 EAH 無 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 6 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note MD2 EBH MD3 ECH MD4 EDH MD5 EEH 参考附件八 ADC IEN1.IEADC(ADC interrupt enable， B8H.2 interrupt vector at 0x53H) IE.EADC(ADC interrupt enable， A8H.5 interrupt vector at 0x2BH) ADCC1 ABH P1ASF BCH ADCC2 ACH ADC_CONTR BDH ADCDH ADH ADC_RES BEH ADCDL AEH ADC_RESL BFH ADCCS AFH AUXR1 A2H 参考附件九 SPI Interface IEN1.IESPI(SPI interrupt enable， B8H.1 interrupt vector at 0x4BH) AUX.P4SPI IE2.ESPI(SPI interrupt enable， AFH.1 interrupt vector at 0x4BH) 91H.5 AUXR1.SPI_P4 =0, SPI at P1. =0, SPI at P1. =1, =1, SS change from P1.4 to P4.0 SS change from P1.4 to P4.0 MOSI change from P1.5 to P4.1 MOSI change from P1.5 to P4.1 MISO change from P1.6 to P4.2 MISO change from P1.6 to P4.2 SPI_CLK change from P1.7 to P4.3 SPICLK change from P1.7 to P4.3 A2H.5 SPIC1 F1H SPSTAT CDH SPIC2 F2H SPCTL CEH SPIS F3H SPDATA CFH SPITxD F4H SPIRxD F5H 参考附件十 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 7 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note IIC Interface IEN1.IEIIC(IIC interrupt enable， B8H.5 無 interrupt vector at 0x6BH) AUX.P4IIC 91H.3 =0, IIC at P1. =1, IIC_SCL change from P1.6 to P4.0 IIC_SDA change from P1.7 to P4.1 IICCTL F9H IICS F8H IICA1 FAH IICA2 FBH IICRWD FCH IICS2 FDH 参考附件十一 KBI Interface IE1.KBD(EEI interrupt enable， A9H.0 無 interrupt vector at 0x5BH) AUX.P0KBI 91H.2 =0, KBI on P2. =1, KBI on P0. KBLS 93H KBE 94H KBF 95H KBD 96H 参考附件十二 Port 4.4~4.7 (40-pin PDIP) & Four I/O type The OCI_SCL、ALE、OCI_SDA and P4SW[6:4] RESET can be define as P4.4、P4.5、 =1,the NA、ALE、EX_LVD define as P4.6 and P4.7 by writer or ISP。 P4.4、P4.5、P4.6 P0 P0M1 80H BBH[6:4] The RST can be define as P4.7 by ISP Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 8 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note ALE P0M0 D3H P0 P1 D2H P0M1 80H P1M1 90H P0M0 93H P1M0 D5H P2 D4H P1 90H P2M1 A0H P1M1 91H P2M0 D7H P1M0 92H P3 D6H P2 A0H P3M1 B0H P2M1 95H P3M0 DBH P2M0 96H P4 DAH P3 B0H P4M1 E8H P3M1 B1H P4M0 DDH P3M0 B2H P5 DCH P4 C0H P5M1 D8H P4M1 B3H P5M0 DFH P4M0 B4H 参考附件十三 DEH P5 C8H P5M1 C9H P5M0 CAH IFCON[3:2] 8FH[3:2] 94H P4SW.ALE_P4.5 =00, ALE always output =1, ALE output only during a MOVX =01, No ALE output =0, as P4.5 I/O BBH.5 =10, ALE output only during a MOVX The ALE can be define as P4.5 I/O by ISP or ICP Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 9 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件一：外掛晶振頻率與內部 RC 震盪器使用說明 SM59R04A2 之時鐘來源可使用外掛晶振或內部 RC 震盪器（因製程及溫度因素，會有一定程度之漂 移，只適用於對時鐘精確度不太要求之應用環境）。 選擇外掛晶振或內部 RC 震盪器需使用 ICP 或 ISP 燒錄模式中選定。 時鐘來源如以下表格，出廠時為選擇 24Mhz 內部 RC 震盪器。 Clock source External crystal 24MHz from internal OSC 20MHz from internal OSC 16MHz from internal OSC 12MHz from internal OSC 8MHz from internal OSC 4MHz from internal OSC 2MHz from internal OSC 1MHz from internal OSC Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 10 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件二：復位使用說明 SM59R04A2 除了標準 Reset Pin 復位功能，另外提供軟體復位功能、內建復位電路(可選擇復位時間)、 低電壓復位功能供客戶使用。 1. 軟體復位功能使用 SWRES(0xE7H)及 TAKEY(0xF7H)兩個特殊功能暫存器設定。 SWRES 特殊功能暫存器於寫入 0xFFH 時產生復位功能，但 SWRES 於寫入之前需先於 TAKEY 特殊 功能暫存器連續寫入 0x55H,0x AAH 及 0x5AH，才能開啟 SWRES 之寫入功能；未於 TAKEY 連續寫入 0x55H,0x AAH 及 0x5AH 時，SWRES 只能讀取不能寫入。 2. 內建復位電路，復位時間於 ICP 或 ISP 燒錄模式中選擇。 Internal Reset time 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 3. SM59R04A2 亦提供低電壓復位功能，且提供中斷向量 0x63H 供客戶使用，低電壓復位功能使用 之特殊功能暫存器為 LVC(0xE6H)。 Mnemonic: LVC 7 LVI_EN 6 - 5 LVRXE Address: E6h 4 - 3 - 2 - 1 - 0 - Reset 00H LVI_EN: Low voltage interrupt function enable bit. LVI_EN = 0 : disable low voltage detect function. LVI_EN = 1 : enable low voltage detect function. LVRXE: External low voltage reset function enable bit. LVRXE = 0 : disable external low voltage reset function. LVRXE = 1 : enable external low voltage reset function. Low Voltage Detect Level LVI SM59R04A2C 4.0V SM59R04A2L 2.7V LVRX 3.6V 2.5V Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 11 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件三：IAP, ISP, EEPROM 使用說明 1. 新茂與 STC IAP, ISP, EEPROM 功能比較： ISP服務原始程式 ISP電腦端開發環境 IAP及EEPROM是否需等待時間 頁(扇區)字節長度 新茂 有提供 有提供 不需要 256 字節 STC 無 無 需依系統工作時鐘設置等待時間 512 字節 2. 新茂與 STC IAP, ISP, EEPROM 特殊功能暫存器比較： 特殊功能暫存器名稱 高位址 低位址 資料 命令 功能致能 功能致能暫存器保護 功能啟動 新茂名稱及位址 ISPFAH (0xE1H) ISPFAL (0xE2H) ISPFD (0xE3H) ISPFC (0xE4H) IFCON.ISPE (0x8FH.0) TAKEY (0xF7H) 於此暫存器連續填入0x55H， 0xAAH及0x5AH以啟動功能 無(不需要) STC名稱及位址 IAP_ADDRH (0xC3H) IAP_ADDRL (0xC4H) IAP_DATA (0xC2H) IAP_CMD (0xC5H) IAP_CONTR (0xC7H) 於此暫存器設定等待時間 無 IAP_TRIG (0xC6H) 於此暫存器連續填入0x5AH， 0xA5H以啟動命令 3. 新茂與 STC IAP, ISP, EEPROM 功能說明： 字節寫 片保護 頁(扇區)擦除 片擦除 字節讀 新茂 ISPFC=0x00H or 0x04H(Note1) ISPFC=0x01H ISPFC=0x02H or 0x06H(Note1) ISPFC=0x03H(Note1) 僅提供於特殊功能 ISPFC =0x05H(Note1) STC IAP_CMD=0x02H 無 IAP_CMD=0x03H 無 IAP_CMD=0x01H Note1： 新茂亦提供以下五個功能選擇位元：看門狗功能致能(ISPFAL=0x03H) 、時鐘來源選擇(ISPFAL=0x04H)、 P4[4:7] I/O 功能選擇(ISPFAL=0x05H)、內建復位電路重置時間選擇(ISPFAL=0x06H)及 ISP 服務程式區進 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 12 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 入方式之設定(ISPFAL=0x08H)。 上述之功能選擇位元之片擦除（ISPFC=0x03H） 、字節寫（ISPFC=0x04H）及頁(扇區)擦除（ISPFC=0x06H） 等命令尚需確認 EMF1~EMF4 等四個旗標之一有置高才會執行，字節讀（ISPFC=0x05H）則無此限制。 a. 看門狗功能致能(ISPFAL=0x03H)說明： 於程式中執行看門狗功能前需先將此功能選擇位元第 7 位元置低(0x03H，Bit 7=0)，此位元可使用 ISP 或 ICP 方式設定；於程式執行中亦可使用 IAP 之字節讀命令讀取此位元之狀態。 Bit 7 WDTEN Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - WDTEN 0 is enable WDT 1 is disable WDT b. 時鐘來源選擇(ISPFAL=0x04H) 說明： 可使用 ISP 或 ICP 等方式設定時鐘來源選擇；於程式執行中亦可使用 IAP 之字節讀命令讀取時鐘來源之設 定值。 System clock Select： Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 FCLK3 System clock select FCLK[3:0] XXXX-0XXX XXXX-1000 XXXX-1001 XXXX-1010 XXXX-1011 XXXX-1100 XXXX-1101 XXXX-1110 XXXX-1111 Bit 2 FCLK2 Bit 1 FCLK1 Bit 0 FCLK0 System clock External crystal 24MHz from internal OSC 20MHz from internal OSC 16MHz from internal OSC 12MHz from internal OSC 8MHz from internal OSC 4MHz from internal OSC 2MHz from internal OSC 1MHz from internal OSC c. P4[4:7] I/O 功能選擇(ISPFAL=0x05H) 說明： Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 13 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 可使用 ICP 或 ISP 方式設定，將 OCI_SCL、ALE、OCI_SDA and RESET 等 I/O 定義成 P4.4、P4.5、P4.6 and P4.7；於程式執行中亦可使用 IAP 之字節讀命令讀取 I/O 之設定值。 Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 RESET Bit 2 OCI_SDA Bit 1 ALE Bit 0 OCI_SCL RESET: 0 is bi-direction I/O pin (P4.7). 1 is reset input pin with 1000ns deglitch. OCI_SDA: 0 is bi-direction I/O pin (P4.6). 1 is OCI_SDA pin. ALE: 0 is bi-direction I/O pin (P4.5). 1 is ALE pin. OCI_SCL: 0 is bi-direction I/O pin (P4.4). 1 is OCI_SCL pin. 各種封裝對應之 PIN 腳如下表： OCI_SCL/P4.4 40-PIN PDIP 29 44-PIN PLCC 32 44-PIN PQFP 26 48-PIN LQFP 29 ALE/P4.5 30 33 27 30 OCI_SDA/P4.6 31 35 29 32 RESET/P4.7 9 10 4 5 d. 內建復位電路重置時間選擇(ISPFAL=0x06H) 說明： 可使用 ICP 或 ISP 方式選擇復位電路重置時間；於程式執行中亦可使用 IAP 之字節讀命令讀取復位電路重 置時間之設定值。 Internal reset timer select： Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Internal reset time select[7:0] XXXX-X111 0000-0110 0000-0101 0000-0100 0000-0011 0000-0010 0000-0001 0000-0000 Bit 2 Bit 1 Bit 0 Reset time 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 2ms e. ISP 服務程式區進入方式之設定(ISPFAL=0x08H) 說明： Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 14 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 可使用 ICP 或 ISP 方式選擇 ISP 服務程式區進入方式，於程式執行中亦可使用 IAP 之字節讀命令讀取 ISP 服務程式區進入方式之設定值，ISP 服務程式區進入方式有四種，分別由旗標 EMF1~4 所記錄。 ISP entry mechanism select： Bit 7 Bit 6 Bit 5 Bit 4 Trigger source ISP entry mechanism (1) First Address Blank. I.e. $0000 = FFh (2) P2.6 = 0 & P2.7 = 0 (3) P4.3 = 0 (4) P3.0 input 2 clocks Bit 3 Bit 2 Bit 1 Bit 0 晶片復位源 Internal Reset 晶片復位源 PAD reset EMF (Entry mechanism flag) Bit 7 Bit 5 Bit 3 Bit 1 Bit 6 Bit 4 Bit 2 Bit 0 EMF1 EMF2 EMF3 EMF4 ISPFC 特殊功能暫存器說明： Mnemonic: TAKEY 7 6 Mnemonic: IFCON 7 6 ITS CDPR Address: F7H 5 5 F12K 4 3 TAKEY [7:0] 4 F8K 3 ALEC[1] 2 2 ALEC[0] 1 1 EMEN 0 Reset 00H Address: 8FH 0 Reset ISPE 00H ISP 致能位元(ISPE)預設為唯讀屬性，為避免程序錯誤導致ISP誤動作，使用者必須依序寫入三筆資料到(55h, AAh, 5Ah)TAKEY，才可將ISP 致能位元(ISPE)改變為可寫入屬性： ISPE: = 1, ISP致能，ISP暫存器(ISPFAH, ISPFAL, ISPFD , ISPFC)設為可寫入。 = 0, ISP禁能，ISP暫存器(ISPFAH, ISPFAL, ISPFD and ISPFC)為唯讀 (預設)。 程序範例，ISP byte program #22H 到 program flash 位置$1005H，如下： MOV TAKEY, #055h MOV TAKEY, #0AAh MOV TAKEY, #05Ah ; enable ISPE write attribute ORL IFCON, #001H ; enable SM59R04A2 ISP function MOV ISPFAH, #010H ; set flash address-high, 10H MOV ISPFAL, #005H ; set flash address-low, 05H MOV ISPFD, #022H ; set flash data to be programmed, data = 22H MOV ISPFC, #000H ; start to program #22H to the flash address $1005H Address: E1H Mnemonic: ISPFAH 7 6 5 4 3 2 1 0 Reset Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 15 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note ISPFAH7 ISPFAH6 ISPFAH5 ISPFAH4 ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0 ISPFAH [7:0]: ISP共提供16位元定址，此為高位元8~15位置。 FFH Mnemonic: ISPFAL 7 6 5 4 3 2 ISPFAL7 ISPFAL6 ISPFAL5 ISPFAL4 ISPFAL3 ISPFAL2 ISPFAL [7:0]: ISP共提供16位元定址，此為低位元0~7的位置。 1 ISPFAL1 Address: E2H 0 Reset ISPFAL0 FFH Mnemonic: ISPFD 7 6 5 ISPFD7 ISPFD6 ISPFD5 ISPFD [7:0]: ISP資料暫存器。 1 ISPFD1 Address: E3H 0 Reset ISPFD0 FFH Mnemonic: ISPFC 7 6 5 EMF1 EMF2 EMF3 4 ISPFD4 4 EMF4 3 ISPFD3 3 - 2 ISPFD2 2 ISPF[2] 1 ISPF[1] Address: E4H 0 Reset ISPF[0] 00H EMF1: Entry mechanism (1) flag, clear by reset. (Read only) ISP服務程式區進入方式記錄旗標(1)，唯讀，可由晶片復位清除 EMF2: Entry mechanism (2) flag, clear by reset. (Read only) ISP服務程式區進入方式記錄旗標(2)，唯讀，可由晶片復位清除 EMF3: Entry mechanism (3) flag, clear by reset. (Read only) ISP服務程式區進入方式記錄旗標(3)，唯讀，可由晶片復位清除 EMF4: Entry mechanism (4) flag, clear by reset. (Read only) ISP服務程式區進入方式記錄旗標(4)，唯讀，可由晶片復位清除 ISPF [2:0]: ISP function select bit. ISP功能選擇元位，提供七組功能 ISPF[2:0] ISP function 字節寫 000 片保護 001 頁(扇區)擦除 010 片擦除 011 特殊功能字節寫 100 特殊功能字節讀 101 特殊功能頁(扇區)擦除 110 保留 111 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 16 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件四：中斷致能及優先權設定不同說明 1. 新茂與 STC 中斷功能比較： 新茂提供 13 組中斷源，STC 12C5A16S2 只有 10 組，STC 之 PCA 中斷需使用 CMOD(0xD9H)、 CCAPM0(0xDA) 及 CCAPM1(0xDB)致能。 新茂之中斷向量 STC 之中斷向量 IE0 – External interrupt 0 TF0 – Timer 0 interrupt 中斷源旗標 0x03H 0x0BH 0x03H 0x0BH IE1 – External interrupt 1 0x13H 0x13H TF1 – Timer 1 interrupt RI0/TI0 – Serial channel 0 interrupt TF2/EXF2 – Timer 2 interrupt 0x1BH 0x23H 0x2BH 0x1BH 0x23H 無 PWMIF – PWM interrupt 0x43H 無 SPIIF – SPI interrupt 0x4BH 0x4BH 0x53H 0x5BH 0x63H 0x6BH 0x83H Same as TF2 0x23H 無 0x2BH 無 ADCIF – A/D converter interrupt KBIIF – keyboard Interface interrupt LVIIF – Low Voltage Interrupt IICIF – IIC interrupt RI1/TI1 – Serial channel 1 interrupt PCA 0x43H 0x3BH 新茂與 STC 12C5A16S2 同樣有四階中斷之優先級，STC 之 SPI 及第二組串口中斷優先級需於 IP2 (0xB5H) 及 IP2H (0xB6H)設定。 2. 新茂與 STC 中斷之特殊功能暫存器比較： 特殊功能暫存器名稱 中斷致能 0 中斷致能 1 中斷致能 2 PCA 中斷致能 中斷優先設定低位址 中斷優先設定高位址 中斷優先設定第二組低位址 中斷優先設定第二組高位址 新茂名稱及位址 IEN0 (0xA8H) IEN1 (0xB8H) IEN2 (0x9AH) 與 Timer 2 中斷共用 IP0 (0xA9H) IP1 (0xB9H) 無 無 STC 名稱及位址 IE (0xA8H) 無 IE2 (0xAFH) CMOD.ECF(0xD9H.0) CCAPM0.ECCF0(0xDA.0) CCAPM1.ECCF1(0xDB.0) IP (0xB8H) IPH(0xB7H) IP2 (0xB5H) IP2H (0xB6H) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 17 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 3. 新茂與 STC 中斷之特殊功能暫存器說明： a. 中斷致能： 新茂中斷致能使用之暫存器說明： Mnemonic: IEN0 7 6 EA - 5 ET2 4 ES0 3 ET1 2 EX1 1 ET0 Address: A8h 0 Reset EX0 00h EA: EA=0 – Disable all interrupt. EA=1 – Enable all interrupt. ET2: ET2=0 – Disable Timer 2 overflow or external reload interrupt. ET2=1 – Enable Timer 2 overflow or external reload interrupt. ES0: ES0=0 – Disable Serial channel 0 interrupt. ES0=1 – Enable Serial channel 0 interrupt. ET1: ET1=0 – Disable Timer 1 overflow interrupt. ET1=1 – Enable Timer 1 overflow interrupt. EX1: EX1=0 – Disable external interrupt 1. EX1=1 – Enable external interrupt 1. ET0: ET0=0 – Disable Timer 0 overflow interrupt. ET0=1 – Enable Timer 0 overflow interrupt. EX0: EX0=0 – Disable external interrupt 0. EX0=1 – Enable external interrupt 0. Mnemonic: IEN1 7 6 EXEN2 5 IEIIC 4 IELVI 3 IEKBI 2 IEADC 1 IESPI Address: B8h 0 Reset IEPWM 00h EXEN2: Timer 2 reload interrupt enable. EXEN2 = 0 – Disable Timer 2 external reload interrupt. EXEN2 = 1 – Enable Timer 2 external reload interrupt. IEIIC: IIC interrupt enable. IEIICS = 0 – Disable IIC interrupt. IEIICS = 1 – Enable IIC interrupt. IELVI: LVI interrupt enable. IELVI = 0 – Disable LVI interrupt. IELVI = 1 – Enable LVI interrupt. IEKBI: KBI interrupt enable. IEKBI = 0 – Disable KBI interrupt. IEKBI = 1 – Enable KBI interrupt. IEADC: A/D converter interrupt enable IEADC = 0 – Disable ADC interrupt. IEADC = 1 – Enable ADC interrupt. IESPI: SPI interrupt enable. IESPI = 0 – Disable SPI interrupt. IESPI = 1 – Enable SPI interrupt. IEPWM: PWM interrupt enable. IEPWM = 0 – Disable PWM interrupt. IEPWM = 1 – Enable PWM interrupt. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 18 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: IE2 7 6 - 5 - 4 - 3 - 2 - 1 - Address: 9Ah 0 Reset ES1 00h ES1: ES1=0 – Disable Serial channel 1 interrupt. ES1=1 – Enable Serial channel 1 interrupt. STC12C5A16S2 中斷致能使用之暫存器說明： Mnemonic: IE 7 6 EA ELVD- 5 EADC 4 ES0 3 ET1 2 EX1 1 ET0 Address: A8h 0 Reset EX0 00h Mnemonic: IE2 7 6 - 5 - 4 - 3 - 2 - 1 ESPI Address: AFh 0 Reset ES2 00h Mnemonic: CMOD 7 6 CIDL - 5 - 4 - 3 CPS2 2 CPS1 1 CPS0 Address: D9h 0 Reset ECF 00h Mnemonic: CCAPM0 7 6 5 ECOM0 4 CAPP0 3 MAT0 2 TOG0 1 PWM0 Address: DAh 0 Reset ECCF0 00h Mnemonic: CCAPM1 7 6 5 ECOM1 4 CAPP1 3 MAT1 2 TOG1 1 PWM1 Address: DBh 0 Reset ECCF1 00h b. 中斷優先設定： 新茂中斷優先級設定使用之暫存器說明： Mnemonic: IP0 7 6 - 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 Address: A9h 0 Reset IP0.0 00h Mnemonic: IP1 7 6 - 5 IP1.5 4 IP1.4 3 IP1.3 2 IP1.2 1 IP1.1 Address: B9h 0 Reset IP1.0 00h Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 19 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Bit IP1.0, IP0.0 IP1.1, IP0.1 IP1.2, IP0.2 IP1.3, IP0.3 IP1.4, IP0.4 IP1.5, IP0.5 IP1.x IP0.x Priority Level 0 0 1 1 0 1 0 1 Level0 (lowest) Level1 Level2 Level3 (highest) Group Serial channel 1 interrupt - External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Timer 2 interrupt PWM interrupt SPI interrupt ADC interrupt KBI interrupt LVI interrupt IIC interrupt STC12C5A16S2 中斷優先級設定使用之暫存器說明： Mnemonic: IP 7 6 PPCA PLVD Mnemonic: IPH 7 6 PPCAH PLVDH 5 PADC 4 PS 5 PADCH 3 PT1 4 PSH 2 PX1 3 PT1H Address: B8h 0 Reset PX0 00h 1 PT0 2 PX1H 1 PT0H Address: B7h 0 Reset PX0H 00h Mnemonic: IP2 7 6 - 5 - 4 - 3 - 2 - 1 PSPI Address: B5h 0 Reset PS2 00h Mnemonic: IP2H 7 6 - 5 - 4 - 3 - 2 - 1 PSPIH Address: B6h 0 Reset PS2H 00h Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 20 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件五：看門狗設定不同說明 1. 新茂與 STC 看門狗功能比較： 新茂 內部獨立之 250KHz RC 震盪 器，復位時間固定 分 16 階，方便使用 1.02 m sec ~ 33.55 sec 時鐘源 復位階數 復位時間 STC 與外部晶振共用，復位時間不固定 分8階 需依公式計算復位時間 2. 新茂與 STC 看門狗特殊功能暫存器比較： 特殊功能暫存器名稱 看門狗功能設定 看門狗功能重置 功能致能暫存器保護 新茂名稱及位址 WDTC (0xB6H) WDTK (0xB7H) TAKEY (0xF7H) 於此暫存器連續填入 0x55H， 0xAAH 及 0x5AH 以啟動功能 STC 名稱及位址 WDT_CONTR (0xC1H) WDT_CONTR.CLR_WDT(0xC1H.4) 無 3. 新茂與 STC 看門狗之特殊功能暫存器說明： a. 新茂看門狗功能使用之暫存器說明： Mnemonic: WDTC 7 6 5 WDTF WDTE 4 - 3 2 1 WDTM [3:0] Address: B6h 0 Reset 04H WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by software or external reset or power on reset. WDTE: Control bit used to enable Watchdog timer. The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT can be disabled / enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is always disabled no matter what the WDTE bit status is. The WDTE bit can be read and written. WDTM [3:0]: WDT clock source divider bit. Please see table 7.8.1 to reference the WDT time-out period. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 21 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: WDTK 7 6 5 4 3 WDTK[7:0] 2 1 Address: B7h 0 Reset 00h WDTK: Watchdog timer refresh key. A programmer must write 0x55 into WDTK register, and then the watchdog timer will be cleared to zero. Mnemonic: TAKEY 7 6 5 4 3 TAKEY [7:0] 2 1 Address: F7h 0 Reset 00H 範例程式：於使用看門狗功能時需先使用 ISP 或 ICP 方式啟動看門狗功能，再於程式中再次啟動看門狗， 看門狗功能才能正常使用 MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah ; 啟動 WDTC 寫入功能. MOV WDTC, #28h ; 設定看門狗復位時間為 262.14 毫秒，並啟動看門狗功能 . . . MOV WDTK, #55h WDTM [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ; 清除看門狗計數器. Divider (250 KHz RC oscillator in) 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 Time period @ 250KHz 1.02ms 2.05ms 4.10ms 8.19ms 16.38ms (default) 32.77ms 65.54ms 131.07ms 262.14ms 524.29ms 1.05s 2.10s 4.19s 8.39s 16.78s 33.55s Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 22 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note b. STC 看門狗功能使用之暫存器說明： Mnemonic: WDT_CONTR 7 6 5 WDT_FLAG EN_WDT 4 CLR_WDT 3 IDLE_WDT 2 PS2 1 PS1 Address: C1h 0 Reset PS0 04H PS [2:0] 000 001 010 011 100 101 110 111 Divider 2 4 8 16 32 64 128 256 Time period @ 20MHz 39.3ms 78.6ms 157.3ms 314.6ms 629.1ms 1.25s 2.5s 5s PS [2:0] 000 001 010 011 100 101 110 111 Divider 2 4 8 16 32 64 128 256 Time period @ 12MHz 65.5ms 131.0ms 262.1ms 524.2ms 1.0485s 2.0971s 4.1943s 8.3886s Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 23 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件六：PCA 設定不同說明 新茂使用定時器 2 之捕獲模式以模擬業界常使用之 PCA 功能，並提供四個通道供使用。 新茂另提供四個通道之 PWM 功能於 P4.0~P4.3，且有獨立之中斷向量。（將說明於附件七） 1. 新茂與 STC PCA 功能比較： 中斷向量 通道數 模式 新茂 0x2BH 1. 4 個 16 位捕獲/比較模塊。 CC0(P1.0 or P4.0) CC1(P1.1 or P4.1) CC2(P1.3 or P4.2) CC3(P1.4 or P4.3) 1. 3 個上升沿捕獲( CC1~CC3 )及 1 個可上升沿或下降沿捕獲 (CC0)。 2. 16 位定時/計數器。 3. 可調制脈衝輸出(PWM)，將說明 於附件七。 STC 0x3BH 1. 2 個 16 位捕獲/比較模塊。 CCP0(P1.3 or P4.2) CCP1(P1.4 or P4.3) 1. 2. 3. 4. 上升/下降沿捕獲。 16 位軟件定時器。 高速輸出。 可調制脈衝輸出(PWM)。 2. 新茂與 STC PCA 特殊功能暫存器比較： 特殊功能暫存器名稱 通道切換 功能設定 比較/捕獲功能設定 比較/捕獲功能致能 計時器 2 低位元 計時器 2 高位元 重載及比較/補獲模塊 0 低 位元 重載及比較/補獲模塊 0 高 位元 比較/補獲模塊 1 低位元 比較/補獲模塊 1 高位元 比較/補獲模塊 2 低位元 比較/補獲模塊 2 高位元 比較/補獲模塊 3 低位元 比較/補獲模塊 3 高位元 新茂名稱及位址 AUX.P4CC(0x91H.6) T2CON (0xC8H) CCCON (0xC9H) TL2 (0xCCH) TH2 (0xCDH) STC 名稱及位址 AUXR1.PCA_P4(0xA2H.6) CCON (0xD8H) CMOD (0xD9H) CCAPM0 (0xDAH) CCAPM1 (0xDBH) CL (0xE9H) CH (0xF9H) CRCL (0xCAH) CCAP0L (0xEAH) CRCH (0xCBH) CCAP0H (0xFAH) CCL1 (0xC2H) CCH1 (0xC3H) CCL2 (0xC4H) CCH2 (0xC5H) CCL3 (0xC6H) CCH3 (0xC7H) CCAP1L (0xEBH) CCAP1H (0xFBH) 無 無 無 無 CCEN (0xC1H) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 24 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 3. 新茂與 STC PCA 之特殊功能暫存器說明： a. 新茂功能使用之暫存器說明： Mnemonic: T2CON 7 6 T2PS CC0FR 5 - 4 3 T2R[1:0] 2 T2CM 1 Address: C8h 0 Reset T2I[1:0] 00h T2PS: Prescaler select bit: T2PS = 0 – timer 2 is clocked with 1/12 of the oscillator frequency. T2PS = 1 – timer 2 is clocked with 1/24 of the oscillator frequency. CC0FR: Select active edge: CC0FR = 0 – falling edge CC0FR = 1 – rising edge T2R[1:0]: Timer 2 reload mode selection T2R[1:0] = 0X – Reload disabled T2R[1:0] = 10 – Mode 0 T2R[1:0] = 11 – Mode 1 T2CM: Timer 2 Compare mode selection T2CM = 0 – Mode 0 T2CM = 1 – Mode 1 T2I[1:0]: Timer 2 input selection T2I[1:0] = 00 – Timer 2 stop T2I[1:0] = 01 – Input frequency f/12 or f/24 T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2 T2I[1:0] = 11 – internal clock input is gated to the Timer 2 Mnemonic: CCCON 7 6 5 CCI3 CCI2 CCI1 4 CCI0 3 CCF3 2 CCF2 1 CCF1 Address: C9h 0 Reset CCF0 00H CCI3: Compare/Capture 3 interrupt control bit. “1” is enable. CCI2: Compare/Capture 2 interrupt control bit. “1” is enable. CCI1: Compare/Capture 1 interrupt control bit. “1” is enable. CCI0: Compare/Capture 0 interrupt control bit. “1” is enable. CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software. CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software. CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software. CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software. Compare/Capture interrupt share T2 interrupt vector. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 25 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: CCEN 7 6 COCAH3 COCAL3 5 COCAH2 4 COCAL2 3 COCAH1 2 COCAL1 1 COCAH0 Address: C1h 0 Reset COCAL0 00H COCAH3,COCAL3: Compare/capture mode for Channel 3. COCAH3 COCAL3 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC3 1 0 Compare enable 1 1 Capture on write operation into register CCL3 COCAH2,COCAL2: Compare/Capture mode for Channel 2. COCAH2 COCAL2 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC2 1 0 Compare enable 1 1 Capture on write operation into register CCL2 COCAH1,COCAL1: Compare/Capture mode for Channel 1. COCAH1 COCAL1 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC1 1 0 Compare enable 1 1 Capture on write operation into register CCL1 COCAH0,COCAL0: Compare/Capture mode for CRC register (Channel 0) COCAH0 COCAL0 Function 0 0 Compare/capture disable 0 1 Capture on falling/rising edge at pin CC0 1 0 Compare enable 1 1 Capture on write operation into register CRCL b. STC PCA 功能使用之暫存器說明： Mnemonic: CCON 7 6 CF CR 5 - 4 - 3 - 2 - 1 CCF1 Address: D8h 0 Reset CCF0 00H Mnemonic: CMOD 7 6 CIDL - 5 - 4 - 3 CPS2 2 CPS1 1 CPS0 Address: D9h 0 Reset ECF 00H CPS2 0 0 0 0 1 1 1 1 CPS1 0 0 1 1 0 0 1 1 CPS0 0 1 0 1 0 1 0 1 PCA/PWM 時鐘源輸入 Fosc/12 Fosc/2 定時器 0 的溢出 ECI(P1.2 or P4.1)外部時鐘輸入；最大 Fosc/2 Fosc Fosc/4 Fosc/6 Fosc/8 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 26 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: CCAPMn, n:0,1 7 6 5 ECOMn CAPPn- 4 CAPNn 3 MATn 2 TOGn ECOMn 0 1 1 1 CAPPn0 0 1 0 CAPNn 0 0 0 1 MATn 0 0 0 0 TOGn 0 0 0 0 PWMn 0 1 1 1 ECCFn 0 0 1 1 1 1 1 0 0 1 1 X 1 0 0 0 0 X X 0 1 0 0 0 X X 1 1 0 0 0 X 1 1 0 0 0 0 1 1 0 1 0 0 X X 1 PWMn Address: DAh,DBh 0 Reset ECCFn 00H 模塊功能 無此操作 8 位 PWM,無中斷 8 位 PWM,由低變高可產生中斷 8 位 PWM,由高變低可產生中斷 8 位 PWM, 由低變高或者由高變低 均可產生中斷 16 位捕獲模式,由 CEXn/PCAn 的上 升沿觸發 16 位捕獲模式,由 CEXn/PCAn 的下 降沿觸發 16 位捕獲模式,由 CEXn/PCAn 的跳 變觸發 16 位軟件定時器 16 位高速輸出 Mnemonic: CL 7 6 5 4 3 2 1 Address: E9h 0 Reset 00H Mnemonic: CH 7 6 5 4 3 2 1 Address: F9h 0 Reset 00H Mnemonic: CCAPnL, n:0,1 7 6 5 4 3 2 1 Address: EAh,EBh 0 Reset 00H Mnemonic: CCAPnH, n:0,1 7 6 5 4 3 2 1 Address: FAh,FBh 0 Reset 00H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 27 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件七：PWM 設定不同說明 新茂提供四個通道之 PWM 功能於 P4.0~P4.3，且有獨立之中斷向量。 STC 之 PWM 功能與 PCA 功能共用 I/O。 1. 新茂與 STC PWM 功能比較： 中斷向量 通道數 特點 新茂 0x43H 1. 4 個 10 位 PWM 模塊。 PWM0(P4.0) PWM1(P4.1) PWM2(P4.2) PWM3( P4.3) 1. 使用獨立之 I/O 及中斷向量。 2. 可設定 PWM I/O 之初始位準。 3. STC 0x3BH(與 PCA 共用) 1. 2 個 8 位 PWM 模塊。 PWM0(P1.3 or P4.2) PWM1(P1.4 or P4.3) 1. 與 PCA 共用 I/O 及中斷向量。 2. I/O 需設定成雙向口或輸出口，並 需加輸出限流電阻 1K~10K。 2. 新茂與 STC PWM 特殊功能暫存器比較： 特殊功能暫存器名稱 功能設定 PWM 最大值低位元 PWM 最大值高位元 PWM 模塊 0 低位元 PWM 模塊 0 高位元 PWM 模塊 0 輔助暫存器 PWM 模塊 1 低位元 PWM 模塊 1 高位元 PWM 模塊 1 輔助暫存器 PWM 模塊 2 低位元 PWM 模塊 2 高位元 PWM 模塊 3 低位元 PWM 模塊 3 高位元 新茂名稱及位址 PWMC (0xB5H) PWMMDL (0xCFH) PWMMDH (0xCEH) PWMD0L (0xBDH) PWMD0H (0xBCH) 無 PWMD1L (0xBFH) PWMD1H (0xBEH) 無 PWMD2L (0xB2H) PWMD2H (0xB1H) PWMD3L (0xB4H) PWMD3H (0xB3H) STC 名稱及位址 CMOD (0xD9H) CCAPM0 (0xDAH) CCAPM1 (0xDBH) CL (0xE9H) 無 CCAP0L (0xEAH) CCAP0H (0xFAH) PCA_PWM0(0xF2H) CCAP1L (0xEBH) CCAP1H (0xFBH) PCA_PWM1(0xF3H) 無 無 無 無 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 28 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 3. 新茂與 STC PWM 之特殊功能暫存器說明： a. 新茂 PWM 功能使用之暫存器說明： Mnemonic: PWMC 7 6 PWMCS[2:0] 5 4 - Address: B5h 3 2 1 0 Reset PWM3EN PWM2EN PWM1EN PWM0EN 00H PWMCS[2:0]: PWM clock select. PWMCS [2:0] Mode 000 Fosc 001 Fosc/2 010 Fosc/4 011 Fosc/6 100 Fosc/8 101 Fosc/12 110 Timer 0 overflow 111 Timer 0 external input (P3.4/T0) PWM3EN: PWM channel 3 enable control bit. PWM3EN = 1 – PWM channel 3 enable. PWM3EN = 0 – PWM channel 3 disable. PWM2EN: PWM channel 2 enable control bit. PWM2EN = 1 – PWM channel 2 enable. PWM2EN = 0 – PWM channel 2 disable. PWM1EN: PWM channel 1 enable control bit. PWM1EN = 1 – PWM channel 1 enable. PWM1EN = 0 – PWM channel 1 disable. PWM0EN: PWM 0 enable control bit. PWM0EN = 1 – PWM channel 0 enable. PWM0EN = 0 – PWM channel 0 disable. Mnemonic: PWMDnH, n:0,1,2,3 7 6 5 4 PWMPn - 3 - Mnemonic: PWMDnL, n:0,1,2,3 7 6 5 4 3 PWMDn[7:0] 2 - 2 Address: BCh,BEh,B1h,B3h 1 0 Reset PWMDn[9:8] 00H Address: BDh,BFh,B2h,B4h 1 0 Reset 00h PWMPn: PWM channel n idle polarity select. “0” – PWM channel n will idle low. “1” – PWM channel n will idle high. PWMDn[9:0]: PWM channel n data register. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 29 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: PWMMDH 7 6 5 Mnemonic: PWMMDL 7 6 5 4 - 3 - 4 3 PWMMD[7:0] 2 - 2 Address: CEh 1 0 Reset PWMMD[9:8] 00H 1 Address: CFh 0 Reset FFH PWMMD[9:0]: PWM Max Data register. PWM count from 0000h to PWMMD[9:0]. When PWM count data equal PWMMD[9:0] is overflow. 當使用新茂之 PWM 功能時，僅需對 PWMC 中 PWMnEN 置位即可。 當 PWMDn[9:0]之值小於 PWMMD[9:0]時，PWMn 口輸出狀態不變。 當 PWMDn[9:0]之值等於 PWMMD[9:0]時，PWMn 口輸出狀態改變。 當 PWMPn= 0 & PWMDn[9:0] = 00h 時，PWMn 口輸出固定為低。 當 PWMPn= 1 & PWMDn[9:0] = 00h 時，PWMn 口輸出固定為低。 b. STC PWM 功能使用之暫存器說明： Mnemonic: CMOD 7 6 CIDL - CPS2 0 0 0 0 1 1 1 1 CPS1 0 0 1 1 0 0 1 1 5 - 4 - CPS0 0 1 0 1 0 1 0 1 Mnemonic: CCAPMn, n:0,1 7 6 5 ECOMn CAPPn- 3 CPS2 2 CPS1 1 CPS0 Address: D9h 0 Reset ECF 00H PCA/PWM 時鐘源輸入 Fosc/12 Fosc/2 定時器 0 的溢出 ECI(P1.2 or P4.1)外部時鐘輸入；最大 Fosc/2 Fosc Fosc/4 Fosc/6 Fosc/8 4 CAPNn 3 MATn 2 TOGn 1 PWMn Address: DAh,DBh 0 Reset ECCFn 00H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 30 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note ECOMn 0 1 1 1 CAPPn0 0 1 0 CAPNn 0 0 0 1 MATn 0 0 0 0 TOGn 0 0 0 0 PWMn 0 1 1 1 ECCFn 0 0 1 1 1 1 1 0 0 1 1 X 1 0 0 0 0 X X 0 1 0 0 0 X X 1 1 0 0 0 X 1 1 0 0 0 0 1 1 0 1 0 0 X X Mnemonic: CL 7 6 模塊功能 無此操作 8 位 PWM,無中斷 8 位 PWM,由低變高可產生中斷 8 位 PWM,由高變低可產生中斷 8 位 PWM, 由低變高或者由高變低 均可產生中斷 16 位捕獲模式,由 CEXn/PCAn 的上 升沿觸發 16 位捕獲模式,由 CEXn/PCAn 的下 降沿觸發 16 位捕獲模式,由 CEXn/PCAn 的跳 變觸發 16 位軟件定時器 16 位高速輸出 5 4 3 2 1 Address: E9h 0 Reset 00H Mnemonic: CCAPnL, n:0,1 7 6 5 4 3 2 1 Address: EAh,EBh 0 Reset 00H Mnemonic: CCAPnH, n:0,1 7 6 5 4 3 2 1 Address: FAh,FBh 0 Reset 00H Mnemonic: PCA_PWMn, n:0,1 7 6 5 4 - 3 - 2 - 1 EPCnH Address: F2h,F3h 0 Reset EPCnL 00H 當使用 STC 之 PWM 功能時，CCAPMn 中 PWMn 及 ECOMn 位必須置位。 當 CL 的值小於﹛EPCnL，CCAPnL﹜時，PWMn 口輸出為高。 當 CL 的值大於﹛EPCnL，CCAPnL﹜時，PWMn 口輸出為低。 當 CL 的值由 FF 變為 00 溢出時，﹛EPCnH，CCAPnH﹜的內容裝載到﹛EPCnL，CCAPnL﹜中。 當 EPCnL=0 及 CCAPnL=00 時，PWMn 口輸出固定為高。 當 EPCnL=1 及 CCAPnL=FF 時，PWMn 口輸出固定為低。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 31 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件八：MDU 設定說明 新茂提供硬體快速的除法運算(32/16-bit & 16/16-bit division)、乘法運算( 16*16-bit multiplication )、位 移功能(32-bit shift)及歸一化(normalize)功能。 STC 並未提供此硬體功能。 1. 新茂 MDU 使用之特殊功能暫存器： Mnemonic Description Direct PCON Power control Arithmetic Control register Multiplication/Divi sion Register 0 Multiplication/Divi sion Register 1 Multiplication/Divi sion Register 2 Multiplication/Divi sion Register 3 Multiplication/Divi sion Register 4 Multiplication/Divi sion Register 5 87H Bit 6 Bit 5 Bit 4 Multiplication Division Unit SMOD MDUF - EFh MDEF ARCON MD0 MD1 MD2 MD3 MD4 MD5 Bit 7 MDOV Bit 3 Bit 2 Bit 1 Bit 0 RESET - - STOP IDLE 40H SLR SC[4:0] 00H 00H E9h MD0[7:0] EAh MD1[7:0] EBh MD2[7:0] ECh MD3[7:0] EDh MD4[7:0] 00H EEh MD5[7:0] 00H 00H 00H 00H 2. 新茂 MDU 功能使用之暫存器說明： Mnemonic: PCON 7 6 SMOD MDUF 5 - 4 - 3 - 2 - 1 STOP Address: 87h 0 Reset IDLE 40h MDUF: MDU finish flag. When MDU is finished, the MDUF will be set by hardware and the bit will clear by hardware at next calculation. Mnemonic: ARCON 7 MDEF 6 MDOV 5 SLR Address: EFh 4 3 2 SC[4:0] 1 0 Reset 00H MDEF: Multiplication Division Error Flag. The MDEF is an error flag. The error flag is read only. The error flag indicates an improperly performed operation (when one of the arithmetic operations has been restarted or interrupted by a new operation). The Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 32 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note error flag mechanism is automatically enabled with the first write to MD0 and disabled with the final read instruction from MD3 multiplication or shift/normalizing) or MD5 (division) in phase three. The error flag is set when: 1. Phase two in process and write access to mdx registers (restart or interrupt calculations) The error flag is reset only if: Phase two finished (arithmetic operation successful completed) and read access to MDx registers. MDOV: Multiplication Division Overflow flag. The overflow flag is read only. The overflow flag is set when: 1. Division by Zero 2. Multiplication with a result greater then 0000FFFFh 3. Start of normalizing if the most significant bit of MD3 is set(MD3.7=1) The overflow flag is reset when: Write access to MD0 register(Start Phase one) SLR: Shift direction bit. SLR = 0 – shift left operation. SLR = 1 – shift right operation. SC[4:0]: Shift counter. When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains the number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift operation is started. The number of shifts performed is determined by the count written to sc.4 to sc.0. sc.4 – MSB ... sc.0 – LSB 3. MDU 功能操作說明： 步驟一： 寫入 MDx（x = 0~5）暫存器，說明如下： 使用MDU運算時，必須注意寫入的順序；所有的應用當中MD0都是在第一個被寫入(First write)的暫存 器，其它暫存器仍必須依順序寫入，而當最後一個暫存器被寫入(Last write)時，MDU即開始做運算處理： Operation First write Last write 32bit/16bit MD0 Dividend Low MD1 Dividend MD2 Dividend MD3 Dividend High MD4 Divisor Low MD5 Divisor High 16bit/16bit MD0 Dividend Low MD1 Dividend High MD4 Divisor Low MD5 Divisor High 16bit x 16bit MD0 Multiplicand Low MD4 Multiplicator Low MD1 Multiplicand High shift/normalizing MD0 LSB MD1 MD2 MD3 MSB MD5 Multiplicator High ARCON start conversion 步驟二： 執行計算 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 33 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note MDU是否完成計算，可由MDUF(PCON.6)旗標判斷；當完成時由硬體設定為”1”，在下一次執行計算時 硬體會自動清除。 步驟三： 由MDx（x = 0~5）暫存器讀取結果： 讀取的順序唯一要注意的是“Last read”，此位元組的部份必須最後才被讀出。 Operation First read Last read 32Bit/16Bit MD0 Quotient Low MD1 Quotient MD2 Quotient MD3 Quotient High MD4 Remainder L MD5 Remainder H 16Bit/16Bit MD0 Quotient Low MD1 Quotient High MD4 Remainder Low MD5 Remainder High 16Bit x 16Bit MD0 Product Low MD1 Product MD2 Product shift/normalizing MD0 LSB MD1 MD2 MD3 Product High MD3 MSB Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 34 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件九：ADC設定不同說明 新茂提供八個通道之 ADC 功能於 P1.0~P1.7，且有獨立之中斷向量。 1. 新茂與 STC ADC 功能比較： 中斷向量 通道數 特點 新茂 0x53H 1. 8 個 10 位 ADC 模塊。 ADC0(P1.0) ADC1(P1.1) ADC2(P1.2) ADC3(P1.3) ADC4(P1.4) ADC5(P1.5) ADC6(P1.6) ADC7(P1.7) 1. ADC 轉換時間有 32 組可選擇。 2. ADC 轉換速度達為 500KHz。 STC 0x2BH 1. 8 個 10 位 ADC 模塊。 ADC0(P1.0) ADC1(P1.1) ADC2(P1.2) ADC3(P1.3) ADC4(P1.4) ADC5(P1.5) ADC6(P1.6) ADC7(P1.7) 1. ADC 轉換時間只有 4 組可選擇。 2. ADC 轉換速度為 250KHz。 2. 新茂與 STC ADC 特殊功能暫存器比較： 特殊功能暫存器名稱 ADC 通道致能 ADC 轉換功能控制設定 ADC 轉換結果高位元 ADC 轉換結果低位元 新茂名稱及位址 ADCC1 (0xABH) ADCC2 (0xACH) ADCCS (0xAFH) ADCDH(0xADH) ADCDL (0xAEH) STC 名稱及位址 P1ASF (0x9DH) ADC_CONTR (0xBCH) AUXR1(0xA2H) ADC_RES(0xBDH) ADC_RESL (0xBEH) 3. 新茂與 STC ADC 之特殊功能暫存器說明： a. 新茂 ADC 功能使用之暫存器說明： Mnemonic: ADCC1 Address: ABh 7 6 5 4 3 2 1 0 Reset ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN 00H ADC7EN: ADC channels 7 enable. ADC7EN = 1 – Enable ADC channel 7 ADC6EN: ADC channels 6 enable. ADC6EN = 1 – Enable ADC channel 6 ADC5EN: ADC channels 5 enable. ADC5EN = 1 – Enable ADC channel 5 ADC4EN: ADC channels 4 enable. ADC4EN = 1 – Enable ADC channel 4 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 35 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note ADC3EN: ADC channels 3 enable. ADC3EN = 1 – Enable ADC channel 3 ADC2EN: ADC channels 2 enable. ADC2EN = 1 – Enable ADC channel 2 ADC1EN: ADC channels 1 enable. ADC1EN = 1 – Enable ADC channel 1 ADC0EN: ADC channels 0 enable. ADC0EN = 1 – Enable ADC channel 0 Mnemonic: ADCC2 7 6 5 4 3 Start ADJUST - - - Address: ACh Rese 1 0 t ADCCH[2:0] 00H 2 Start: When this bit is set, the ADC will be start conversion. ADJUST: Adjust the format of ADC conversion DATA. ADJUST = 0: (default value) ADC data high byte ADCD [9:2] = ADCDH [7:0]. ADC data low byte ADCD [1:0] = ADCDL [1:0]. ADJUST = 1: ADC data high byte ADCD [9:8] = ADCDH [1:0]. ADC data low byte ADCD [7:0] = ADCDL [7:0]. ADCCH[2:0]: ADC channel select. ADCCH [2:0] Channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 ADJUST = 0: Mnemonic: ADCDH Address: ADh 7 6 5 4 3 2 1 0 Reset ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] 00H Mnemonic: ADCDL 7 6 ADJUST = 1: Mnemonic: ADCDH 7 6 - 5 - 5 - 4 - 4 - 3 - 2 - 3 - 1 ADCD[1] 2 - Address: AEh 0 Reset ADCD[0] 00H Address: ADh 1 0 Reset ADCD[9] ADCD[8] 00H Mnemonic: ADCDL Address: AEh 7 6 5 4 3 2 1 0 Reset ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] 00H ADCD[9:0]: ADC data register. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 36 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: ADCCS 7 6 - 5 - Address: AFh 4 3 2 1 0 Reset ADCCS[4] ADCCS[3] ADCCS[2] ADCCS[1] ADCCS[0] 00H ADCCS[4:0]: ADC clock select. *The ADC clock maximum 12.5MHz. *The ADC Conversion rate maximum 500KHz. ADCCS[4:0] ADC Clock(HZ) Clocks for ADC Conversion 00000 Fclk/2 46 00001 Fclk/4 92 00010 Fclk/6 138 00011 Fclk/8 184 00100 Fclk/10 230 00101 Fclk/12 276 00110 Fclk/14 322 00111 Fclk/16 368 01000 Fclk/18 414 01001 Fclk/20 460 01010 Fclk/22 506 01011 Fclk/24 552 01100 Fclk/26 598 01101 Fclk/28 644 01110 Fclk/30 690 01111 Fclk/32 736 10000 Fclk/34 782 10001 Fclk/36 828 10010 Fclk/38 874 10011 Fclk/40 920 10100 Fclk/42 966 10101 Fclk/44 1012 10110 Fclk/46 1058 10111 Fclk/48 1104 11000 Fclk/50 1150 11001 Fclk/52 1196 11010 Fclk/54 1242 11011 Fclk/56 1288 11100 Fclk/58 1334 11101 Fclk/60 1380 11110 Fclk/62 1426 11111 Fclk/64 1472 Fclk 2 × ( ADCCS + 1) ADC_Clock ADC _ Conversion _ Rate = 23 ADC _ Clock = Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 37 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note b. STC ADC 功能使用之暫存器說明： Mnemonic: P1ASF 7 6 P17ASF P16ASF Mnemonic: ADC_CONTR 7 6 ADC_POWER SPEED1 5 P15ASF 5 SPEED0 4 P14ASF 3 P13ASF 4 ADC_FLAG 2 P12ASF 1 P11ASF 3 ADC_START 2 CHS2 Address: 9Dh 0 Reset P10ASF 00H 1 CHS1 Address: BCh 0 Reset CHS0 00H ADC_POWER: =0：關閉 ADC 電源 SPEED[1:0] ADC 轉換速度控制. SPEED [1:0] A/D 轉換所需時間 00 540 個時鐘周期 01 360 個時鐘周期 10 180 個時鐘周期 11 90 個時鐘周期 ADC_FLAG: =1：A/D 轉換完成，並產生中斷，需由軟體清”0” ADC_START =1：A/D 開始轉換，轉換結束後為”0” CHS[2:0]: ADC channel select. CHS [2:0] Channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Mnemonic: AUXR1 7 6 5 PCA_P4 SPI_P4 4 S2_P4 ADRJ = 0: Mnemonic: ADC_RES 7 6 5 3 GF2 4 2 ADRJ 3 Address: A2H 0 Reset DPS 00H 1 - 2 1 ADC_RES9 ADC_RES8 ADC_RES7 ADC_RES6 ADC_RES5 ADC_RES4 ADC_RES3 Mnemonic: ADC_RESL 7 6 5 ADRJ= 1: Mnemonic: ADC_RES 7 6 5 - 4 - 4 - 3 - 2 - 3 - 1 ADC_RES1 2 - 1 ADC_RES9 Address: BDh 0 Reset ADC_RES2 00H Address: BEh 0 Reset ADC_RES0 00H Address: BDh 0 Reset ADC_RES8 00H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 38 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: ADC_RESL 7 6 5 4 3 2 1 ADC_RES7 ADC_RES6 ADC_RES5 ADC_RES4 ADC_RES3 ADC_RES2 ADC_RES1 Address: BEh 0 Reset ADC_RES0 00H ADC_RES[9:0]: ADC data register. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 39 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件十：SPI 設定不同說明 1. 新茂與 STC SPI 功能比較： 中斷向量 通道數 特點 新茂 0x4BH 1. SPI 模塊 I/O 說明。 SPI_SS(P1.4 or P4.0) SPI_MOSI(P1.5 or P4.1) SPI_MISO(P1.6 or P4.2) SPI_CLK(P1.7 or P4.3) 1. SPI_CLK 有 8 組可選擇。 2. 有全雙工模式，可同時傳送及接 收。 STC 0x4BH 1. SPI 模塊 I/O 說明。 SS(P1.4 or P4.0) MOSI(P1.5 or P4.1) MISO(P1.6 or P4.2) SPICLK(P1.7 or P4.3) 1. SPICLK 只有 4 組可選擇。 2. 不可同時傳送及接收。 2. 新茂與 STC SPI 特殊功能暫存器比較： 特殊功能暫存器名稱 通道切換 功能設定 1 功能設定 2 狀態暫存器 傳送資料緩衝器 接收資料緩衝器 新茂名稱及位址 AUX.P4SPI(0x91H.5) SPIC1 (0xF1H) SPIC2 (0xF2H) SPIS (0xF5H) SPITxD (0xF3H) SPIRxD (0xF4H) STC 名稱及位址 AUXR1.SPI_P4(0xA2H.5) SPCTL(0xCEH) SPSTAT(0xCDH) SPDAT (0xCFH) 3. 新茂與 STC SPI 之特殊功能暫存器說明： a. 新茂 SPI 功能使用之暫存器說明： SPI Description Direct Bit 7 AUX Auxiliary register SPI control register 1 SPI control register 2 SPI status register SPI transmit data buffer SPI receive data buffer 91h BRGS F1h SPIEN SPIMSS F2h SPIFD F5h - SPIC1 SPIC2 SPIS SPITXD SPIRXD Bit 6 Bit 5 SPI function P4CC P4SPI SPISSP Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET P4UR1 P4IIC P0KBI - DPS 00H SPICKP SPICKE SPIBR[2:0] 08H - RBC[2:0] 00H TBC[2:0] SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS 40H F3h SPITXD[7:0] 00H F4h SPIRXD[7:0] 00H Mnemonic: AUX 7 6 5 BRGS P4CC P4SPI 4 P4UR1 3 P4IIC 2 P0KBI 1 - Address: 91h 0 Reset DPS 00H Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 40 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note P4SPI: P4SPI = 0 – SPI function on P1. P4SPI = 1 – SPI function on P4. P4SPI setting SPI_SS P1.4 0 P4.0 1 Mnemonic: SPIC1 7 6 SPIEN SPIMSS 5 SPISSP SPI_MOSI P1.5 P4.1 4 SPICKP 3 SPICKE SPI_MISO P1.6 P4.2 2 SPI_CLK P1.7 P4.3 Address: F1h 1 0 Reset SPIBR[2:0] 08h SPIEN: SPI 模組致能旗標： “1” – 致能 “0” – 禁能 SPIMSS: 主從模式選擇旗標（Master or Slave mode Select） “1” – MCU 做為 Master mode. “0” – MCU 做為 Slave mode. SPISSP: (SS)引腳致能狀態旗標；當 MCU 為 slave 時，可由旗標設定 Slave Select (SS)引腳致能狀態 (slave mode used only) “1” – 高準位致能 high active. “0” – 低準位致能 low active. SPICKP: 時脈閒置準位旗標(master mode used only) “1” – 時脈信號閒置時為高準位(SCK high during idle), Ex : “0” – 時脈信號閒置時為低準位(SCK high during idle), Ex : SPICKE: 時脈取樣旗標 Clock sample edge select. “1” – 正緣取樣 data latch in rising edge “0” – 負緣取樣 data latch in falling edge. * 為確保資料取樣的正確性，無論使用正緣或負緣取樣，時脈及資料同步時皆需有足夠的準備時間 (set-up time)及保持時間(hold time)，時序產生如下圖： sufficient set-up time sufficient hold time SPIBR[2:0]: SPI 鮑率選擇(master mode used only), Fosc 為晶振頻率： SPIBR[2:0] Baud rate Fosc/4 0:0:0 Fosc/8 0:0:1 Fosc/16 0:1:0 Fosc/32 0:1:1 Fosc/64 1:0:0 Fosc/128 1:0:1 Fosc/256 1:1:0 Fosc/512 1:1:1 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 41 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: SPIC2 7 6 5 SPIFD TBC[2:0] 4 3 - 2 1 RBC[2:0] Address: F2h 0 Reset 00h SPIFD: 全雙工模式致能旗標(Full-duplex mode enable) “1” : 全雙工模式致能 “0” : 全雙工模式禁能 當該旗標致能時，TBC[2:0]和RBC[2:0]會被清除並保持為零，SPI全雙工模式僅允許8位元通訊． Master透過MOSI引腳做資料輸出，slave時透過MISO回傳資料，SPI的時脈信號由master主控產 生；所有資料 (輸出及輸入) 皆和時脈同步。 Input Shift register SPIRXD Output Shift register SPITXD Clock Generator MISO MISO MOSI MOSI SCK SCK SyncMos Master Output Shift register SPITXD Input Shift register SPIRXD SyncMos Slave TBC[2:0]: SPI 傳送元位計數旗標(SPI transmitter bit counter) 可設定 1~8 位元通訊，但全雙工模式僅允許 8 位元通訊。 TBC[2:0] Bit counter 8 bits output 0:0:0 1 bit output 0:0:1 2 bits output 0:1:0 3 bits output 0:1:1 4 bits output 1:0:0 5 bits output 1:0:1 6 bits output 1:1:0 7 bits output 1:1:1 RBC[2:0]: SPI 接收元位計數旗標(SPI receiver bit counter) 可設定 1~8 位元通訊，但全雙工模式僅允許 8 位元通訊。 RBC[2:0] Bit counter 8 bits input 0:0:0 1 bit input 0:0:1 2 bits input 0:1:0 3 bits input 0:1:1 4 bits input 1:0:0 5 bits input 1:0:1 6 bits input 1:1:0 1:1:1 7 bits input Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 42 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Mnemonic: SPIS 7 6 5 SPIMLS SPIOV 4 SPITXIF 3 SPITDR 2 SPIRXIF Address: F5h 0 Reset SPIRS 40h 1 SPIRDR SPIMLS: MSB or LSB output /input first “1” : 最高位元先傳送 (MSB output/input first)。 “0” : 最低位元先傳送 (LSB output/input first)。 SPIOV: 溢位旗標(Overflow flag) “1” : 當 SPIRDR 已設定（SPIRXD 原有資料未被讀取）且下一筆資料正寫入 SPIRXD 時，SPIOV 將被設定為”1”，告知 SPIRXD 資料以有損毀。 “0” : 當 SPIRDR 清為零時，SPIOV 則由硬體清除。 SPITXIF: 傳送中斷旗標(Transmit Interrupt Flag) “1” : 當 SPITXD 的資料已載入移位暫存器，由硬體設定為”1” 。 “0” : 傳送資料完成後必須由軟體清除。 SPITDR: 資料傳送位元(Transmit Data Ready) “1”: 當程序為傳送模式時，資料儲存至 SPITXD 後，由軟體設定此旗標為”1” ，告知 SPI module 允許傳出資料。 “0”: 當 SPI module 由 SPITXD 完成傳送時(或 SPITXD 被載至移位暫存器時)，此旗標則由硬體自 動清除。 SPIRXIF: 接收中斷旗標(Receive Interrupt Flag) “1” : 當 SPIRXD 被載入新一筆資料後，由硬體設定為”1” 。 “0” : 接收資料完成後必須由軟體清除。 SPIRDR: 資料接收位元(Receive Data Ready) “1” : SPI module接收資料時，SPIRDR由硬體自動設定為”1”，以告知MCU完成接收並儲存至 SPIRXD；當新的一筆資料寫入SPIRXD，而SPIRDR未清除時，SPIRXD原有的資料將被覆寫，產 生overflow “0” : 由 SPIRXD 讀取資料後，必須由軟體清除此旗標。 SPIRS: 接收開始位元(Receive Start) “1” : 由軟件設為”1”，告知 SPI 模組 SPIRXD 開始接收資料(即 SPI_CLK 開始送 clock)。 “0” : 當資料接收完成，由硬體清為”0” Mnemonic: SPITXD 7 6 5 4 3 SPITXD[7:0] 2 1 0 Address: F3h Reset 00h SPITXD[7:0]: 傳送資料緩衝器(Transmit data buffer) Mnemonic: SPIRXD 7 6 5 4 3 SPIRXD[7:0] 2 1 Address: F4h 0 Reset 00h SPIRXD[7:0]: 接收資料緩衝器(Receive data buffer) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 43 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note b. STC SPI 功能使用之暫存器說明： SPI Description Direct Bit 7 AUXR1 SPSTAT SPCTL SPITXD Auxiliary register 1 SPI Status register SPI control register SPI data register A2h CDh CEh CFh SPIF SSIG Mnemonic: AUXR1 7 6 PCA_P4 5 SPI_P4 Bit 6 Bit 5 SPI function PCA_P4 SPI_P4 WCOL SPEN DORD 4 S2_P4 SPI_P4: SPI_P4 = 0 – SPI function on P1. SPI_P4 = 1 – SPI function on P4. SPI_P4 setting /SS P1.4 0 P4.0 1 Mnemonic: SPSTAT 7 6 SPIF WCOL 5 - 4 - Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET S2_P4 MSTR GF2 CPOL ADJ CPHA SPR1 DPS SPR0 00H 0xH 04H 00H 3 GF2 2 ADJ MOSI P1.5 P4.1 3 - 1 - MISO P1.6 P4.2 2 - 1 - Address: A2h 0 Reset DPS 00H SPICLK P1.7 P4.3 Address: CDh 0 Reset 0xH SPIF: SPI 傳輸完成標志,當一次串行傳輸完成時,SPIF 置位,並當 ESPI 和 EA 都置位時產生中斷。 當 SPI 處於主模式且 SSIG=0 時,如果/SS 為輸入並被驅動為低電平,SPIF 也將置位。SPIF 標志通過軟件向其寫入”1”清零。 WCOL: SPI 寫衝突標志。在數據傳輸的過程中如果對 SPI 數據寄存器 SPDAT 執行寫操作,WCOL 將置位。WCOL 標志通過軟件向其寫入”1”清零。 Mnemonic: SPCTL 7 6 SSIG SPEN 5 DORD 4 MSTR 3 CPOL 2 CPHA 1 SPR1 Address: CEh 0 Reset SPR0 04H SSIG: /SS 忽略 =1,由 MSTR 確定器件為主機還是從機。 =0,/SS 腳用於確定器件為主機還是從機。/SS 腳可作為 I/O 口使用(見 SPI 主從選擇表) SPEN: SPI 使能 =1,SPI 使能。 =0,SPI 被禁止,所有 SPI 管腳都作為 I/O 口使用。 DORD: SPI 數據順序 =1,數據字的 LSB(最低位)最先發送。 =0,數據字的 MSB(最高位)最先發送。 MSTR: 主從模式選擇。(見 SPI 主從選擇表) CPOL: SPI 時鐘極性 =1,SPICLK 空閒時為高電平,SPICLK 的前時鐘沿為下降沿而後沿為上升沿。 =0,SPICLK 空閒時為低電平,SPICLK 的前時鐘沿為上升沿而後沿為下降沿。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 44 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note CPHA: SPI 時鐘相位選擇 =1,數據在 SPICLK 的前時鐘沿驅動,並在後時鐘沿採樣。 =0, 數據在/SS 為低(SSIG=0)時被驅動,在 SPICLK 的後時鐘沿被改變,並在前時鐘沿採樣。 (註：SSIG=1 時的操作未定義) SPR[1:0]: SPI 時鐘速率選擇控制位 =00,SPICLK=CPU_CLK/4 =01,SPICLK=CPU_CLK/16 =10,SPICLK=CPU_CLK/64 =11,SPICLK=CPU_CLK/256 Mnemonic: SPDAT 7 6 5 4 3 SPDAT[7:0] 2 1 0 Address: CFh Reset 00h SPDAT[7:0]: 數據寄存器(SPI data Register) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 45 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件十一：IIC 設定說明 新茂提供 IIC 介面功能，亦提供中斷功能，中斷向量為 0x6BH。 STC 並未提供此硬體功能。 1. 新茂 IIC 使用之特殊功能暫存器： Mnemonic Description Direct Bit 7 AUX IICCTL IICS Auxiliary register IIC control register IIC status register IIC Address 1 register IIC Address 2 register IIC Read/Write register IIC status2 register 91h F9h F8h BRGS IICEN MStart IICA1 IICA2 IICRWD IICS2 Bit 6 Bit 5 IIC function P4CC P4SPI MSS RXIF TXIF Bit 4 Bit 3 Bit 2 P4UR1 MAS RDR P4IIC RStart TDR P0KBI FAh IICA1[7:1] FBh IICA2[7:1] FCh FDh Bit 1 Bit 0 DPS IICBR[2:0] RXAK TXAK RW MATCH1 or RW1 MATCH2 or RW2 IICRWD[7:0] - - - - 3 P4IIC 2 P0KBI AB_EN 4 P4UR1 BF_EN AB_F BF 1 - Address: 91h 0 Reset DPS 00H P4IIC: P4IIC = 0 – IIC function on P1(P1.6 as IIC_SCL,P1.7 as IIC_SDA). P4IIC = 1 – IIC function on P4(P4.0 as IIC_SCL,P4.1 as IIC_SDA). Mnemonic: IICCTL 7 6 IICEN - 5 MSS 4 MAS 3 RStart 2 00H 04H 00H A0H 60H 00H 2. 新茂 IIC 功能使用之暫存器說明： Mnemonic: AUX 7 6 5 BRGS P4CC P4SPI RESET 1 IICBR[2:0] 0 Address: F9h Reset 04h IICEN: IC 致能位元(Enable IIC module) IICEN = 1，IIC 致能。 IICEN = 0，IIC 禁能。 MSS: 主從模式選擇位元 Master or slave mode select： MSS = 1，設定為 master mode。 MSS = 0，設定為 slave mode。 *要使用 IIC，在設定其它 IIC SFR 時，程序必須最先致能此位元。 MAS: 控制位址位元 Master address select (master mode only)： MAS = 0 ，選擇控制位址位元(control byte)由 SFR IICA1 送出。 MAS = 1 ，選擇控制位址位元(control byte)由 SFR IICA2 送出。 RStart: 重新起始位元 Re-start control bit (master mode only)： RStart = 0，在送出位置後旗標由硬件清除為”0” 。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 46 Ver. A 2010/02 00H SM59R04A2 Replace STC12C5A16S2 Application Note RStart = 1，由軟件設定，在收到 ACK 後，送出起始條件(start condition)及控制位址位元 (控制位址位元由 MAS)。 IICBR[2:0]: IIC 鮑率選擇元位 Baud rate selection (master mode only)： 系統頻率(Fosc)依據 MCU 外部晶振(或內部晶振)而定，預設值為 Fosc/512 。 IICBR[2:0] 000 001 010 011 100 101 110 111 Mnemonic: IICS 7 6 MStart RxIF Baud rate Fosc/32 Fosc/64 Fosc/128 Fosc/256 Fosc/512 Fosc/1024 Fosc/2048 Fosc/4096 5 TxIF 4 RDR 3 TDR 2 RxAK 1 TxAK Address: F8h 0 Reset RW 00h MStart: 起始位元 Master start control bit (master mode only) MStart = 1，由軟體設置為”1”，送出起始條件(start condition)及控制位址位元(控制位址位 元由 MAS)。 MStart = 0，由軟體清除為”0”，送出停止條件(stop condition)。 RxIF: 資料接收中斷旗標 Data receive interrupt flag Slaver 由此旗標可判斷資料是否已接收 RxIF = 1，當資料讀寫暫存器(IICRWD)載入資料完成時，由硬體設為”1”。 RxIF = 0，接收完成後必須由軟體清除。 TxIF: 資料傳送中斷旗標 Data transmit interrupt flag Master 由此旗標可判斷資料是否已傳出 TxIF = 1，當資料已由資料讀寫暫存器(IICRWD)載至位移暫存器，並已由位移暫存器傳送 時，TxIF 為”1” TxIF = 0，傳送資料完成後必須由軟體清除。 RDR: 資料接收完成位元 Read data ready RDR = 1，IIC module 接收資料至資料讀寫暫存器(IICRWD)時，由硬體自動設定為”1” 。 RDR = 0，當資料讀寫暫存器(IICRWD)完成接收後，必須由軟體清除為”0”；當 RDR = 0 時，IIC module 才可再次寫入新的資料至資料讀寫暫存器(IICRWD)。 TDR: 資料傳送完成位元 Transmit data ready TDR = 1，由程序將資料寫入資料讀寫暫存器(IICRWD)後，由軟體設定此旗標為”1” ，告 知硬件 IIC module 將資料傳出。 TDR = 0，當IIC module由資料讀寫暫存器(IICRWD)讀取資料並完成傳送時，此位元則由 硬體自動清除。 RxAK: 接收應答位元 Receive acknowledgement 當 IIC module 傳送資料時此位元為唯讀位元，等待接收端回覆應答(ACK/NACK)，不可由 程序編寫。 當 IIC module 為 master mode：傳出資料(8-bit)後，由 slaver 回覆應答位元(RxAK)。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 47 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 當 IIC module 為 slave mode：傳出資料(8-bit)後，由 master 回覆應答位元(RxAK)。 TxAK: 傳送應答位元 Transmit acknowledgement IIC module 當接收端時，接收資料完成後，回覆傳送端應答位元(ACK/NACK)。 RW: Slave mode read or write(read only) 1. 當 IIC module 為 slave mode 時，此位元為唯讀，不可由程序編寫。 2. 此位元由 master 的位址 IICA1(或 IICA2) 的 8th-bit 所控制： = 0 : master 要求 slaver 的 IIC module 為接收模式(即 master write, slaver read)。 = 1 : master 要求 slaver 的 IIC module 為傳送模式(即 master read, slaver write)。 Fig. Acknowledgement bit in the 9th bit of a byte transmission Mnemonic: IICA1 7 6 5 4 IICA1[7:1] R/W 3 2 1 Address: FAH Reset 0 Match1 or RW1 A0H R or R/W Slave mode: IICA1[7:1]: IIC Address registers 第一組控制位址 IICA1 共 7-bit，由軟件設定，當 slaver 接收到 master 的位址時，兩者會相互比對。 Match1: = 1，當 master 與 slaver 的控制位址 7-bit 相同時，slaver 的 8th-bit(Match1)由硬體設為”1” 。 = 0，當 IIC Stop 時，由該位元由硬體清為”0” 。 Master mode: IICA1[7:1]: IIC Address registers 1. 第一組控制位址 IICA1 共 7-bit，由軟件設定。 2. 當 MAS = 0，選擇控制位址位元(IICA1)。 (當 MAS = 1，選擇控制位址位元(IICA2)。) 3. 當 MStart 由軟體設置為”1”時，會送出起始條件(start condition)及控制位址位元(IICA1)。 RW1: 當 master 與 slave 的控制位址 7-bit 相同時，master 送出 8th-bit(R／W-bit)，告知 slaver 讀寫的狀 態 RW1= 1：為 master IIC module 接收模式(即 master read, slaver write)。 RW1= 0：為 master IIC module 傳送模式(即 master write, slaver read)。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 48 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note Fig. : RW bit in the 8th bit after IIC address Mnemonic: IICA2 7 6 5 Address: FBh 4 IICA2[7:1] R/W 3 2 1 0 Match2 or RW2 R or R/W Reset 60h Slave mode: IICA2[7:1]: IIC Address registers 第一組控制位址 IICA2 共 7-bit，由軟件設定，當 slaver 接收到 master 的位址時，兩者會相互比對。 Match2: = 1，當 master 與 slaver 的控制位址 7-bit 相同時，slaver 的 8th-bit(Match1)由硬體設為”1” 。 = 0，當 IIC Stop 時，由該位元由硬體清為”0” 。 Master mode: IICA2[7:1]: IIC Address registers 1. 第二組控制位址 IICA2 共 7-bit，由軟件設定。 2. 當 MAS = 1，選擇控制位址位元(IICA2)。 (當 MAS = 0，選擇控制位址位元(IICA1)。) 3. 當 MStart 由軟體設置為”1”時，會送出起始條件(start condition)及控制位址位元(IICA2)。 RW2: 當 master 與 slave 的控制位址 7-bit 相同時，master 送出 8th-bit(R／W-bit)，告知 slaver 讀寫的狀 態 RW1= 1：為 master IIC module 接收模式(即 master read, slaver write)。 RW1= 0：為 master IIC module 傳送模式(即 master write, slaver read)。 Mnemonic: IICRWD 7 6 5 4 3 IICRWD[7:0] 2 Address: FCh 0 Reset 00h 1 IICRWD[7:0]: IIC 資料讀寫暫存器(8-bit) IIC read write data buffer： IIC module 為接收模式(讀取)時，為接收資料的暫存區。 IIC module 為傳送模式(寫入)時，為傳送資料的暫存區。 Mnemonic: IICS2 Address: FDH 7 6 5 4 - - - - 3 AB_EN 2 1 0 Reset BF_EN AB_F BF 00H AB_EN: Arbitration lost enable bit. (Master mode only) If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred, Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 49 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost condition. Set this bit when multi-master and slave connection. Clear this bit when single master to single slave. BF_EN: 匯流排忙碌偵測致能位元 Bus busy enable bit. (Master mode only) 當該位元設置為”1”時，master IIC module將不會送出起啟訊號，直到BF=0。 當該位元清除為”0”時，master IIC module將不會BF=0或1 當系統有為”多個”主從元件時，請致能該偵測位元(BF_EN)。 當系統僅有”單一”主從元件時，可禁能該偵測位元(BF_EN)。 AB_F: Arbitration lost bit. (Master mode only) In multi-master condition, when send out data bit “1” but return back “0”, bus arbitration lost occurred and this bit will be set. Software need to clear this bit and check until BF=0 to resend data again. BF: 匯流排忙碌偵測位元 Bus busy bit. (Master mode only) 當偵測到SCL=0或SDA＝0或起啟訊號時，該位元由硬體設為”1”。 當偵測停止訊號或一週期性(4.7us)的訊號時，該位元由硬體清為”0”。 此位元也可由軟件清為”0”，使匯流排回到初始狀態。 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 50 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件十二：KBI 設定說明 新茂提供 8 個 I/O(Port 0 或 Port 2)可當鍵盤介面功能，8 個獨立的 flag(KBF.0~ KBF.7)，可由程式設定 為高電位或低電位觸發，此功能共用同一個中斷向量(0x5BH)。 STC 並未提供此硬體功能。 1. 新茂 KBI 使用之特殊功能暫存器： KBI AUX KBLS KBE KBF KBD IEN1 IRCON Description Auxiliary register KBI level selection KBI input enable KBI flag KBI De-bounce control register Interrupt Enable 1 register Interrupt request register Direct Bit 7 Bit 6 Bit 5 Bit 4 KBI function P4CC P4SPI P4UR1 KBLS6 KBLS5 KBLS4 KBE6 KBE5 KBE4 KBF6 KBF5 KBF4 Bit 3 Bit 2 Bit 1 Bit 0 RESET 91h 93h 94h 95h BRGS KBLS7 KBE7 KBF7 P4IIC KBLS3 KBE3 KBF3 P0KBI KBLS2 KBE2 KBF2 KBLS1 KBE1 KBF1 DPS KBLS0 KBE0 KBF0 00H 00H 00H 00H 96h KBDEN - - - - - KBD1 KBD0 00H B8h EXEN2 - IEIIC IELVI IEKBI IEADC IESPI IEPWM 00h C0H EXF2 TF2 IICIF LVIIF KBIIF ADCIF SPIIF PWMIF 00H 2. 新茂 KBI 功能使用之暫存器說明： Mnemonic: AUX 7 6 BRGS P4CC 5 P4SPI 4 P4UR1 3 P4IIC 2 P0KBI 1 - Address: 91h 0 Reset DPS 00H P0KBI: P0KBI = 0 – KBI function on P2. P0KBI = 1 – KBI function on P0. Mnemonic: KBLS 7 6 KBLS.7 KBLS.6 5 KBLS.5 4 KBLS.4 3 KBLS.3 2 KBLS.2 1 KBLS.1 Address: 93h 0 Reset KBLS.0 00h KBLS.7: Keyboard Line 7 level selection bit 0 : enable a low level detection on KBI7. 1 : enable a high level detection on KBI7. KBLS.6: Keyboard Line 6 level selection bit 0 : enable a low level detection on KBI6. 1 : enable a high level detection on KBI6. KBLS.5: Keyboard Line 5 level selection bit 0 : enable a low level detection on KBI5. 1 : enable a high level detection on KBI5. KBLS.4: Keyboard Line 4 level selection bit 0 : enable a low level detection on KBI4. 1 : enable a high level detection on KBI4. KBLS.3: Keyboard Line 3 level selection bit 0 : enable a low level detection on KBI3. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 51 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 1 : enable a high level detection on KBI3. KBLS.2: Keyboard Line 2 level selection bit 0 : enable a low level detection on KBI2. 1 : enable a high level detection on KBI2. KBLS.1: Keyboard Line 1 level selection bit 0 : enable a low level detection on KBI1. 1 : enable a high level detection on KBI1. KBLS.0: Keyboard Line 0 level selection bit 0 : enable a low level detection on KBI0. 1 : enable a high level detection on KBI0. Mnemonic: KBE 7 6 KBE.7 KBE.6 5 KBE.5 4 KBE.4 3 KBE.3 2 KBE.2 1 KBE.1 Address: 94h 0 Reset KBE.0 00h KBE.7: Keyboard Line 7 enable bit 0 : enable standard I/O pin. 1 : enable KBF.7 bit in KBF register to generate an interrupt request. KBE.6: Keyboard Line 6 enable bit 0 : enable standard I/O pin. 1 : enable KBF.6 bit in KBF register to generate an interrupt request. KBE.5: Keyboard Line 5 enable bit 0 : enable standard I/O pin. 1 : enable KBF.5 bit in KBF register to generate an interrupt request. KBE.4: Keyboard Line 4 enable bit 0 : enable standard I/O pin. 1 : enable KBF.4 bit in KBF register to generate an interrupt request. KBE.3: Keyboard Line 3 enable bit 0 : enable standard I/O pin. 1 : enable KBF.3 bit in KBF register to generate an interrupt request. KBE.2: Keyboard Line 2 enable bit 0 : enable standard I/O pin. 1 : enable KBF.2 bit in KBF register to generate an interrupt request. KBE.1: Keyboard Line 1 enable bit 0 : enable standard I/O pin. 1 : enable KBF.1 bit in KBF register to generate an interrupt request. KBE.0: Keyboard Line 0 enable bit 0 : enable standard I/O pin. 1 : enable KBF.0 bit in KBF register to generate an interrupt request. Mnemonic: KBF 7 6 KBF.7 KBF.6 5 KBF.5 4 KBF.4 3 KBF.3 2 KBF.2 1 KBF.1 Address: 95h 0 Reset KBF.0 00h KBF.7: Keyboard Line 7 flag This is set by hardware when KBI7 detects a programmed level. It generates a Keyboard interrupt request if KBE.7 is also set. It must be cleared by software. KBF.6: Keyboard Line 6 flag This is set by hardware when KBI6 detects a programmed level. It generates a Keyboard interrupt request if KBE.6 is also set. It must be cleared by software. KBF.5: Keyboard Line 5 flag Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 52 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note This is set by hardware when KBI5 detects a programmed level. It generates a Keyboard interrupt request if KBE.5 is also set. It must be cleared by software. KBF.4: Keyboard Line 4 flag This is set by hardware when KBI4 detects a programmed level. It generates a Keyboard interrupt request if KBE.4 is also set. It must be cleared by software. KBF.3: Keyboard Line 3 flag This is set by hardware when KBI3 detects a programmed level. It generates a Keyboard interrupt request if KBE.3 is also set. It must be cleared by software. KBF.2: Keyboard Line 2 flag This is set by hardware when KBI2 detects a programmed level. It generates a Keyboard interrupt request if KBE.2 is also set. It must be cleared by software. KBF.1: Keyboard Line 1 flag This is set by hardware when KBI1 detects a programmed level. It generates a Keyboard interrupt request if KBE.1 is also set. It must be cleared by software. KBF.0: Keyboard Line 0 flag This is set by hardware when KBI0 detects a programmed level. It generates a Keyboard interrupt request if KBE.0 is also set. It must be cleared by software. Mnemonic: KBD 7 6 KBDEN - 5 - 4 - 3 - 2 - 1 KBD.1 Address: 96H 0 Reset KBD.0 00H KBDEN: Enable KBI de-bounce function. The default KBI function is enabled. KBDEN = 0, enable KBI de-bounce function. The de-bounce time is selected by KBD [1:0]. KBDEN = 1, disable KBI de-bounce function. The KBI input pin without de-bounce mechanism. KBD[1:0]: Select KBI de-bounce time. If KBDEN = “0”, the default de-bounce time is 320 ms. KBD[1:0] = 00, the de-bounce time is 320 ms. KBD[1:0] = 01, the de-bounce time is 160 ms. KBD[1:0] = 10, the de-bounce time is 80 ms. KBD[1:0] = 11, the de-bounce time is 40 ms. Mnemonic: IEN1 7 6 EXEN2 5 IEIIC 4 IELVI 3 IEKBI 2 IEADC 1 IESPI Address: B8h 0 Reset IEPWM 00h 1 SPIIF Address: C0h 0 Reset PWMIF 00H IEKBI: KBI interrupt enable. IEKBI = 0 – Disable KBI interrupt. IEKBI = 1 – Enable KBI interrupt. Mnemonic: IRCON 7 6 5 EXF2 TF2 IICIF 4 LVIIF 3 KBIIF 2 ADCIF KBIIF: KBI interrupt flag. Must be cleared by software. Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 53 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 附件十三：GPIO 設定不同說明 1. 新茂與 STC GPIO 功能比較： GPIO 之 4 種 I/O 型態 P4[7:4] GPIO 之致能 1. 2. 3. 4. 新茂 准雙向 I/O(預設) 推挽輸出 僅輸入(高阻抗) Open drain Only define by writer or ISP 1. 2. 3. 4. STC 准雙向 I/O(預設) 推挽輸出 僅輸入(高阻抗) Open drain P4SW[6:4]=1,the NA、ALE、EX_LVD define as P4.4、P4.5、P4.6 The RST can be define as P4.7 by ISP 特點 2. 新茂與 STC GPIO 特殊功能暫存器比較： 特殊功能暫存器名稱 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 P0 I/O 模式控制 0 P0 I/O 模式控制 1 P1 I/O 模式控制 0 P1 I/O 模式控制 1 P2 I/O 模式控制 0 P2 I/O 模式控制 1 P3 I/O 模式控制 0 P3 I/O 模式控制 1 P4 I/O 模式控制 0 P4 I/O 模式控制 1 P5 I/O 模式控制 0 P5 I/O 模式控制 1 P4 [6:4] I/O 切換 特殊功能 I/O 之切換 新茂名稱及位址 Port0(0x80H) Port1(0x90H) Port2(0xA0H) Port3(0xB0H) Port4(0xE8H) Port5(0xD8H) P0M0(0xD2H) P0M1(0xD3H) P1M0(0xD4H) P1M1(0xD5H) P2M0(0xD6H) P2M1(0xD7H) P3M0(0xDAH) P3M1(0xDBH) P4M0(0xDCH) P4M1(0xDDH) P5M0(0xDEH) P5M1(0xDFH) 無 AUX(0x91H) STC 名稱及位址 Port0(0x80H) Port1(0x90H) Port2(0xA0H) Port3(0xB0H) Port4(0xC0H) Port5(0xC8H) P0M0(0x94H) P0M1(0x93H) P1M0(0x92H) P1M1(0x91H) P2M0(0x96H) P2M1(0x95H) P3M0(0xB1H) P3M1(0xB2H) P4M0(0xB4H) P4M1(0xB3H) P5M0(0xCAH) P5M1(0xC9H) P4SW(0xBBH) AUXR1(0xA2H) Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 54 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 3. 新茂與 STC GPIO 之特殊功能暫存器說明： a. 新茂 GPIO 功能使用之暫存器說明： Mnemonic Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Mnemonic P0M0 P0M1 P1M0 P1M1 P2M0 P2M1 P3M0 P3M1 P4M0 P4M1 P5M0 P5M1 Mnemonic AUX Description Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Direct Bit 7 Bit 6 Bit 5 Ports Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET D8h E8h B0h A0h 90h 80h P4.7 P3.7 P2.7 P1.7 P0.7 P4.6 P3.6 P2.6 P1.6 P0.6 P4.5 P3.5 P2.5 P1.5 P0.5 P4.4 P3.4 P2.4 P1.4 P0.4 P5.3 P4.3 P3.3 P2.3 P1.3 P0.3 P5.2 P4.2 P3.2 P2.2 P1.2 P0.2 P5.1 P4.1 P3.1 P2.1 P1.1 P0.1 P5.0 P4.0 P3.0 P2.0 P1.0 P0.0 0Fh FFh FFh FFh FFh FFh Description Direct Port 0 output mode 0 Port 0 output mode 1 Port 1 output mode 0 Port 1 output mode 1 Port 2 output mode 0 Port 2 output mode 1 Port 3 output mode 0 Port 3 output mode 1 Port 4 output mode 0 Port 4 output mode 1 Port 5 output mode 0 Port 5 output mode 1 Description Direct Bit 7 Bit 6 91h BGRS P4CC Auxiliary register PxM1.y 0 0 1 1 D2h D3h D4h D5h D6h D7h DAh DBh DCh DDh DEh DFh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 I/O port function register P0M0 [7:0] P0M1[7:0] P1M0[7:0] P1M1[7:0] P2M0[7:0] P2M1[7:0] P3M0[7:0] P3M1[7:0] P4M0[7:0] P4M1[7:0] - PxM0.y 0 1 0 1 Bit 5 AUX P4SPI 6 P4CC Bit 1 Bit 0 RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H P5M0[3:0] P5M1[3:0] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET P4UR1 P4IIC P0KBI - DPS 00H Port output mode Quasi-bidirectional (standard 8051 port outputs) (pull-up) Push-pull Input only (high-impedance) Open drain Mnemonic: AUX 7 BRGS Bit 2 Address: 91h 5 P4SPI 4 P4UR1 3 P4IIC 2 P0KBI 1 - 0 DPS Reset 00H P4CC: P4CC = 0 – Capture/Compare function on P1. P4CC = 1 – Capture/Compare function on P4. P4CC 0 1 CC0 P1.0 P4.0 CC1 P1.1 P4.1 CC2 P1.3 P4.2 CC3 P1.4 P4.3 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 55 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note P4SPI: P4SPI = 0 – SPI function on P1. P4SPI = 1 – SPI function on P4. P4SPI 0 1 SS P1.4 P4.0 MOSI P1.5 P4.1 MISO P1.6 P4.2 SPI_CLK P1.7 P4.3 P4UR1: P4UR1 = 0 – Serial interface 1 function on P1. P4UR1 = 1 – Serial interface 1 function on P4. P4UR1 0 1 RXD1 P1.2 P4.2 TXD1 P1.3 P4.3 P4IIC: P4IIC = 0 – IIC function on P1. P4IIC = 1 – IIC function on P4. P4IIC 0 1 IIC_SCL P1.6 P4.0 IIC_SDA P1.7 P4.1 P0KBI: P0KBI = 0 – KBI function on P2. P0KBI = 1 – KBI function on P0. P0KBI 0 1 KBI0 P2.0 P0.0 KBI1 P2.1 P0.1 KBI2 P2.2 P0.2 KBI3 P2.3 P0.3 KBI4 P2.4 P0.4 KBI5 P2.5 P0.5 KBI6 P2.6 P0.6 KBI7 P2.7 P0.7 多 4 個 GPIO 之方法： 此顆 MCU 可用 ICP 或 ISP 等燒錄模式將 OCI_SCL、ALE、OCI_SDA and RESET 等 I/O 定義成 P4.4、 P4.5、P4.6 and P4.7。 各種封裝對應之 PIN 腳如下表： OCI_SCL/P4.4 ALE/P4.5 OCI_SDA/P4.6 RESET/P4.7 40-PIN PDIP 29 30 31 9 44-PIN PLCC 32 33 35 10 44-PIN PQFP 26 27 29 4 48-PIN LQFP 29 30 32 5 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 56 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note b. STC GPIO 功能使用之暫存器說明： Mnemonic Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Description Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Mnemonic Direct Bit 7 Bit 6 Bit 5 Ports Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET C8h C0h B0h A0h 90h 80h P4.7 P3.7 P2.7 P1.7 P0.7 P4.6 P3.6 P2.6 P1.6 P0.6 P4.5 P3.5 P2.5 P1.5 P0.5 P4.4 P3.4 P2.4 P1.4 P0.4 P5.3 P4.3 P3.3 P2.3 P1.3 P0.3 P5.2 P4.2 P3.2 P2.2 P1.2 P0.2 P5.1 P4.1 P3.1 P2.1 P1.1 P0.1 P5.0 P4.0 P3.0 P2.0 P1.0 P0.0 0Fh FFh FFh FFh FFh FFh Bit 1 Bit 0 Description Direct P0M0 P0M1 P1M0 P1M1 P2M0 P2M1 P3M0 P3M1 P4M0 P4M1 Port 0 output mode 0 Port 0 output mode 1 Port 1 output mode 0 Port 1 output mode 1 Port 2 output mode 0 Port 2 output mode 1 Port 3 output mode 0 Port 3 output mode 1 Port 4 output mode 0 Port 4 output mode 1 94h 93h 92h 91h 96h 95h B2h B1h B4h B3h P4SW P4 Switch BBH P5M0 P5M1 Port 5 output mode 0 Port 5 output mode 1 CAh C9h Mnemonic AUXR1 Description Auxiliary register PxM1.y 0 0 1 1 Bit 7 Bit 6 Bit 5 I/O port function register - Bit 3 P0M0 [7:0] P0M1[7:0] P1M0[7:0] P1M1[7:0] P2M0[7:0] P2M1[7:0] P3M0[7:0] P3M1[7:0] P4M0[7:0] P4M1[7:0] NA_ P4.4 - Direct Bit 7 Bit 6 A2h - PCA_P4 PxM0.y 0 1 0 1 ALE_ P4.5 LVD_ P4.6 Bit 4 Bit 5 AUX SPI_P4 6 PCA_P4 RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H - - - 0XH P5M0[3:0] P5M1[3:0] 00H 00H Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET S2_P4 GF2 ADRJ - DPS 00H Port output mode Quasi-bidirectional (standard 8051 port outputs) (pull-up) Push-pull Input only (high-impedance) Open drain Mnemonic: AUXR1 7 - Bit 2 Address: A2h 5 SPI_P4 4 S2_P4 3 GF2 2 ADRJ 1 - 0 DPS Reset 00H PCA_P4: PCA_P4 = 0 – Capture/Compare function on P1. PCA_P4 = 1 – Capture/Compare function on P4. PCA_P4 ECI PCA0/PWM0 PCA1/PWM1 0 P1.2 P1.3 P1.4 1 P4.1 P4.2 P4.3 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 57 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note SPI_P4: SPI_P4 = 0 – SPI function on P1. SPI_P4 = 1 – SPI function on P4. SPI_P4 0 1 SS P1.4 P4.0 MOSI P1.5 P4.1 MISO P1.6 P4.2 SPICLK P1.7 P4.3 S2_P4: S2_P4 = 0 – Serial interface 1 function on P1. S2_P4 = 1 – Serial interface 1 function on P4. S2_P4 0 1 RxD2 P1.2 P4.2 TxD2 P1.3 P4.3 Mnemonic: P4SW 7 - 6 LVD_P4.6 Address:BBh 5 ALE_P4.5 4 NA_P4.4 3 - 2 - 1 - 0 - Reset 0xH LVD_P4.6: LVD_P4.6 = 0 –是外部低壓檢測腳. LVD_P4.6 = 1 –設置成 P4.6 I/O. ALE_P4.5: ALE_P4.5 = 0 –是 ALE 信號腳. ALE_P4.5 = 1 –設置成 P4.5 I/O. NA_P4.4 NA_P4.4 = 0 –無任何功能. NA_P4.4 = 1 –設置成 P4.4 I/O. The RST can be define as P4.7 by ISP 各種封裝對應之 PIN 腳如下表： 40-PIN PDIP 44-PIN PLCC 44-PIN PQFP 48-PIN LQFP NA_P4.4 29 32 26 29 ALE_P4.5 30 33 27 30 LVD_P4.6 31 35 29 32 RESET/P4.7 9 10 4 5 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 58 Ver. A 2010/02 SM59R04A2 Replace STC12C5A16S2 Application Note 六、 注意事項： 七、 參考文件： 所有應用參考文件皆可於新茂網站 www.syncmos.com.tw 下載 Specifications subject to change without notice, contact your sales representatives for the most recent information. ISSFA-0167 59 Ver. A 2010/02