RD74VT1G86 2–input Exclusive–OR Gate / Dual Supply Voltage Translator REJ03D0516–0100 Rev.1.00 Apr. 15, 2005 Description The RD74VT1G86 performs the Boolean functions Y = A ⊕ B or Y = AB + AB in positive logic. A common application is as a true / complement element. If one of the inputs is low, the other input will be reproduced in true form at the output. If one of the inputs is high, the signal on the other input will be reproduced inverted form at the output. The input is designed to track VCCIN, which accepts voltage from 1.2V to 3.6V, and the output is designed to track VCCOUT, which operates at 1.2V to 3.6V. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • This product function as level shift that change VCCIN input level to VCCOUT output level by providing different supply voltage to VCCIN and VCCOUT. • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Supply voltage range: VCCIN = 1.2 V to 3.6 V VCCOUT = 1.2 V to 3.6 V Operating temperature range: –40 to +85°C • All inputs VIH (Max.) = 3.6 V (@VCCIN = 0 V to 3.6 V) Outputs VO (Max.) = 3.6 V (@VCCOUT = 0 V) ±2 mA (@VCCOUT = 1.2 V) • Output current ±4 mA (@VCCOUT = 1.4 V to 1.6 V) ±6 mA (@VCCOUT = 1.65 V to 1.95 V) ±18 mA (@VCCOUT = 2.3 V to 2.7 V) ±24 mA (@VCCOUT = 3.0 V to 3.6 V) • Ordering Information Part Name RD74VT1G86CLE Package Type Package Code (Previous Code) Package Abbreviation WCSP-6 pin SXBG0006KB–A (TBS-6AV) CL Article Indication Marking Year code Month code V8YM Rev.1.00 Apr. 15, 2005 page 1 of 8 Taping Abbreviation (Quantity) E (3,000 pcs/reel) RD74VT1G86 Function Table Inputs A Output Y B L L L L H H H L H H H L H: High level L: Low level Pin Arrangement Height 0.5 mm 0.5 mm pitch 0.23 mm 6–Ball (CL) GND 3 4 Y A 2 5 VCCOUT B 1 6 1.4 mm 0.9 mm Pin#1 INDEX VCCIN (Bottom view) (Top view) Logic Diagram A B Rev.1.00 Apr. 15, 2005 page 2 of 8 Y RD74VT1G86 Absolute Maximum Ratings Item Supply voltage range Symbol Ratings Unit VCCIN, VCCOUT –0.5 to 4.6 V VI –0.5 to 4.6 V VO –0.5 to VCCOUT+0.5 V Input voltage range *1 Output voltage range *1, 2 Conditions Output: “H” or “L” VCCOUT: OFF –0.5 to 4.6 Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 VO > VCC+0.5 50 Continuous output current IO ±50 mA Continuous output current VCC or GND ICCIN, ICCOUT, IGND ±100 mA θja 123 °C/W Tstg –65 to 150 °C Package Thermal impedance Storage temperature Notes: The absolute maximum ratings are values, which must st not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings ngs may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. Recommended Operating Conditions Item Supply voltage range Input/Output voltage Symbol Ratings Unit V VCCIN 1.2 to 3.6 VCCOUT 1.2 to 3.6 VI 0 to 3.6 V VO 0 to VCCOUT V IOH IOL –2 mA VCCOUT = 1.2 V –4 VCCOUT = 1.5±0.1 V –6 VCCOUT = 1.8±0.15 V –18 VCCOUT = 2.5±0.2 V –24 VCCOUT = 3.3±0.3 V 2 mA VCCOUT = 1.2 V 4 VCCOUT = 1.5±0.1 V 6 VCCOUT = 1.8±0.15 V 18 VCCOUT = 2.5±0.2 V 24 VCCOUT = 3.3±0.3 V Input transition rise or fall time ∆t / ∆v 10 ns / V Operation free-air temperature Ta –40 to 85 °C Rev.1.00 Apr. 15, 2005 page 3 of 8 Output: “H” or “L” VCCOUT: OFF 0 to 3.6 Output current Conditions RD74VT1G86 Electrical Characteristics (Ta = −40 to 85°C) Item Input voltage Symbol VCCIN (V) VIH VIL Output voltage VOH VOL * VCCOUT (V) * Min Typ Max Unit V VCCIN×0.75 1.5±0.1 VCCIN×0.70 1.8±0.15 VCCIN×0.65 2.5±0.2 1.6 3.3±0.3 2.0 VCCIN×0.25 1.2 1.2 1.2 to 3.6 1.2 to 3.6 1.5±0.1 VCCIN×0.30 1.8±0.15 VCCIN×0.35 2.5±0.2 0.7 3.3±0.3 0.8 VCCOUT−0.2 1.2 to 3.6 1.2 to 3.6 1.2 to 3.6 Test conditions V V IOH = –100 µA 1.2 0.9 IOH = –2 mA 1.5±0.1 1.1 IOH = –4 mA 1.8±0.15 1.25 IOH = –6 mA 2.5±0.2 1.7 IOH = –18 mA 3.3±0.3 2.2 IOH = –24 mA 1.2 to 3.6 0.2 1.2 0.3 IOL = 2 mA 1.5±0.1 0.3 IOL = 4 mA 1.8±0.15 0.3 IOL = 6 mA 2.5±0.2 0.6 IOL = 18 mA 3.3±0.3 0.55 IOL = 24 mA V IOL = 100 µA IIN 3.6 3.6 –1.0 1.0 µA VIN = GND or VCCIN Output leakage current IOFF 0 0 1.5 µA VIN, VOUT = 0 to 3.6 V Quiescent supply current ICCIN 1.2 to 3.6 1.2 to 3.6 –3.0 3.0 µA IO(Y port) = 0 VIN = VCCIN or GND ICCOUT 1.2 to 3.6 1.2 to 3.6 –3.0 3.0 Increase in ICC per input ∆ICC 3.6 3.6 250 µA A or B port VCCIN–0.6 (1 input) Input capacitance CIN 3.3 3.3 3.5 pF VIN = VCC or GND Input current IO(Y port) = 0 VIN = VCCIN or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.1.00 Apr. 15, 2005 page 4 of 8 RD74VT1G86 Switching Characteristics VCCIN = 3.3 ± 0.3 V Ta = –40 to 85°C VCCOUT= VCCOUT= VCCOUT= VCCOUT= VCCOUT= FROM TO 1.2V 1.5±0.1V 1.8±0.15V 2.5±0.2V 3.3±0.3V Test Symbol (Input) (Output) Typ Min Max Min Max Min Max Min Max Unit Propagation tPLH A or B Y 8.6 2.0 8.4 1.5 5.8 1.0 4.4 1.0 3.9 ns delay time tPHL 8.6 2.0 8.4 1.5 5.8 1.0 4.4 1.0 3.9 Item Conditions CL = 15 pF RL = 2.0 kΩ VCCIN = 2.5 ± 0.2 V Ta = –40 to 85°C VCCOUT= VCCOUT= VCCOUT= VCCOUT= FROM TO 1.2V 1.5±0.1V 1.8±0.15V 2.5±0.2V Symbol (Input) (Output) Typ Min Max Min Max Min Max Min Max Unit Propagation tPLH A or B Y 8.7 2.0 8.8 1.5 6.2 1.0 4.7 1.0 4.5 ns delay time tPHL 8.7 2.0 8.8 1.5 6.2 1.0 4.7 1.0 4.5 Item VCCOUT= 3.3±0.3V Test Conditions CL = 15 pF RL = 2.0 kΩ VCCIN = 1.8 ± 0.15 V Ta = –40 to 85°C VCCOUT= VCCOUT= VCCOUT= VCCOUT= VCCOUT= 1.5±0.1V 1.8±0.15V 2.5±0.2V 3.3±0.3V FROM TO 1.2V Symbol (Input) (Output) Typ Min Max Min Max Min Max Min Max Unit Propagation tPLH A or B Y 9.8 2.0 9.8 1.5 7.4 1.0 6.4 1.0 6.2 ns delay time tPHL 9.8 2.0 9.8 1.5 7.4 1.0 6.4 1.0 6.2 Item Test Conditions CL = 15 pF RL = 2.0 kΩ VCCIN = 1.5 ± 0.1 V Ta = –40 to 85°C FROM TO VCCOUT= VCCOUT= VCCOUT= VCCOUT= VCCOUT= 1.2V 1.5±0.1V 1.8±0.15V 2.5±0.2V 3.3±0.3V Test Symbol (Input) (Output) Typ Min Max Min Max Min Max Min Max Unit Propagation tPLH A or B Y 10.5 2.0 11.2 1.5 10.0 1.0 9.0 1.0 8.8 ns delay time tPHL 10.5 2.0 11.2 1.5 10.0 1.0 9.0 1.0 8.8 Item Conditions CL = 15 pF RL = 2.0 kΩ VCCIN = 1.2 V Ta = –40 to 85°C VCCOUT= VCCOUT= VCCOUT= VCCOUT= VCCOUT= FROM TO 1.2V 1.5±0.1V 1.8±0.15V 2.5±0.2V 3.3±0.3V Symbol (Input) (Output) Typ Typ Typ Typ Typ Unit Propagation tPLH A or B Y 12.0 10.5 9.5 9.5 9.5 ns delay time tPHL 12.0 10.5 9.5 9.5 9.5 Item Rev.1.00 Apr. 15, 2005 page 5 of 8 Test Conditions CL = 15 pF RL = 2.0 kΩ RD74VT1G86 Operating Characteristics Ta = 25°C Item Power dissipation capacitance Symbol VCCIN (V) VCCOUT (V) Min Typ Max Unit CPD 3.3 3.3 — 12 — pF Test Conditions f = 10 MHz CL = 0 Power-up Considerations Level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems. 1. Connect ground before any supply voltage is applied. 2. Next, power up the input side of the device. (Power up of VCCIN is first. Next power up is VCCOUT) Test Circuit VCCIN Pulse Generator Z out = 50 Ω A or B VCCOUT Y Output CL =15 pF Note: CL includes probe and jig capacitance. Rev.1.00 Apr. 15, 2005 page 6 of 8 RL =2.0 kΩ RD74VT1G86 • Waveforms tr tf Input VIH 90% 90% V ref V ref 10% 10% t PLH GND t PHL VOH V ref In phase output V ref VOL t PHL t PLH VOH Out of phase output V ref V ref VOL Symbol VCC = 1.2V to 3.6V t r / tf 2.0 ns VIH VCC Vref 1/2 VCC Note: Input waveform : PRR ≤ 10 MHz, ZO = 50 Ω, duty cycle 50% Rev.1.00 Apr. 15, 2005 page 7 of 8 RD74VT1G86 Package Dimensions JEITA Package Code S-XFBGA6-0.9x1.4-0.50 RENESAS Code SXBG0006KB-A Previous Code TBS-6AV MASS[Typ.] 0.001g e ZD D ZE C E B e B A 1 Pin#1 index area 2 A 6 × φb y1 C φ× M C A B φ× M C Reference Symbol * Reference value. Rev.1.00 Apr. 15, 2005 page 8 of 8 Max 0.50 A1 0.155 0.185 (0.315) * A2 0.25 0.20 D 0.90 E 1.40 e 0.50 x 0.05 y 0.05 A A1 y C A2 Seating plane Nom A b C Dimension in Millimeters Min 0.20 y 1 Z D 0.20 Z E 0.20 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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