RT9005A/B DDR VDDQ and Termination Voltage Regulator General Description Features The RT9005A/B is a dual-output linear regulator for DDRSDRAM VDDQ supply and termination voltage VTT supply. z The Regulator is capable of actively sinking or sourcing up to 2A. The output termination voltage can be tightly regulated to track 1/2 VDDQ by two external voltage divider resistors. z z z z z Ordering Information RT9005 z Package Type SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) VOUT1 Output Voltage A : 2.5V B : 1.8V Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` z z z z Ideal for DDR-I and DDR-II VDDQ, VTT Applications Integrated Power MOSFETs Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces High Accuracy Output Voltage at Full-Load VOUT2 Sink and Source 2A Continuous Current VOUT2 Adjustment by Two External Resistors Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output Current Limiting Protection On-Chip Thermal Protection Available in SOP-8 (Exposed Pad) Packages RoHS Compliant and 100% Lead (Pb)-Free Applications z z z z z z Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I and DDR-II Memory Systems Suitable for use in SnPb or Pb-free soldering processes. Pin Configurations (TOP VIEW) BP VIN1 2 VIN2 3 VCNTL 4 8 VOUT1 7 GND GND 6 9 5 VOUT2 VREFEN SOP-8 (Exposed Pad) DS9005A/B-03 April 2011 www.richtek.com 1 RT9005A/B Typical Application Circuit VIN1 VIN2 CIN1 2.2uF CBP 10nF 1 BP 3 VIN2 VCNTL 4 R1 COUT1 2.2uF R2 CSS 1uF CVCNTL 47uF RT9005A/B 5 VREFEN 2N7002 VCTNL = 3.3V CIN2 470uF 8 VOUT1 VOUT1 EN 2 VIN1 RTT VOUT2 6 GND 7, Exposed Pad(9) COUT2 470uF GND Note : If there is any application need to use 10μF ceramic capacitor in front of RTT, please shut one 1000μF (Aluminum eletrolytic capacitor). Functional Pin Description Pin No. 1 Pin Name BP Pin Function Noise Reduction. Connecting a 10nF capacitor to GND to reduce output noise. Common Ground (The exposed pad must be soldered to a large PCB and 7, 9 (Exposed Pad) 2 GND VIN1 connected to GND for maximum power dissipation). The GND pad are a should be as large as possible and using many vias to conduct the heat into the buried GND plate of PCB layer. Linear Regulator Power Input Voltage. Input voltage which supplies current to the output pin. Connect this pin to a 3 VIN2 well-decoupled supply voltage. To prevent the input rail from dropping during large load transient, a large, low ESR capacitor is recommended to use. The capacitor should be placed as close as possible to the VIN2 pin. VCNTL supplies the internal control circuitry and provides the drive voltage. The 4 VCNTL driving capability of output current is proportioned to the VCNTL. Connect this pin to 3.3V bias supply to handle large output current with at least 10uF capacitor from this pin to GND. 5 VREFEN Reference voltage input and active low VOUT2 shutdown control pin. Two resistors dividing down the VIN voltage on the pin to create the regulated output voltage. Pulling the pin to ground turns off the device by an open-drain, such as 2N7002, signal N-MOSFET. Regulator Output. VOUT2 is regulated to REFEN voltage that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the 6 VOUT2 output rail. To maintain adequate large signal transient response, typical value of 1000μF AL electrolytic capacitor with 10μF ceramic capacitors are recommended to reduce the effects of current transients on VOUT. 8 www.richtek.com 2 VOUT1 Regulator 2.5V/1.8/1.5V Output. DS9005A/B-03 April 2011 RT9005A/B Function Block Diagram VIN1 BP 0.8V Reference Current Limit Sensor + Error Amplifier + VCNTL VOUT1 Thermal Shutdown VCNTL VIN2 Current Limit Thermal Protection GND + VOUT2 DS9005A/B-03 April 2011 VREFEN - www.richtek.com 3 RT9005A/B Absolute Maximum Ratings z z z z z z z (Note 1) Supply Input Voltage, VIN -----------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C SOP-8 (Exposed) ---------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOP-8 (Exposed), θJA ---------------------------------------------------------------------------------------------SOP-8 (Exposed), θJC ---------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10sec.) -------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z z z 6V 1.33W 75°C/W 28°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage, VIN1 ----------------------------------------------------------------------------------------Supply Input Voltage, VIN2 ----------------------------------------------------------------------------------------Control Voltage, VCNTL ---------------------------------------------------------------------------------------------Junction Temperature Range -------------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------------- 5V to 2.5V 3.6V to 1.5V 5V to 3.1V −40°C to 125°C −40°C to 85°C Electrical Characteristics (VIN1 =3.3V , VIN1 = VOUT + 1V, CIN1 = COUT1 = 2.2μF (Ceramic) & CBP = 10nF; VIN2 = 2.5V/1.8/1.5V, VCNTL = 3.3V, VREFEN = 1.25V/ 0.9/0.75V, CIN2 = 470μF, CVCNTL= 47μF, COUT2 = 1000μF(Electrolytic), TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- 1.5 3.0 mA -- 50 90 uA Input Operation Current Standby Current IVCNTL (Note 5) ISTBY2 IOUT = 0A VREFEN < 0.2V (Shutdown), RLOAD = 180Ω VOUT1 (VDDQ) VOUT1 Accuracy ΔV OUT IOUT = 10mA −2 -- +2 V VOUT1 Current Limit ILIM1 RLOAD = 0.5Ω, VIN1 = 3.3V 2 2.8 3 A VOUT1 Dropout Voltage (Note 6) VDROP IOUT = 0.5A -- 120 180 IOUT = 1.0A -- 240 360 Line Regulation ΔV LINE VIN1 = (V OUT1 + 0.5V) to 5.5V IOUT1 = 1mA -- -- 0.3 % -- 0.4 -- %/A −20 -- +20 mV Load Regulation (Note 7) ΔV LOAD VIN1 = (V OUT1 + 0.5V) 10mA < IOUT1 < 1A mV VOUT2 (VTT) Output Offset Voltage (Note 8) VOS IOUT = 0A To be continued www.richtek.com 4 DS9005A/B-03 April 2011 RT9005A/B Parameter Load Regulation (Note 7) VOUT2 Current Limit Symbol ΔVLOAD Test Conditions IOUT = +2A IOUT = −2A ILIM2 Min Typ Max Unit −20 -- +20 mV 2.2 -- -- A -- 170 -- °C -- 35 -- °C 0.6 -- -- -- -- 0.2 Protection Thermal Shutdown Temperature T SD Thermal Shutdown Hysteresis ΔTSD REFEN Shutdown Shutdown Threshold VIH Enable VIL Shutdown V Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers, 2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (Exposed Pad) package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. VOUT2 Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on REFEN pin (VIL < 0.2V). It is measured with VIN2 = VCNTL = 5V. Note 6. The dropout voltage is defined as VIN -VOUT, which is measured when VOUT is VOUT(NORMAL) − 100mV. Note 7. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. Note 8. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. DS9005A/B-03 April 2011 www.richtek.com 5 RT9005A/B Typical Operating Characteristics VIN2 Current vs. Temperature Output Voltage vs. Temperature 3.0 5 VIN1 = VIN2 = VCNTL = 3.3V 2.5 V IN2 Current (mA) Output Voltage (V) 4.5 VOUT1 = 2.5V 2.0 1.5 VOUT1 = 1.25V 4 VIN2 VIN2 = 1.8V, VCNTL = 3.3V VIN2 = 1.8V, VCNTL = 5V = 2.5V, VCNTL = 3.3V VIN2 = 2.5V, VCNTL = 5V 3.5 3 VIN2 = 1.5V, VCNTL = 5V 2.5 VIN2 = 1.5V, VCNTL = 3.3V 2 1.0 -50 -25 0 25 50 75 100 -50 125 -25 0 Temperature (°C) VIN2 VIN2 = 1.8V, VCNTL = 3.3V VIN2 = 1.8V, VCNTL = 5V VIN2 = 2.5V, VCNTL = 3.3V = 2.5V, VCNTL = 5V 0.55 0.45 VIN2 = 1.5V, VCNTL = 5V VIN2 = 1.5V, VCNTL = 3.3V 0.35 100 125 REFEN Threshold vs. Temperature 0.5 0.4 75 0.6 REFEN Threshold (V) V CNTL Current (mA) 0.55 50 Temperature (°C) VCNTL Current vs. Temperature 0.6 25 VCNTL = 5V, Turn On VCNTL = 5V, Turn Off 0.5 0.45 0.4 VCNTL = 3.3V, Turn On 0.35 VCNTL = 3.3V, Turn Off 0.3 0.25 0.3 -50 -25 0 25 50 75 100 -50 125 0 25 50 75 Temperature (°C) Temperature (°C) VOUT1 Short Circuit VOUT2 Short Circuit VOUT1 (1V/Div) VOUT2 (1V/Div) IOUT1 (1A/Div) IOUT2 (2A/Div) VIN1 = VIN2 = VCNTL = 3.3V Time (1ms/Div) www.richtek.com 6 -25 100 125 VIN1 = VIN2 = VCNTL = 3.3V Time (1ms/Div) DS9005A/B-03 April 2011 RT9005A/B VOUT1 @ 1A Load Transient Response Line Transient Response VIN1 4.3 (V) 3.3 IOUT1 (1A/Div) VOUT1 (100mV/Div) VOUT1 (50mV/Div) VOUT2 (100mV/Div) VOUT2 (50mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT1 = 50mA to 1A VIN2 = VCNTL = 3.3V, ILOAD = 1A Time (500μs/Div) Time (500μs/Div) VOUT1 @ 1.5A Load Transient Response VOUT2 @ 2A Load Transient Response Sink IOUT2 (2A/Div) IOUT1 (1A/Div) VOUT1 (20mV/Div) VOUT1 (100mV/Div) VOUT2 (100mV/Div) VOUT2 (20mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT1 = 50mA to 1.5A Time (500μs/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT2 = 50mA to 2A Time (500μs/Div) VOUT2 @ 2A Load Transient Response Source IOUT2 (2A/Div) VOUT1 (20mV/Div) VOUT2 (20mV/Div) VIN1 = VIN2 = VCNTL = 3.3V, IOUT2 = 50mA to 2A Time (500μs/Div) DS9005A/B-03 April 2011 www.richtek.com 7 RT9005A/B Application Information Thermal Consideration RGOLD-LINE RT9005A/B regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. For continued operation, do not exceed maximum operation junction temperature 125°C. The power dissipation definition in device is : RLEAD FRAME RPCB path 1 Junction RDIE RDIE-ATTACH RDIE-PAD path 2 RPCB Case (Exposed Pad) Ambient PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) -TA ) /θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. The junction to ambient thermal resistance (θJA is layout dependent) for SOP-8 package (Exposed Pad) is 75°C/ W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W Figure 2 show the package sectional drawing of SOP-8 (Exposed Pad). Every package has several thermal dissipation paths. As show in Figure 2, the thermal resistance equivalent circuit of SOP-8 (Exposed Pad). The path 2 is the main path due to these materials thermal conductivity. We define the exposed pad is the case point of the path 2. Ambient Molding Compound Gold Line RMOLDING-COMPOUND path 3 Figure 2. Thermal Resistance Equivalent Circuit The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of SOP-8 package. About PCB layout, the Figure 3 show the relation between thermal resistance θJA and copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA = 25°C.We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. We use the “dog-bone” copper patterns on the top layer as Figure 4. As shown in Figure 5, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad of 2 oz. copper (Figure 5.a), θJA is 75°C/W. Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 5.b) reduces the θJA to 64°C/W. Even further, increasing the copper area of pad to 70mm2 (Figure 5.e) reduces the θJA to 49°C/W. Lead Frame Die Pad Case (Exposed Pad) Figure 1. SOP-8 (Exposed Pad) Package Sectional Drawing www.richtek.com 8 DS9005A/B-03 April 2011 RT9005A/B θJA vs. Copper Area 100 90 θ JA (°C/W) 80 70 Figure 5 (c). Copper Area = 30mm2, θJA = 54°C/W 60 50 40 30 0 10 20 30 40 50 60 70 2 Copper Area (mm ) Figure 3 Figure 5 (d). Copper Area = 50mm2, θJA = 51°C/W Exposed Pad W≦2.28mm Figure 5 (e). Copper Area = 70mm2, θJA = 49°C/W Figure 4. Dog-Bone layout Figure 5. Thermal Resistance vs. Different Cooper Area Layout Design Figure 5 (a). Minimum Footprint, θJA = 75°C/W Figure 5 (b). Copper Area = 10mm2, θJA = 64°C/W DS9005A/B-03 April 2011 www.richtek.com 9 RT9005A/B Outline Dimension H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 10 DS9005A/B-03 April 2011