Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
SPECIFICATIONS FOR
LCD MODULE
CUSTOMER
CUSTOMER PART NO.
AM-480234G1TMQW-B0
AMPIRE PART NO.
APPROVED
BY
DATE
Approved For Specifications
Approved For Specifications & Sample
AMPIRE CO., LTD.
Building D., 2F., No.88, Sec. 1, Sintai 5th Rd., Sijhih City,
Taipei County 221, Taiwan (R.O.C.)
台北縣汐止市新台五路一段 88 號 2 樓(東方科學園區 D 棟)
TEL:886-2-26967269 , FAX:886-2-286967196 or 26967270
APPROVED BY
Date : 2008/09/18
CHECKED BY
AMPIRE CO., LTD.
ORGANIZED BY
1
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
RECORD
Revision Date Page
2008/07/29
2008/08/14
2008/09/18
-
OF
REVISION
Contents
Editor
New Release
Emil
38,39 Modify Mechanical Drawing (The direction of Connector.)
- Rename the official part No. to AM-480234G1TMQW-B0.
Date : 2008/09/18
AMPIRE CO., LTD.
Emil
Emil
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
1 Features
7.0 inch Amorphous-TFT-LCD (Thin Film Transistor Liquid Crystal Display)
module. This module is composed of a 7.0” TFT-LCD panel, LCD controller,
power driver circuit and backlight unit.
1.1 TFT Panel Feature :
(1) Construction: 7.0” a-Si color TFT-LCD, White LED Backlight and PCB.
(2) Resolution (pixel): 480(R.G.B) X234
(3) Number of the Colors: 65K and 262K colors selectable.
(4) LCD type : Transmissive Color TFT LCD (normally White)
(5) Interface: 40 pin pitch 0.5 FFC
(6) Power Supply Voltage: 5.0V single power input. Built-in power supply
circuit.
(7) Viewing Direction: 6 O’clock ( The direction it’s hard to be discolored ):
1.2 LCD Controller Feature:
(1) MCU interface 8/9/16/18 bit 80&68 series MCU interface selectable by
hardware (Jumper).
(2) Display RAM size: 640x240x3x6 bits. Ex: 320x240 two frame buffer
with 262K colors.
(3) Arbitrary display memory start position selection.
(4) MCU interface: 8 bit 80 MPU interface.
(5) 8 bit / 16 bit interface support 65K (R5G6B5) /262K (R6G6B6) colors
data format.
(6) 9 bit / 18 bit interface support 262K (R6G6B6) colors data format only.
2 Physical specifications
Item
Display resolution(dot)
Active area
Screen size
Dot pitch
Color configuration
Overall dimension
Weight
Backlight unit
Date : 2008/09/18
Specifications
1440 (W) x 234(H)
154.08 (W) x 86.58 (H)
7.0(Diagonal)
0.107 (W) x 0.370 (H)
R.G.B stripe
164.9(W)x100.0(H)x9.2(D)
193.10
LED
AMPIRE CO., LTD.
Unit
dot
mm
mm
mm
mm
g
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
3 Default Setting & Option
z Interface :
The user can select the MCU interface by change the Jumper & Resister Array.
Setting
JP1
RA1
RA2
RA3
RA4
Remark
Interface Type
1,2 short
2K
80-18Bit interface
OPEN OPEN OPEN
2,3 open
ohm
1,2 short
2K
80-16Bit interface
OPEN
OPEN OPEN
2,3 open
ohm
1,2 short
2K
80-9Bit interface
OPEN OPEN
OPEN
2,3 open
ohm
1,2 short
2K
Default
80-8Bit interface
OPEN OPEN OPEN
2,3 open
ohm
1,2 open
2K
68-18Bit interface
OPEN OPEN OPEN
2,3 short
ohm
1,2 open
2K
68-16Bit interface
OPEN
OPEN OPEN
2,3 short
ohm
1,2 open
2K
68-9Bit interface
OPEN OPEN
OPEN
2,3 short
ohm
1,2 open
2K
68-8Bit interface
OPEN OPEN OPEN
2,3 short
ohm
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
4 Electrical specification
4.1 Absolute max. ratings
4.1.1 Electrical Absolute max. ratings
Item
Symbol Condition
Power voltage
VDD
Input voltage
V in
B
VSS=0
B
Min.
Max.
Unit
-0.3
5.5
V
-0.3
VDD+0.3
V
Remark
Note 1
Note1: /CS,/WR,/RD,RS,DB0~DB7
4.1.2 Environmental Absolute max. ratings
OPERATING
STORAGE
Item
MIN
MAX
MIN
MAX
Temperature
0
60
-20
70
Humidity
Note1
Note1
Corrosive Gas
Not Acceptable
Not Acceptable
Remark
Note2,3,4,5,6,7
Note1: Ta <= 40℃ : 85% RH max
Ta > 40℃ : Absolute humidity must be lower than the humidity of
85%RH at 40℃
Note2: For storage condition Ta at -20℃ < 48h, at 70℃ < 100h
For operating condition Ta at 0℃ < 100h
Note3: Background color changes slightly depending on ambient
temperature. This phenomenon is reversible.
Note4: The response time will be slower at low temperature.
Note5: Only operation is guarantied at operating temperature. Contrast,
response time, another display quality are evaluated at +25℃
Note6:
z LED BL: When LCM is operated over 40℃ ambient temperature, the
I LED of the LED back-light should be follow :
B
Allowable Forward Current IF (mA)
B
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
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Note7: This is panel surface temperature, not ambient temperature.
Note8:
z LED BL: When LCM is operated over than 40℃, the life time of the
LED back-light will be reduced.
4.2 Electrical characteristics
4.2.1 DC Electrical characteristic of the LCD
Typical operating conditions (VSS=0V)
Symbol
Min.
Typ.
Item
Power supply
Input Voltage
for logic
Output Voltage for
Logic
H Level
Max.
Unit
VDD
4.5
5.0
5.2
V
V IH
2.0
-
5.5
V
B
B
Remark
Note 1
L Level
V IL
H Level
V OH
B
B
B
B
VSS
-
0.8
V
2.4
-
VDD
V
Note 2
L Level
Power Supply current
V OL
VSS
IDD
-
B
B
(800)
0.4
V
-
mA
Note 3
Note1: With 5V Tolerance Input, /CS, /WR,/RD,RS,DB0~DB17
Note2: DB0~DB17
Note3: fV =60Hz, Ta=25℃, VDD=5.0V, DCLK=10MHz, PLL frequency=40MHz,
Display pattern: All Black
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
4.3
Electrical characteristic of LED Back-light
Parameter
Symbol
LED Forward Voltage
VF
9.6
V
LED Forward current
ILED
140
mA
Min.
Typ.
Max.
Unit
Remark
The constant current source is needed for white LED back-light driving.
When LCM is operated over 40℃ ambient temperature, the I LED of the LED
B
B
Allowable Forward Current IF (mA)
back-light should be adjusted to 90mA max
150
120
90
60
30
-20 -10
0
10
20
30
40
50
60
70
Ambient Temperature Ta (℃)
Date : 2008/09/18
AMPIRE CO., LTD.
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4.4 AC Timing characteristic of the Graphic TFT LCD controller
4.4.1 80 series Timing
Symbol
tcycle
PWHW
PWLW
tAS
tAH
tDSW
tHWR
tcsb-s
tcsb-h
Parameter
Enable cycle time
Enable high-level pulse width
Enable low-level pulse width
RS setup time
RS hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
Date : 2008/09/18
Min
100
66
33
16
16
50
50
16
16
Typ
200
70
130
25
45
50
40
20
30
AMPIRE CO., LTD.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remark
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third part without the prior written consent of AMPIRE CO., LTD
4.4.2 68eries Timing
Symbol
tcycle
PWEH
PWEL
tASE
tAHE
tDSWE
tHE
tcsb-s
tcsbh
Parameter
Enable cycle time
Enable high-level pulse width
Enable low level pulse width
RS setup time
RS hold time
Write data setup time
Write data hold time
CSB setup time
CSB hold time
Date : 2008/09/18
Min
100
66
33
16
16
50
50
16
16
Typ
200
70
130
25
45
50
40
20
30
AMPIRE CO., LTD.
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remark
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
5 Optical specification
5.1 Optical characteristic:
Item
Response
time
Symbol
Rise
Fall
Contrast ratio
Top
Bottom
Left
Right
Brightness
( 9 point average )
Condition
Min.
Typ.
Tr
Tf
Θ=0°
-
15
35
CR
At optimized
viewing angle
150
250
-
35
55
70
70
-
deg.
Note 5,6
cd/m2
Note 7
Viewing
angle
Uniformity (with LCM)
White chromaticity
Red chromaticity
Green chromaticity
Blue chromaticity
CR≧10
Max.
Unit
Remark
ms
ms
Note 3,5
Note 4,5
YL
IL=140mA,
25℃
200
250
-
-
IL=140mA
80%
-
-
Note 8
Θ=0°
Θ=0°
-
0.34
0.35
0.58
0.36
0.34
0.35
0.14
0.09
-
Note 7
X
Y
X
Y
X
Y
X
Y
( )For reference only. These data should be update according the prototype.
Note 1:
LED BL: Ambient temperature=25℃, and lamp current I LED =140mA.To be
measured in the dark room.
Note 2: To be measured on the center area of panel with a viewing cone of 1°by
Topcon luminance meter BM-7, after 10 minutes operation.
z
B
B
Note 3.Definition of response time:
The output signals of photo detector are measured when the input signals
are changed from “black“to “white”(falling time) and from” white” to “black”
(rising time), respectively. The response time is defined as the time
interval
between the 10% and 90% of amplitudes. Refer to figure as below.
Date : 2008/09/18
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Note 4.Definition of contrast ratio:
Contrast ratio is calculated with the following formula.
Contrast ratio (CR) =
Photo detector output when LCD is at ”White” state
Photo detector Output when LCD is at “Black” state
Note 5: White V i =V i50 +1.5V
B
B
B
B
Black V i =V i50 +2.0V
“±”means that the analog input signal swings in phase with V COM signal.
“ “ means that the analog input signal swings out of phase with V COM
signal.
B
B
B
B
B
B
B
B
V i50 : The analog input voltage when transmission is 50%.The 100%
Transmission is defined as the transmission of LCD panel when all the
Input terminals of module are electrically opened.
B
B
Note 6.Definition of viewing angle, Refer to figure as below.
Date : 2008/09/18
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Note 7.Measured at the center area of the panel when all the input terminals of
LCD panel are electrically opened.
Ring light
Brightness gauge
BM-7 (Topcon)
LCD module
Metal halide lamp
Glass fiber
LIGHT:OFF, LIGHT:ON
LCD
Optical Detector
Brightness gauge
BM-7 (Topcon)
LED / CCFL
Date : 2008/09/18
LIGHT:ON, LIGHT:OFF
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5.2 Optical characteristic of the LED Back-light
ITEM
MIN
TYP
MAX
UNIT
Condition
Bare Brightness
3000
--Cd/m2
I LED =140mA,
AVG. X of 1931 C.I.E.
0.26
0.28
0.32
-V LED =10.5V,
AVG. X of 1931 C.I.E.
0.27
0.29
0.33
-Ta=25℃
Brightness Uniformity
80
--%
( ) For reference only. These data should be update according the prototype.
B
B
B
B
Note1: Measurement after 10 minutes from LED BL operating.
Note2: Measurement of the following 9 places on the display.
Note3: The Uniformity definition
(Min Brightness / Max Brightness) x 100%
Date : 2008/09/18
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6 Interface specifications
6.1 Driving signals for the TFT panel
6.1.1 24pin FFC connector
Pin no
Symbol
I/O
Description
Remark
1
DGND
- GND
2
3
NC
- No Connection.
4
NC
- No Connection.
5
/RESET
I Reset signal for TFT LCD controller.
6
RS
I Register and Data select for TFT LCD controller.
7
/CS506
I Chip select low active signal for TFT LCD controller.
80mode: /WR low active signal for TFT LCD controller.
8
/WR
I
68mode: E signal latch on rising edge.
80mode: /RD low active signal for TFT LCD controller.
9
/RD
I
68mode: R/W signal Hi: read, Lo: write.
10
DB0
I
11
DB1
I
12
DB2
I
13
DB3
I
14
DB4
I
15
DB5
I
16
DB6
I
Data bus.
17
DB7
I
8bit[7:0]=[DB7:DB0]
18
DB8
I
9bit[8:0]=[DB8:DB0]
19
DB9
I
16bit[15:0]=[DB15:DB0]
20
DB10
I 18bit[17:0]=[DB17:DB0]
21
DB11
I
22
DB12
I
23
DB13
I
24
DB14
I
25
DB15
I
26
DB16
I
27
DB17
I
28
262K/65K
I Hi=262 K Color Mode; Lo: 65 K Color Mode.
29
DGND
- GND
30
NC
- No Connection.
31
NC
- No Connection.
32
NC
- No Connection.
33
NC
- No Connection.
34
NC
- No Connection.
35-37
VDD
- Power supply for the logic (5.0V).
38-40
DGND
- GND.
Date : 2008/09/18
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7 BLOCK DIAGRAM
Line 1
480 xRGBx234
Line 234
S1440
S1
Source Driver+ Tcon
Gate driver
TFT Panel
VCOM
circuit
Output control
SRAM
640x240x6x6 bits
Power circuit
SRAM control
A
K
OSC
TFT LCD controller
VDD
VSS
/WR (E)
/RD(R/W)
/CS
RS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
Input control
PLL
LED/CCFL
Back-light
VS
HS
DE
DC
LK
R6
G6
B6
PCB circuit
Date : 2008/09/18
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8 Interface Protocol
8.1 8Bit-80/68- Write to Command Register
8.2 8Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[7:0]
Note1
Display
RAM
Write Enable
0x000C1
Note2
Send
Data1
Note3
Send
Data2
Note4
Note5
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[7:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[7:0] represent the writing Data1 to Display RAM
Note3: DB[7:0] represent the writing Data2 to Display RAM
Note4: DB[7:0] represent the writing DataN to Display RAM
Note5: DB[7:0] send 0x00080 to Disable the Display RAM write.
Date : 2008/09/18
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8.3 Data transfer order Setting
8.3.1 8 bit interface 65K color (JP2 1,2 short 65K/262K =Low)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 st data
X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3
2 nd data
X X X X X X X X G2 G1 G0 B4 B3 B2 B1 B0
P
P
P
P
8.3.2 8 bit interface 262K color (JP2 2,3 short 65K/262K =High)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1 st data
X X X X X X X X
2 nd data
X X X X X X X X R3 R2 R1 R0 G5 G4
rd
3 data
X X X X X X X X G1 G0 B5 B4 B3 B2
P
P
P
P
P
P
Date : 2008/09/18
AMPIRE CO., LTD.
1
0
R5
G3
B1
R4
G2
B0
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9 Register Depiction
Register
Address
(Hex)
00
Description
Register
Address
(Hex)
01
Description
Register
Address
(Hex)
02
Description
Register
Address
(Hex)
03
Description
Register
Address
(Hex)
04
Description
Register
Address
(Hex)
05
Description
Register
Address
(Hex)
06
Description
Register
Address
(Hex)
07
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis end position
01
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis end position
3F
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis start position
00
set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis start position
00
Set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis end position
00
set the vertical end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis end position
EF
Set the vertical end position of display active region
Date : 2008/09/18
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To simplify the address control of display RAM access, the window area address
function
allows for writing data only within a window area of display RAM specified by
registers REG[00]~REG[07] .
After writing data to the display RAM, the Address counter will be increased within
setting window address-range which is specified by
MIN X address (REG[0] & REG[1])
MAX X address (REG[2] & REG[3])
MIN Y address (REG[4] & REG[5])
MAX Y address (REG[6] & REG[7])
Therefore, data can be written consecutively without thinking the data address.
Date : 2008/09/18
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Register
Address
(Hex)
08
Default
DB7 DB6 DB5 DB4
(Hex)
01
X
X
X
X
DB3
DB2
X
X
DB1
DB0
Remark
_PanelXSize
H_Byte[1:0]
Description Set the panel X size
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1
(Hex)
(Hex)
09
40
_PanelXSize L_Byte[7:0]
Description Set the panel X size
DB0
Remark
The register REG[08] and REG[09] is use to calculate the RAM address. If you
want to use the TFT as Landscape mode (320x240), the REG[08] & RGE[09 must
set to 320. If you want to use the TFT as Portrait mode (240x320), the REG[08] &
RGE[09] must set to 240.
Register
Address
(Hex)
Default
(Hex)
0A
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
[17:16] bits of
memory write start
address
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
0B
00
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[7:0] bits of memory write start address
0C
00
Description Memory write start address
Register
Address
(Hex)
0x10
Default
(Hex)
DB7
DB6
DB5 DB4
Remark
DB3
DB2
Remark
Remark
DB1 DB0 Remark
BUS_SEL
Blanking P/S_SEL
CLK_SEL
0x0D Bit_SWAP OUT_TEST
"0x10_Clk_sel[1:0]" : The TFT controller built-in 40Mhz PLL clock. These bits
Description are for select the TFT panel dot clock frequency.
00 : 20Mhz 01: 10Mhz 02: 5 Mhz
Date : 2008/09/18
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"0x10_ps_sel[2]" : The TFT controller support parallel and serial RGB
interface. These bits are for select the output timing.
0 : serial Panel 1: Parallel panel
"0x10_blanking_tmp[3]"
0 : OFF (blanking) 1: ON ( normal operation)
"0x10_bus_sel[5:4]" : It only for serial Panel
00=R , 01=G , 10=B
"0x10_out_test[6]" : Self test
0 : normal operation 1: for test (don’t use for normal operation)
When set the bit to “1” , the Rout=(Reg 2a[6:0]) Gout=(Reg 2b[6:0])
Bout=(Reg 2c[6:0])
"0x10_bit_swap[7]" : 0-normal
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
0x11
Description
Register
Address
(Hex)
0x12
Default
(Hex)
DB7
DB6
DB5 DB4
DB3
DB2
DB1 DB0 Remark
X
X
EVEN
_ODD
00
" Even line of serial panel data out sequence or data bus order of parallel
panel
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Odd line of serial panel data out sequence
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Must Set to 0x05 for AM320240N1
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_stH_Byte[3:0]
For TFT output timing adjust:
Description Hsync start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x13
00
Hsync_stL_Byte[7:0]
Description For TFT output timing adjust:
Date : 2008/09/18
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
Hsync start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
0x14
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description Hsync pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x15
10
Hsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description Hsync pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x16
00
Hact_stH_Byte[3:0]
For TFT output timing adjust:
Description DE pulse start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x17
38
Hact_stL_Byte[7:0]
For TFT output timing adjust:
Description DE pulse start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x18
01
Hact_pwH_Byte[3:0]
For TFT output timing adjust:
Description DE pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x19
40
Hact_pwL_Byte[7:0]
For TFT output timing adjust:
Description DE pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
Default
(Hex)
Date : 2008/09/18
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AMPIRE CO., LTD.
Remark
22
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
(Hex)
0x1A
01
HtotalH_Byte[3:0]
For TFT output timing adjust:
Description Hsync total clocks H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1B
B8
HtotalL_Byte[7:0]
For TFT output timing adjust:
Description Hsync total clocks H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
0x1C
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vsync_stH_Byte[3:0]
For TFT output timing adjust:
Description Vsync start position H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1D
00
Vsync_stL_Byte[7:0]
For TFT output timing adjust:
Description Vsync start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1E
00
Vsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description Vsync pulse width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x1F
08
Vsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description Vsync pulse width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x20
00
Vact_stH_Byte[3:0]
For TFT output timing adjust:
Description
Vertical DE pulse start position H-Byte
Date : 2008/09/18
AMPIRE CO., LTD.
23
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
0x21
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
12
Vact_stL_Byte[7:0]
For TFT output timing adjust:
Description Vertical DE pulse start position L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x22
00
Vact_pwH_Byte[3:0]
For TFT output timing adjust:
Description Vertical Active width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x23
F0
Vact_pwL_Byte[7:0]
For TFT output timing adjust:
Description Vertical Active width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x24
01
VtotalH_Byte[3:0]
For TFT output timing adjust:
Description Vertical total width H-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x25
09
VtotalL_Byte[7:0]
For TFT output timing adjust:
Description Vertical total width L-Byte
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Address
(Hex)
26
Default
(Hex)
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
[17:16] bits of
memory read start
address
Description Memory read start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
27
00
Description Memory read start address
Date : 2008/09/18
AMPIRE CO., LTD.
Remark
Remark
24
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1
(Hex)
(Hex)
[7:0] bits of memory write start address
28
00
Description Memory read start address
Register
Address
(Hex)
29
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
DB0
Remark
DB0
Remark
[7:1] Reversed
00
[0] Load output timing related setting (H sync., V sync. and DE) to take
Description
effect
Register
Address
(Hex)
0x2A
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00
X
TestPatternRout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Rout data equal to TestPatternRout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x2B
00
X
TestPatternGout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Gout data equal to TestPatternGout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x2C
00
X
TestPatternBout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Bout data equal to TestPatternBout[6:0]
Remark
Remark
Remark
If you set the " REG[0x10]_out_test[6]" : Self test =1 , the TFT controller will skip
the connect of the display RAM. The Output port will send the
REG[2A] ,REG[2B],REG[2C] data.
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
Register
Address
(Hex)
Default
DB7 DB6 DB5 DB4 DB3
(Hex)
DB2
DB1 DB0 Remark
Rising/falling
_rotate
edge[2]
[1:0]
[3] Output pin X_DCON level control ; TFT Power ON/OFF control
0: TFT POWER circuit OFF
1: TFT POWER circuit ON
Rising/falling edge[2] :
0: The RGB out put data are on the Rising edge of the DCLK.
Description 1: The RGB out put data are on the Falling edge of the DCLK.
_rotate [1:0]:
00 : rotate 0 degree
01 : rotate90 degree
10 : rotate 270 degree
11 : rotate 180 degree
0x2D
00
Register
Address
(Hex)
Default
(Hex)
30
00
X
X
X
X
DB7 DB6 DB5 DB4
X
X
X
X
[3]
DB3
DB2 DB1 DB0
X
_H byte
H-Offset[3:0]
Description Set the Horizontal offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
31
00
_L byte H-Offset[7:0]
Description Set the Horizontal offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
_H byte
32
00
X
X
X
X
X
V-Offset[3:0]
Description Set the Vertical offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
33
00
_L byte V-Offset[7:0]
Description Set the Vertical offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
_H byte
[7:4] Reserved
34
00
H-def[3:0]
Description [3:0] MSB of image horizontal physical resolution in memory
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
Date : 2008/09/18
AMPIRE CO., LTD.
Remark
Remark
Remark
Remark
Remark
Remark
26
Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
35
40
_L byte H-def[7:0]
Description [7:0] LSB of image horizontal physical resolution in memory
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
_H byte
[7:4] Reserved
36
01
V-def[3:0]
Description [3:0] MSB of image vertical physical resolution in memory
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
37
E0
_L byte V-def[7:0]
Description [7:0] LSB of image vertical physical resolution in memory
Remark
Remark
The total RAM size is 640x240x18bit. The user can arrange the Horizontal ram
size by REG[34],REG[35] and the Vertical ram size by REG[36],REG[37].
EX: 320x480x18bit REG[34]=0x01 , REG[35]=0x40 , REG[36]=0x01 ,
REG[37]=0xE0
EX: 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
The TFT LCD controller default value is for AM320240N1 already. So we can start
to write our data in a few steps:
Target: To write a 640x240 data to Display RAM and scroll the display data by
change the Horizontal offset register.
9.1 Step 1: Make sure the interface Protocol.
9.2 Step 2: Define the Horizontal ram seize = 640 and Vertical ram size =240
640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
9.3 Step 3: Define the Panel X Size = 320
REG[8]=0x01 , REG[9]=0x40
9.4 Step4: Define the Write window. Start=(0,0) End=(619,239)
REG[0]=0x00 , REG[1]=0x00 , REG[2]=0x02 , REG[3]=0x6B , // Start X , End
X
REG[4]=0x00 , REG[5]=0x00 , REG[6]=0x00 , REG[7]=0xEF , // Star Y ,End Y
Date : 2008/09/18
AMPIRE CO., LTD.
27
Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
9.5 Step5: Write the 640x240x18 bit data consecutively
9.6 Step6: The display will show the following image.
Date : 2008/09/18
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28
Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
9.7 Step7: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 160 , REG[30]=00 REG[31]=A0 . You will see
9.8 Step8: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 320 , REG[30]=01 REG[31]=40 . You will see
Date : 2008/09/18
AMPIRE CO., LTD.
29
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
DISPLAYED COLOR AND INPUT DATA
Color &
Gray
Scale
Basic
Color
Red
Green
Blue
Black
Red(0)
Green(0)
Blue(0)
Cyan
Magenta
Yellow
White
Black
Red(62)
Red(61)
:
Red(31)
:
Red(1)
Red(0)
Black
Green(62)
Green(61)
:
Green(31)
:
Green(1)
Green(0)
Black
Blue(62)
Blue(61)
:
Blue(31)
:
Blue(1)
Blue(0)
DATA SIGNAL
R5
0
1
0
0
0
1
1
1
0
0
0
:
0
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R4
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
Date : 2008/09/18
R3
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R2
0
1
0
0
0
1
1
1
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R1
0
1
0
0
0
1
1
1
0
0
1
:
1
:
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
R0
0
1
0
0
0
1
1
1
0
1
0
:
1
:
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
G5
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
1
1
0
0
0
:
0
:
0
0
G4
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
G3
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
G2
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
0
0
0
:
0
:
0
0
AMPIRE CO., LTD.
G1
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
0
1
:
1
:
1
1
0
0
0
:
0
:
0
0
G0
0
0
1
0
1
0
1
1
0
0
0
:
0
:
0
0
0
1
0
:
0
:
0
1
0
0
0
:
0
:
0
0
B5
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
0
:
1
1
B4
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B3
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B2
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
0
:
1
:
1
1
B1
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
0
1
:
1
:
1
1
30
B0
0
0
0
1
1
1
0
1
0
0
0
:
0
:
0
0
0
0
0
:
0
:
0
0
0
1
0
:
1
:
0
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
10 QUALITY AND RELIABILITY
10.1 TEST CONDITIONS
Tests should be conducted under the following conditions :
Ambient temperature :
Humidity
:
25 ± 5°C
60 ± 25% RH.
10.2 SAMPLING PLAN
Sampling method shall be in accordance with MIL-STD-105E , level II,
normal single sampling plan .
10.3 ACCEPTABLE QUALITY LEVEL
A major defect is defined as one that could cause failure to or materially
reduce the usability of the unit for its intended purpose. A minor defect is one that
does not materially reduce the usability of the unit for its intended purpose or is an
infringement from established standards and has no significant bearing on its
effective use or operation.
10.4 APPEARANCE
An appearance test should be conducted by human sight at
approximately 30 cm distance from the LCD module under flourescent light. The
inspection area of LCD panel shall be within the range of following limits.
Date : 2008/09/18
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
10.5 INSPECTION QUALITY CRITERIA
No.
Item
1
Non display
2
Irregular
operation
Criterion for defects
Defect type
No non display is allowed
Major
No irregular operation is allowed
Major
3
Short
No short are allowed
Major
4
Open
Any segments or common patterns that don’t activate
are rejectable.
Major
5
6
7
8
Black/White
spot (I)
Black/White
line (I)
Black/White
sport (II)
Black/White
line (II)
9
Back Light
10
Display pattern
Size D (mm)
D < 0.15
0.15 < D < 0.20
0.20 < D < 0.30
0.30 < D
U
U
U
U
U
U
Length(mm)
10 < L
5.0 < L < 10
1.0 < L < 5.0
L < 1.0
U
U
U
U
U
U
Acceptable number
Ignore
3
2
0
0.03 < W
0.04 < W
0.06 < W
0.07 < W
<
<
<
<
U
U
U
U
U
U
U
U
Size D (mm)
D < 0.30
0.30 < D < 0.50
0.50 < D < 1.20
1.20 < D
U
U
U
U
Length (mm)
20 < L
10 < L < 20
5.0 < L < 10
L < 5.0
U
U
U
U
U
U
Acceptable number
Ignore
5
3
0
U
U
Acceptable number
5
3
2
1
0.04
0.06
0.07
0.09
Width (mm)
0.05 < W < 0.07
0.07 < W < 0.09
0.09 < W < 0.10
0.10 < W < 0.15
U
U
U
U
U
U
U
U
Acceptable number
5
3
2
1
1. No Lighting is rejectable
2. Flickering and abnormal lighting are rejectable
Unit:mm
A+B
≤ 0.30 0 < C
2
Minor
Minor
Minor
Minor
Major
Minor
D+E
F+G
≤ 0.25
≤ 0.25
2
2
Note: 1. Acceptable up to 3 damages
2. NG if there’re to two or more pinholes per dot
Date : 2008/09/18
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
Blemish &
Foreign matters
11
Size D (mm)
D < 0.15
0.15 < D < 0.20
0.20 < D < 0.30
0.30 < D
U
Size:
A+ B
D=
2
Scratch on
Polarizer
12
U
U
U
U
U
Width (mm)
W < 0.0
U
U
3
0.03<W < 0.05
U
U
0.05<W < 0.08
U
Acceptable number
Ignore
3
2
0
U
Length (mm)
Ignore
L < 2.0
L > 2.0
L > 1.0
L < 1.0
Note (1)
U
U
U
U
Acceptable number
Ignore
Ignore
1
1
Ignore
Note(1)
Minor
Minor
0.08<W
Note(1) Regard as a blemish
Bubble in
13 polarizer
Size D (mm)
D < 0.20
0.20 < D < 0.50
0.50 < D < 0.80
0.80 < D
Stains on
U
U
U
U
U
U
Acceptable number
Ignore
3
2
0
Minor
14 LCD panel
Stains that cannot be removed even when wiped lightly
with a soft cloth or similar cleaning too are rejectable.
Minor
15
Rust which is visible in the bezel is rejectable.
Minor
Defect of
land surface
16 contact (poor
soldering)
Evident crevices which is visible are rejectable.
Minor
Parts
17 mounting
1. Failure to mount parts
2. Parts not in the specifications are mounted
3. Polarity, for example, is reversed
Parts
18 alignment
1. LSI, IC lead width is more than 50% beyond pad
outline.
2. Chip component is off center and more than 50% of
the leads is off the pad outline.
Major
Major
Major
Minor
surface
Rust in Bezel
Conductive
foreign matter
19 (Solder ball,
Solder chips)
Faulty PCB
20 correction
Date : 2008/09/18
1. 0.45<φ
,N≧1
2. 0.30<φ < 0.45 ,N≧1
φ:Average diameter of solder ball (unit: mm)
3. 0.50<L
,N≧1
L: Average length of solder chip (unit: mm)
1. Due to PCB copper foil pattern burnout, the pattern is
connected, using a jumper wire for repair; 2 or more
places are corrected per PCB.
2. Short circuited part is cut, and no resist coating has
been performed.
U
U
AMPIRE CO., LTD.
Minor
Major
Minor
Minor
Minor
Minor
33
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
The TFT panel may have bright dot or Dark dot.
The acceptable number defection:
21
Defect Dot
Bright
dot
2
Dark dot Total dot
3
4
Distance
between
Dark-- dark
L≧5 mm
Minor
11 Reliability test items (Note2):
No.
1
2
3
4
Test items
6
High temperature storage
Low temperature storage
High temperature operation
Low temperature operation
High temperature and high
humidity
Heat shock
7
Electrostatic discharge
8
Vibration
9
Vibration (With carton)
5
10
Drop (with carton)
Date : 2008/09/18
Conditions
Ta=70℃
Ta=-30℃
Ta=60℃
Ta=-20℃
Ta=40℃,85% RH
240Hrs
240Hrs
240Hrs
240Hrs
240Hrs
-30℃~70℃/200 cycles 1Hrs/cycle
±200V,200Pf(0Ω),once for each
terminal
Frequency range
:8~33.3Hz
Stoke
:1.3mm
Sweep
:2.9G,33.3~400Hz
Cycle
:15 minutes
2 hours for each direction of X,Z
4 hours for Y direction
Random vibration:
0.015G 2 /Hz from 5~200Hz
-6dB/octave from 200~500Hz
Height:60cm
1 corner,3 edges,6 surfaces
P
P
AMPIRE CO., LTD.
Remark
Operation
Non-operation
Non-operation
JIS C7021,
A-10
Condition A
IEC 68~34
JIS Z0202
34
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
12 USE PRECAUTIONS
12.1 Handling precautions
1) The polarizing plate may break easily so be careful when handling it. Do not
touch, press or rub it with a hard-material tool like tweezers.
2) Do not touch the polarizing plate surface with bare hands so as not to make it
dirty. If the surface or other related part of the polarizing plate is dirty, soak a
soft cotton cloth or chamois leather in benzine and wipe off with it. Do not use
chemical liquids such as acetone, toluene and isopropyl alcohol. Failure to do
so may bring chemical reaction phenomena and deteriorations.
3) Remove any spit or water immediately. If it is left for hours, the suffered part
may deform or decolorize.
4) If the LCD element breaks and any LC stuff leaks, do not suck or lick it. Also if
LC stuff is stuck on your skin or clothing, wash thoroughly with soap and water
immediately.
12.2 Installing precautions
1) The PCB has many ICs that may be damaged easily by static electricity. To
prevent breaking by static electricity from the human body and clothing, earth
the human body properly using the high resistance and discharge static
electricity during the operation. In this case, however, the resistance value
should be approx. 1MΩ and the resistance should be placed near the human
body rather than the ground surface. When the indoor space is dry, static
electricity may occur easily so be careful. We recommend the indoor space
should be kept with humidity of 60% or more. When a soldering iron or other
similar tool is used for assembly, be sure to earth it.
2) When installing the module and ICs, do not bend or twist them. Failure to do
so may crack LC element and cause circuit failure.
3) To protect LC element, especially polarizing plate, use a transparent protective
plate (e.g., acrylic plate, glass etc) for the product case.
4) Do not use an adhesive like a both-side adhesive tape to make LCD surface
(polarizing plate) and product case stick together. Failure to do so may cause
the polarizing plate to peel off.
Date : 2008/09/18
AMPIRE CO., LTD.
35
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
12.3 Storage precautions
1) Avoid a high temperature and humidity area. Keep the temperature between
0°C and 35°C and also the humidity under 60%.
2) Choose the dark spaces where the product is not exposed to direct sunlight or
fluorescent light.
3) Store the products as they are put in the boxes provided from us or in the
same conditions as we recommend.
12.4 Operating precautions
1) Do not boost the applied drive voltage abnormally. Failure to do so may break
ICs. When applying power voltage, check the electrical features beforehand
and be careful. Always turn off the power to the LC module controller before
removing or inserting the LC module input connector. If the input connector is
removed or inserted while the power is turned on, the LC module internal
circuit may break.
2) The display response may be late if the operating temperature is under the
normal standard, and the display may be out of order if it is above the normal
standard. But this is not a failure; this will be restored if it is within the normal
standard.
3) The LCD contrast varies depending on the visual angle, ambient temperature,
4)
5)
6)
7)
power voltage etc. Obtain the optimum contrast by adjusting the LC dive
voltage.
When carrying out the test, do not take the module out of the low-temperature
space suddenly. Failure to do so will cause the module condensing, leading to
malfunctions.
Make certain that each signal noise level is within the standard (L level:
0.2Vdd or less and H level: 0.8Vdd or more) even if the module has functioned
properly. If it is beyond the standard, the module may often malfunction. In
addition, always connect the module when making noise level measurements.
The CMOS ICs are incorporated in the module and the pull-up and pull-down
function is not adopted for the input so avoid putting the input signal open
while the power is ON.
The characteristic of the semiconductor element changes when it is exposed
to light emissions, therefore ICs on the LCD may malfunction if they receive
light emissions. To prevent these malfunctions, design and assemble ICs so
that they are shielded from light emissions.
Date : 2008/09/18
AMPIRE CO., LTD.
36
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
8) Crosstalk occurs because of characteristics of the LCD. In general, crosstalk
occurs when the regularized display is maintained. Also, crosstalk is affected
by the LC drive voltage. Design the contents of the display, considering
crosstalk.
12.5 Other
1) Do not disassemble or take the LC module into pieces. The LC modules once
disassembled or taken into pieces are not the guarantee articles.
2) The residual image may exist if the same display pattern is shown for hours.
This residual image, however, disappears when another display pattern is
shown or the drive is interrupted and left for a while. But this is not a problem
on reliability.
3) AMIPRE will provide one year warranty for all products and three months
warrantee for all repairing products.
Date : 2008/09/18
AMPIRE CO., LTD.
37
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
晶采 光 電 科技
13 OUTLINE DIMENSION
13.1 OUTLINE DIMENSION-1 (With FFC P0.5x40 pins)
Date : 2008/09/18
AMPIRE CO., LTD.
38
晶采 光 電 科技
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
Date : 2008/09/18
AMPIRE CO., LTD.
39
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
14 Application Note:
/* Exported types ------------------------------------------------------------*/
typedef
unsigned
char
uint8;
typedef
signed
char
int8;
typedef
unsigned
short
uint16;
typedef
signed
short
int16;
typedef
unsigned long
uint32;
typedef
signed
int
int32;
/*****************************************************************/
/*
STEP1: Define MCU BUS type
/*****************************************************************/
#define Mode80
// 8080 MCU /WR /RD
//#define Mode68
// 6800 MCU R/W E
/*****************************************************************/
/*
STEP2: Define BUS wide
/*****************************************************************/
//#define C80_18B
//#define C80_16B
//#define C80_9B
#define C80_8B
/*****************************************************************/
/*
STEP3: Define Landscap/Portrait
/*****************************************************************/
#define Landscap
//#define Portrait
/*****************************************************************/
/*
STEP4: Define Resolution
/*****************************************************************/
#ifdef Landscap
#define
Resolution_X 480
#define
Resolution_Y 234
*/
*/
*/
*/
#endif
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
#ifdef Portrait
#define
Resolution_X 234
#define
Resolution_Y 480
#endif
/*****************************************************************/
/*
STEP5: TFT timing
/*****************************************************************/
#define Rising 0<<2
// Don't need to change
#define Falling 1<<2 // Don't need to change
*/
#define LCD_DCLK 10
/* LCD_DCLK=(40*(0x42)/(0x41))/R10_B10*/
/*5, 6.67, 7.5, 8.57, 10, 12, 15, */
#define LCD_DCLK_Latch
Rising
//0<<2:normal , 1<<2:Inverse
#define H_Sync_Pluse_Wide 10
#define H_Sync_to_DE
68// DE horizontal start position
#define H_Sync_total
440
#define V_Sync_Pluse_Wide 8
#define V_Sync_to_DE
18// DE horizontal start position
#define V_Sync_total
265
//*************************************************************//
/**************Don't need to change the bellow macro**************/
#if LCD_DCLK== 5
#define R41
#define R42
#define R10_B10
#endif
1
1
2
#if LCD_DCLK== 6
#define R41
#define R42
#define R10_B10
#endif
3
4
2
Date : 2008/09/18
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Preliminary
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third part without the prior written consent of AMPIRE CO., LTD
#if LCD_DCLK== 7
#define R41
#define R42
#define R10_B10
#endif
4
3
1
#if LCD_DCLK== 8
#define R41
#define R42
#define R10_B10
#endif
12
10
1
#if LCD_DCLK== 10
#define R41
1
#define R42
1
#define R10_B10 1
#endif
#if LCD_DCLK== 12
#define R41
5
#define R42
6
#define R10_B10 1
#endif
#if LCD_DCLK== 15
#define R41
2
#define R42
3
#define R10_B10 1
#endif
#define _DisplayRAM_WriteEnable_ 0xc1
#define _DisplayRAM_WriteDisable_ 0x80
typedef struct
Date : 2008/09/18
AMPIRE CO., LTD.
42
Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
{
uint8 REG_Index;
uint8 REG_Value;
}FSA506_REG_Setting;
#ifdef
Landscap
static
FSA506_REG_Setting FSA506_A[] =
{
{0x40,0x12},
{0x41,R41},
{0x42,R42},
{0x08,(uint8)(Resolution_X>>8)},
{0x09,(uint8)(Resolution_X)},
{0x0a,0x00},
{0x0b,0x00},
{0x0c,0x00},
{0x10,0x0C|R10_B10},
//{0x10,0x0C|0x02},
{0x11,0x05},
{0x12,0x00},
{0x13,0x00},
{0x14,(uint8)(H_Sync_Pluse_Wide>>8)},
{0x15,(uint8)(H_Sync_Pluse_Wide)},
{0x16,(uint8)(H_Sync_to_DE>>8)},
{0x17,(uint8)(H_Sync_to_DE)},
{0x18,(uint8)(Resolution_X>>8)},
{0x19,(uint8)(Resolution_X)},
{0x1a,(uint8)(H_Sync_total>>8)},
{0x1b,(uint8)(H_Sync_total)},
{0x1c,0x00},
{0x1d,0x00},
{0x1e,(uint8)(V_Sync_Pluse_Wide>>8)},
{0x1f,(uint8)(V_Sync_Pluse_Wide)},
{0x20,(uint8)(V_Sync_to_DE>>8)},
{0x21,(uint8)(V_Sync_to_DE)},
Date : 2008/09/18
AMPIRE CO., LTD.
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{0x22,(uint8)(Resolution_Y>>8)},
{0x23,(uint8)(Resolution_Y)},
{0x24,(uint8)(V_Sync_total>>8)},
{0x25,(uint8)(V_Sync_total)},
{0x26,0x00},
{0x27,0x00},
{0x28,0x00},
{0x29,0x01},
{0x2d,LCD_DCLK_Latch|0x08},
// [7:4] Reserved
// [3] Output pin X_DCON level control
// [2] Output clock inversion 0: Normal 1: Inverse
// [1:0] Image rotate
//
00: 0° 01: 90° 10: 270° 11: 180°
{0x30,0x00},
{0x31,0x00},
{0x32,0x00},
{0x33,0x00},
{0x34,(uint8)(Resolution_X>>8)},
{0x35,(uint8)(Resolution_X)},
{0x36,(uint8)((2*Resolution_Y)>>8)},
{0x37,(uint8)(2*Resolution_Y)},
};
#endif
#ifdef
Portrait
static
FSA506_REG_Setting FSA506_A[] =
{
{0x40,0x12},
{0x41,R41},
{0x42,R42},
{0x08,(uint8)(Resolution_X>>8)},
Date : 2008/09/18
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{0x09,(uint8)(Resolution_X)},
{0x0a,0x00},
{0x0b,0x00},
{0x0c,0x00},
{0x10,0x0C|R10_B10},
//{0x10,0x0C|0x02},
{0x11,0x05},
{0x12,0x00},
{0x13,0x00},
{0x14,(uint8)(H_Sync_Pluse_Wide>>8)},
{0x15,(uint8)(H_Sync_Pluse_Wide)},
{0x16,(uint8)(H_Sync_to_DE>>8)},
{0x17,(uint8)(H_Sync_to_DE)},
{0x18,(uint8)(Resolution_Y>>8)},
{0x19,(uint8)(Resolution_Y)},
{0x1a,(uint8)(H_Sync_total>>8)},
{0x1b,(uint8)(H_Sync_total)},
{0x1c,0x00},
{0x1d,0x00},
{0x1e,(uint8)(V_Sync_Pluse_Wide>>8)},
{0x1f,(uint8)(V_Sync_Pluse_Wide)},
{0x20,(uint8)(V_Sync_to_DE>>8)},
{0x21,(uint8)(V_Sync_to_DE)},
{0x22,(uint8)(Resolution_X>>8)},
{0x23,(uint8)(Resolution_X)},
{0x24,(uint8)(V_Sync_total>>8)},
{0x25,(uint8)(V_Sync_total)},
{0x26,0x00},
{0x27,0x00},
{0x28,0x00},
{0x29,0x01},
{0x2d,LCD_DCLK_Latch|0x08|0x01},
// [7:4] Reserved
// [3] Output pin X_DCON level control
// [2] Output clock inversion 0: Normal 1: Inverse
// [1:0] Image rotate
Date : 2008/09/18
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//
00: 0°
01: 90°
10: 270° 11: 180°
{0x30,0x00},
{0x31,0x00},
{0x32,0x00},
{0x33,0x00},
{0x34,(uint8)(Resolution_X>>8)},
{0x35,(uint8)(Resolution_X)},
{0x36,(uint8)((2*Resolution_Y)>>8)},
{0x37,(uint8)(2*Resolution_Y)},
};
#define
NOP()
__asm{NOP}
#endif
/**************Don't need to change the above macro**************/
void AMP506_80Mode_Command_SendAddress(uint8 Addr);
void AMP506_80Mode_Command_SendData(uint8 Data);
void AMP506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit);
void AMP506_Command_Write(uint8 CMD_Address,uint8 CMD_Value);
void Initial_AMP506(void) ;
void AMP506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y) ;
void FD506_DisplayRAM_WriteEnable(void);
void FD506_DisplayRAM_WriteDisable(void);
void GUI_RectangleFill(uint32 x0, uint32 y0, uint32 x1, uint32 y1, uint16
color);
void Full_LCD(uint16 Dat16bit);
void LCD_Pixel(uint16 x , uint16 y , uint16 couleur);
/**************FSA506 Write Registr Address function *************************/
void AMP506_80Mode_Command_SendAddress(uint8 Addr)
{
#ifdef Mode68
uint16 i;
Date : 2008/09/18
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CLR_nWRL;
CLR_RS;
CLR_CS1;
CLR_nRD;
DB16OUT(Addr);
NOP();NOP();
SET_nWRL;
//Enable
NOP();NOP();NOP(); NOP();NOP();//NOP(); NOP();NOP();NOP();
CLR_nWRL;
//Enable
SET_RS;
SET_CS1;
#endif
#ifdef Mode80
SET_nRD;
//SET_RW
CLR_RS;
DB16OUT(Addr); NOP();
CLR_CS1;
CLR_nWRL;
//CLR_E
NOP();NOP();NOP();
SET_nWRL;
AMP506 Buffer
SET_RS;
SET_CS1;
#endif
//SER_E
// Low to High Latch Data to
}
/**************FSA506 Write Command Data function *************************/
void AMP506_80Mode_Command_SendData(uint8 Data)
{
#ifdef Mode68
uint16 i;
CLR_nWRL;
//E
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SET_RS;
CLR_CS1;
CLR_nRD; //W/R
DB16OUT(Data);
NOP();NOP();
SET_nWRL;
NOP();NOP();NOP();NOP();NOP();//NOP();NOP();NOP();
CLR_nWRL;
//E nable
SET_RS;
SET_CS1;
#endif
#ifdef Mode80
SET_nRD;
SET_RS;
DB16OUT(Data); NOP(); // NOP()
CLR_CS1;
CLR_nWRL;
NOP();NOP();NOP();
SET_nWRL;
Buffer
SET_RS;
SET_CS1;
#endif
// Low to High Latch Data to AMP506
}
/**************FSA506 Write Data function *************************/
void AMP506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit)
{
#ifdef Mode80
#ifdef C80_16B
SET_nRD;
SET_RS;
DB16OUT(Dat16bit);NOP();
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CLR_CS1;
CLR_nWRL;
NOP(); NOP();
NOP();
SET_nWRL;
Buffer
SET_CS1;
// Low to High Latch Data to AMP506
#endif
#ifdef C80_8B
DB16OUT(Dat16bit>>8);NOP();NOP();
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
NOP(); NOP();
SET_nWRL;
Buffer
SET_CS1;
NOP();
// Low to High Latch Data to AMP506
//Delay_uS(1);
DB16OUT(Dat16bit);NOP(); NOP();
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
NOP(); NOP(); NOP();
SET_nWRL;
Buffer
SET_CS1;
// Low to High Latch Data to AMP506
#endif
Date : 2008/09/18
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third part without the prior written consent of AMPIRE CO., LTD
//Delay_uS(1);
#ifdef C80_18B
uint32 k=0;
uint16 R_temp,G_temp,B_temp;
R_temp=((0xf800&Dat16bit)>>11);
G_temp=((0x07e0&Dat16bit)>>5);
B_temp=((0x001f&Dat16bit));
k|=((R_temp<<1)<<12);
k|=(G_temp<<6);
k|=(B_temp<<1);
//+G_temp+B_temp;
FIO1MASK=0xFFE0FFFF;
// FIOMASK 只可寫 P1.20~P1.16
FIO1PIN=k;
// 將 Address A20~A16 寫入 P1.20~P1.16
FIO1MASK=0x00;
SET_nRD;
SET_RS;
DB16OUT(k);NOP();
CLR_CS1;
CLR_nWRL;
NOP(); NOP();
SET_nWRL;
Buffer
SET_CS1;
NOP();
// Low to High Latch Data to AMP506
#endif
#ifdef C80_9B
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uint32 k=0;
uint16 R_temp,G_temp,B_temp;
R_temp=((0xf800&Dat16bit)>>11);
G_temp=((0x07e0&Dat16bit)>>5);
B_temp=((0x001f&Dat16bit));
k|=((R_temp<<1)<<12);
k|=(G_temp<<6);
k|=(B_temp<<1);
//+G_temp+B_temp;
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB16OUT(((k&0x3FE00)>>9));
SET_nWRL;
Buffer
DB16OUT((k&0x1FF)); NOP();
SET_CS1;
// Delay_uS(1);
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
NOP(); NOP();
SET_nWRL;
Buffer
SET_CS1;
// Low to High Latch Data to AMP506
NOP();
// Low to High Latch Data to AMP506
#endif
#endif
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#ifdef Mode68
#ifdef C80_16B
uint16 i;
NOP();NOP();
CLR_nWRL;
//E=0
SET_RS;
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT(Dat16bit);
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Buffer
SET_CS1;
#endif
#ifdef C80_8B
uint16 i;
//for (i=0;i<16;i++);
NOP();NOP();
CLR_nWRL;
//E=0
SET_RS;
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT(Dat16bit>>8);
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
Buffer
SET_CS1;
CLR_nWRL;
//E=0
SET_RS;
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT(Dat16bit);
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Buffer
SET_CS1;
#endif
//Delay_uS(1);
#ifdef C80_18B
uint32 k=0;
uint16 R_temp,G_temp,B_temp;
uint16 i;
NOP();NOP();
R_temp=((0xf800&Dat16bit)>>11);
G_temp=((0x07e0&Dat16bit)>>5);
B_temp=((0x001f&Dat16bit));
k|=((R_temp<<1)<<12);
k|=(G_temp<<6);
k|=(B_temp<<1);
//+G_temp+B_temp;
FIO1MASK=0xFFE0FFFF;
// FIOMASK 只可寫 P1.20~P1.16
FIO1PIN=k;
// 將 Address A20~A16 寫入 P1.20~P1.16
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
FIO1MASK=0x00;
CLR_nWRL;
//E=0
SET_RS;
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT(k);
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();NOP();//NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Buffer
SET_CS1;
#endif
#ifdef C80_9B
uint32 k=0;
uint16 R_temp,G_temp,B_temp;
uint16 i;
//for (i=0;i<16;i++);
NOP();NOP();
R_temp=((0xf800&Dat16bit)>>11);
G_temp=((0x07e0&Dat16bit)>>5);
B_temp=((0x001f&Dat16bit));
k|=((R_temp<<1)<<12);
k|=(G_temp<<6);
k|=(B_temp<<1);
CLR_nWRL;
SET_RS;
Date : 2008/09/18
//+G_temp+B_temp;
//E=0
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT(((k&0x3FE00)>>9));
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Buffer
SET_CS1;
// Delay_uS(1);
CLR_nWRL;
//E=0
SET_RS;
CLR_CS1;
CLR_nRD; // W/R=0
DB16OUT((k&0x1FF));
SET_nWRL;
// Low to High Latch Data to AMP506
Buffer
NOP();NOP();NOP();NOP();//NOP();NOP();NOP();NOP();
CLR_nWRL;
// Low to High Latch Data to AMP506
Buffer
SET_CS1;
#endif
#endif
}
/**************FSA506 Write Command function *************************/
void AMP506_Command_Write(uint8 CMD_Address,uint8 CMD_Value)
{
AMP506_80Mode_Command_SendAddress(CMD_Address);
AMP506_80Mode_Command_SendData(CMD_Value);
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
}
/**************FSA506 Initial function
void Initial_AMP506(void)
{
*************************/
//
uint8 i;
for(i=0;i < (sizeof(FSA506_A) / sizeof (FSA506_A[0]));i++)
{
AMP506_Command_Write(FSA506_A[i].REG_Index
FSA506_A[i].REG_Value);
,
}
}
/**************FSA506 Set Start & End area function *************************/
void AMP506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y)
{
AMP506_80Mode_Command_SendAddress(0x00);
AMP506_80Mode_Command_SendData((S_X)>>8);
AMP506_80Mode_Command_SendData(S_X);
AMP506_80Mode_Command_SendData((E_X-1)>>8);
AMP506_80Mode_Command_SendData(E_X-1);
AMP506_80Mode_Command_SendData(S_Y>>8);
AMP506_80Mode_Command_SendData(S_Y);
AMP506_80Mode_Command_SendData((E_Y-1)>>8);
Date : 2008/09/18
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
AMP506_80Mode_Command_SendData(E_Y-1);
}
//****************************************************************************
//
Enable Display RAM Write
//****************************************************************************
void FD506_DisplayRAM_WriteEnable(void)
{
AMP506_80Mode_Command_SendAddress(_DisplayRAM_WriteEnable_);
}
//****************************************************************************
//
Disable Display RAM Write
//****************************************************************************
void FD506_DisplayRAM_WriteDisable(void)
{
AMP506_80Mode_Command_SendAddress(_DisplayRAM_WriteDisable_);
}
/**************FSA506 Set Start & End area function *************************/
void GUI_RectangleFill(uint32 x0, uint32 y0, uint32 x1, uint32 y1, uint16
color)
{
uint32 k,l;
AMP506_WindowSet(x0,y0,x1,y1);
FD506_DisplayRAM_WriteEnable();
for(k=y0;k<y1;k++)
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
{
for(l=x0;l<x1;l++)
{
AMP506_80Mode_16Bit_Memory_SendData(color);
}
}
FD506_DisplayRAM_WriteDisable();
}
/**************Full Display function
void Full_LCD(uint16 Dat16bit)
{
*************************/
GUI_RectangleFill(0,0,Resolution_X,Resolution_Y,Dat16bit);
}
void LCD_Pixel(uint16 x , uint16 y , uint16 couleur)
{
uint8 hiByte, lowByte;
AMP506_80Mode_Command_SendAddress(0x00);
AMP506_80Mode_Command_SendData((x)>>8);
AMP506_80Mode_Command_SendData(x);
AMP506_80Mode_Command_SendData((x)>>8);
AMP506_80Mode_Command_SendData(x);
AMP506_80Mode_Command_SendData(y>>8);
AMP506_80Mode_Command_SendData(y);
AMP506_80Mode_Command_SendData((y)>>8);
AMP506_80Mode_Command_SendData(y);
FD506_DisplayRAM_WriteEnable();
AMP506_80Mode_16Bit_Memory_SendData(couleur);
FD506_DisplayRAM_WriteDisable();
Date : 2008/09/18
AMPIRE CO., LTD.
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Preliminary
The contents of this document are confidential and must not be disclosed wholly or in part to any
third part without the prior written consent of AMPIRE CO., LTD
}
void main(void)
{
Initial_AMP506();
Full_LCD(0xf800);
Full_LCD(0x07e0);
Full_LCD(0x001f);
}
Date : 2008/09/18
AMPIRE CO., LTD.
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