AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable www.azmicrotek.com FEATURES DESCRIPTION • Minimizes External Components • Selectable Enable Polarity and Threshold (CMOS or PECL) • High Bandwidth for ≥1GHz • Similar operation as AZ100EL16VO • -147 dBc/Hz Typical Noise Floor The AZ100LVEL16VR is a specialized oscillator gain stage with a high gain output buffer including an enable function. The QHG/Q ¯ HG outputs have voltage gain several times greater than the Q/Q ¯ outputs. It provides a selectable QHG/Q ¯ HG enable that allows continuous oscillator operation via the Q/Q ¯ outputs. The AZ100LVEL16VR provides adjustable internal pull-down current sources for the Q/Q ¯ outputs and optional 10mA current sources for the QHG/Q ¯ HG outputs. Internal input biasing further reduces the number of needed external components BLOCK DIAGRAM APPLICATIONS • 4mA each Q Q CS-SEL D QHG D QHG 470Ω 10mA each VBB PACKAGE AVAILABILITY • 75kΩ PULL-UP • EN VEEP Crystal or saw oscillators that require minimal external components. MLP8 o Green/RoHS Compliant/Pb-Free MLP16 o Green/RoHS Compliant/Pb-Free VEE 75kΩ PULL-DOWN CMOS THRESHOLD EN-SEL Order Number AZ100LVEL16VRLG1 Package MLP16 Marking 100G / 16R / <Date Code>2 AZ100LVEL16VRNEG1 MLP8 R5G / <Date Code>2 1 Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description AZ100LVEL16VRL Pin Name Type Function 1 NC - N/A 2 D Input Data Input 3 D ¯ Input Inverting Data Input 4 VBB Output Reference Voltage 5 EN Input Output Enable 6 NC - N/A 7 VEE Power Negative Supply 8 VEEP Input High Gain Current Source Enable 9 EN-SEL Input 10 Q ¯ HG 11 Q Q NC VCC 16 15 14 13 NC 1 D 2 Enable Polarity Select D 3 Output High Gain Inverting PECL Output VBB 4 QHG Output High Gain PECL Output 12 CS-SEL Input Current Source Select 5 6 7 8 13 VCC Power Positive Supply EN NC VEE VEEP 14 NC - N/A 15 Q Output PECL Output 16 Q ¯ Output Inverting PECL Output 12 CS-SEL Leave Pad Open or Connect to VEE 11 QHG 10 QHG 9 EN-SEL Figure 1 - Pin Configuration for AZ100LVEL16VRL Table 2 - Pin Description AZ100LVEL16VRNEG Pin Name Type Function 1 D Input Data Input 2 VBB Output Reference Voltage 3 EN Input Output Enable 4 VEE Power Negative Supply 5 Q ¯ HG Output High Gain Inverting PECL Output 6 QHG Output High Gain PECL Output 7 VCC Power Positive Supply 8 Q ¯ Output Inverting PECL Output D 1 VBB 2 EN 3 VEE 4 Leave Pad open or connect to VEE 8 Q 7 VCC 6 QHG 5 QHG Figure 2 - Pin Configuration for AZ100LVEL16VRNEG www.azmicrotek.com +1-480-962-5881 Request a Sample 2 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable ENGINEERING NOTES FUNCTIONALITY MLP16 PACKAGE (AZ100LVEL16VRL) The AZ100LVEL16VR provides a selectable QHG/Q ¯ HG enable that allows continuous oscillator operation via the Q/Q ¯ outputs. Table 3 shows the operating modes. Leaving EN-SEL open (NC) selects PECL/ECL operation for the EN pad/pin. In this mode the QHG/Q ¯ HG outputs are enabled when EN is left open (NC) or set to a PECL/ECL low. Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to VEE, the QHG/Q ¯ HG outputs are disabled when EN is left open (NC). When EN-SEL is tied to VCC or VBB, the QHG/Q ¯ HG outputs are enabled when EN is left open. This default logic condition can be overridden by a ≤ 20kΩ resistor connected to the opposite supply. The AZ100LVEL16VR also provides a VBB and 470Ω internal bias resistors from D to VBB and D ¯ to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a 0.01 µF capacitor. Outputs Q/Q ¯ each have a selectable on-chip pull-down current source. See Table 4 for the supported values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for the Q/Q ¯ outputs. Each of the QHG/Q ¯ HG outputs has an optional on-chip pull-down current source of 10mA. When pad/pin VEEP is left open (NC), the output current sources are disabled and the QHG /Q ¯ HG operate as standard PECL/ECL. When VEEP is connected to VEE, the current sources are activated. The QHG /Q ¯ HG pull-down current can be decreased by using a resistor between VEEP and VEE. 4mA EA. Q Q CS-SEL D QHG D QHG 470Ω 10mA EA. VBB 75kΩ PULL-UP EN VEEP VEE 75kΩ PULL-DOWN EN-SEL CMOS THRESHOLD Figure 3 - AZ100LVEL16VRL Block Diagram www.azmicrotek.com +1-480-962-5881 Request a Sample 3 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable Table 3 – Enable Truth Table EN-SEL EN PECL Low, VEE or NC PECL High or VCC CMOS Low, VEE or NC CMOS High or VCC CMOS Low or VEE CMOS High, VCC or NC NC VEE1 VCC or VBB1,2 1 EN-SEL connections must be ≤1Ω. 2 Date codes prior to 0428 do not support this operating mode. Q/Q ¯ Data Data Data Data Data Data QHG Data Low Low Data Low Data Q ¯ HG Data High High Data High Data Table 4 - Current Source Truth Table CS-SEL Q Q ¯ NC VEE1 4mA typ 8mA typ VCC1 0 4mA typ 8mA typ 4mA typ Connection must be less than 1Ω 1. Figure 3 illustrates the timing sequences for the AZ100LVEL16VR in the MLP 16 package or as die. It is shown here with the enable operating in active Low mode with a PECL threshold. This mode is determined by leaving the EN-SEL open (NC). An active High enable with a CMOS/TTL threshold is also an option. D EN (PECL) Q Q QHG QHG Figure 4 - AZ100LVEL16VRL Timing Diagram www.azmicrotek.com +1-480-962-5881 Request a Sample 4 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable FUNCTIONALITY MLP8 PACKAGE (AZ100LVEL16VRNEG) A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open (NC), the Q ¯ and QHG/Q ¯ HG outputs follow the data input. When EN is LOW, the QHG output is forced high and the Q ¯ HG output is forced low while Q ¯ continues to follow the data input. The Q ¯ output has an internal 4 mA current source to VEE, in most cases eliminating the need for an external pull-down resistor. The AZ100LVEL16VRNEG also provides biasing. Data input D is tied to the VBB pin through a 470Ω internal bias resistor while the inverting input D ¯ is connected directly to VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground with a 0.01 µF capacitor. 4mA Q D QHG 470Ω QHG VBB VEE EN Figure 5 - AZ100LVEL16VRNEG Block Diagram D EN (CMOS) Q QHG QHG Figure 6 - AZ100LVEL16VRNEG Timing Diagram www.azmicrotek.com +1-480-962-5881 Request a Sample 5 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable VOUTpp (mV) 1000 900 800 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 FREQUENCY (MHz) 3000 3500 4000 AC Coupling Capacitor C2 R1 See table EL16VO Front End 3.3 or 5 V CMOS D R2 470 Ω D VBB C1 0.01 μF Figure 7 - Application Circuit for CMOS Inputs Recommended Component Values for CMOS Single Ended Inputs R11 Value AC Coupled (C2 in circuit) DC Coupled (C2 shorted) 3.3 V CMOS 1.1 kΩ 2.0 kΩ 5.0 V CMOS 1.6 kΩ 3.3 kΩ R1 should be chosen so that the input swing on the D input with respect to D ¯ is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the D input is < ±750 mV with respect to VBB. Input Type 1. www.azmicrotek.com +1-480-962-5881 Request a Sample 6 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable 0 0.9 -10 0.85 -20 Phase Magnitude 0.95 0.8 -30 0.75 -40 0.7 S11 MAG 8mA S11 MAG 4mA S11 PHASE 8mA -50 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) 0.025 225 0.02 200 0.015 175 Phase Magnitude Figure 8 - S11 50Ω external AC, 4 & 8mA internal DC load 0.01 150 0.005 125 0 S12 MAG 8mA S12 MAG 4mA S12 PHASE 8mA 100 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) Figure 9 - S12 50Ω external AC, 4 & 8mA internal DC load www.azmicrotek.com +1-480-962-5881 Request a Sample 7 February 2014, Rev 2.2 AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable 40 200 35 175 30 150 25 125 20 100 15 75 10 50 5 25 0 Phase Magnitude Arizona Microtek, Inc. S21 MAG 8mA S21 MAG 4mA S21 PHASE 8mA 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) 0.8 200.00 0.75 190.00 0.7 180.00 0.65 170.00 0.6 160.00 0.55 150.00 0.5 140.00 0.45 130.00 0.4 Phase Magnitude Figure 10 – S21 50Ω external AC, 4 & 8mA internal DC load S22 MAG 8mA S22 MAG 4mA S22 PHASE 8mA 120.00 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) Figure 11 – S22 50Ω external AC, 4 & 8mA internal DC load www.azmicrotek.com +1-480-962-5881 Request a Sample 8 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable PERFORMANCE DATA Table 5 – Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VD_PECL PECL D Input Voltage Referenced to VBB V VEN_PECL PECL D Input Voltage VEE = 0V ±0.75 0 to + 6.0 VEE ECL Power Supply VCC = 0V -6.0 to 0 V VD_ECL ECL D Input Voltage Referenced to VBB ECL D Input Voltage VCC = 0V ±0.75 -6.0 to 0 V VEN_ECL Continuous Q 25 Surge Q 50 Continuous QHG 50 Surge QHG 100 IOUT Output Current V V mA TA Operating Temperature Range - -40 to +85 °C TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V Table 6 - ECL DC Characteristics ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) -40°C Symbol Characteristic VOH Output HIGH Voltage1 VOL 1 0°C 25°C 85°C Unit Min Max Min Max Min Max Min Max -1045 -835 -1025 -835 -1025 -835 -1025 -835 mV -1925 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV Input HIGH Voltage EN (CMOS)3 VEE+ 2000 VCC VEE+ 2000 VCC VEE+ 2000 VCC VEE+ 2000 VCC mV Input LOW Voltage D,EN (ECL)2 -1900 -1475 -1900 -1475 -1900 -1475 -1900 -1475 mV Input LOW Voltage EN (CMOS)3 VEE VEE+ 800 VEE VEE+ 800 VEE VEE+ 800 VEE VEE+ 800 mV VBB Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mV IIH Input HIGH Current EN 150 µA Output LOW Voltage Input HIGH Voltage D,EN (ECL) VIH VIL Input LOW Current EN (ECL) IIL 150 2 Input LOW Current EN (CMOS) 1 IEE Power Supply Current 2 3 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 48 48 1 Specified with each output terminated through 50Ω resistors to VCC - 2V. 2 EN-SEL = NC 3 EN-SEL = VCC or VEE www.azmicrotek.com +1-480-962-5881 Request a Sample 150 48 µA 54 mA 9 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable Table 7 - LVPECL DC Characteristics LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) -40°C Symbol Characteristic VOH Output HIGH Voltage1,2 VOL 1,2 Output LOW Voltage VIH VIL 85°C Unit Min Max Min Max Min Max Min Max 2255 2465 2275 2465 2275 2465 2275 2465 mV 1375 1745 1400 1680 1400 1680 1400 1680 mV Input HIGH Voltage D,EN (ECL) 2135 2560 2135 2560 2135 2560 2135 2560 mV Input HIGH Voltage EN (CMOS) 4 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D,EN (ECL) 3 1400 1825 1400 1825 1400 1825 1400 1825 mV Input LOW Voltage EN (CMOS) 4 GND 800 GND 800 GND 800 GND 800 mV 1910 2050 1910 2050 1910 2050 1910 2050 mV 150 µA 1 Reference Voltage IIH Input HIGH Current EN Input LOW Current EN (ECL) 150 3 Input LOW Current EN (CMOS) 4 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 2 IEE 25°C 3 VBB IIL 0°C Power Supply Current 48 48 µA 48 1 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value 2 Specified with each output terminated through 50Ω resistors to VCC - 2V. 3 EN-SEL = NC 4 EN-SEL = VCC or VEE 54 mA Table 8 - PECL DC Characteristics PECL DC Characteristics (VEE = GND, VCC = +5.0V) -40°C Symbol Characteristic VOH Output HIGH Voltage1,2 VOL 1,2 Output LOW Voltage VIH Unit Min Max Min Max Min Max Min Max 3955 4165 3975 4165 3975 4165 3975 4165 mV 3445 3100 3380 3100 3380 3100 3380 mV Input HIGH Voltage D,EN (ECL) 3835 4260 3835 4260 3835 4260 3835 4260 mV Input HIGH Voltage EN (CMOS) 4 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 3 3100 3525 3100 3525 3100 3525 3100 3525 mV 4 GND 800 GND 800 GND 800 GND 800 mV 3610 3750 3610 3750 3610 3750 3610 3750 mV 150 µA 1 VBB Reference Voltage IIH Input HIGH Current EN Input LOW Current EN (ECL) 150 3 Input LOW Current EN (CMOS) 2 IEE 85°C 3075 Input LOW Voltage EN (CMOS) IIL 25°C 3 Input LOW Voltage D,EN (ECL) VIL 0°C Power Supply Current 4 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 48 48 48 1 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value 2 Specified with each output terminated through 50Ω resistors to VCC - 2V. 3 EN-SEL = NC 4 EN-SEL = VCC or VEE www.azmicrotek.com +1-480-962-5881 Request a Sample µA 54 mA 10 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable Table 9 - AC Characteristics AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol Characteristic -40°C Min Typ 0°C Max Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Propagation Delay tPLH/tPHL D toQ1 1 tSKEW Vpp (AC) D to QHG Duty Cycle Skew3 Input Swing4 Differential Output Rise/Fall1,2 (20% - 80%) tr/tf 1 2 3 5 400 400 400 400 ps 450 450 450 450 ps 20 ps 20 5 20 5 20 5 80 1000 80 1000 80 1000 80 1000 mV 100 240 100 240 100 240 100 240 ps Specified with CS-SEL connected to VEE, Q terminated with an AC coupled to 50Ω load Specified with each output terminated through 50Ω resistors to VCC - 2V. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 4 VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. The device has a voltage gain of ≈20 to Q/ outputs and a voltage gain of ≈100 to QHG outputs. www.azmicrotek.com +1-480-962-5881 Request a Sample 11 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable PACKAGE DIAGRAM MLP16 Green/RoHS compliant/Pb-Free MSL=1 www.azmicrotek.com +1-480-962-5881 Request a Sample 12 February 2014, Rev 2.2 Arizona Microtek, Inc. AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable PACKAGE DIAGRAM MLP8 Green/RoHS compliant/Pb-Free MSL=1 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 13 February 2014, Rev 2.2