AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
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FEATURES
DESCRIPTION
• Minimizes External
Components
• Selectable Enable Polarity and
Threshold (CMOS or PECL)
• 3V to 5.5V Power Supply
• Similar Operation as
AZ100LVEL16VT except
with LVDS Outputs
The AZV99 is a specialized oscillator gain stage with an LVDS output
buffer including an enable. The selectable enable input allows continuous
oscillator operation by only controlling the QHG /Q
¯ HG outputs.
The AZV99 provides adjustable internal pull-down current sources for the
Q/Q
¯ outputs. Internal input biasing further reduces the number of needed
external components
BLOCK DIAGRAM
APPLICATIONS
•
Crystal or saw oscillators that
require minimal external
components
PACKAGE AVAILABILITY
1
2
•
•
•
MLP8
MLP16
MSOP8
•
Green/RoHS Compliant/Pb-Free
Order Number
Package
Marking
AZV99NG 1
MLP8
V1G <Date Code> 2
AZV99NBG 1
MLP8
V8G <Date Code> 2
AZV99NDG 1
MLP8
V2G <Date Code> 2
AZV99LG 1
MLP16
AZMG <Date Code> 2
AZV99T+ 1
MSOP8
AZ+V99 2
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in
See www.azmicrotek.com for date code format
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1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description for AZV99N
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
8
VCC
7
QHG
6
QHG
4
5
VEE
D
1
8
Q
VBB
2
7
VCC
EN
3
6
QHG
VEE
4
5
QHG
Q
1
8
VCC
D
2
7
QHG
VBB
3
6
QHG
EN
4
5
VEE
Q
1
D
2
VBB
3
EN
Leave Pad
open or
connect to
VEE
Table 2 - Pin Description for AZV99NB
Pin
Name
Type
Function
1
D
Input
Data Input
2
VBB
Output
Reference Voltage
3
EN
¯¯
Input
Output Enable
4
VEE
Power
Negative Supply
5
Q
¯ HG
Output
Inverting LVDS Output
6
QHG
Output
LVDS Output
7
VCC
Power
Positive Supply
8
Q
¯
Output
Inverting PECL Output
Leave Pad
open or
connect to
VEE
Table 3 - Pin Description for AZV99ND
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
¯¯
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
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Leave Pad
open or
connect to
VEE
2
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 4 - Pin Description for AZV99L
Pin
Name
Type
Function
1
NC
-
N/A
2
D
Input
Data Input
3
D
¯
Input
Inverting Data Input
4
VBB
Output
Reference Voltage
5
EN
Input
Output Enable
6
NC
-
N/A
7
VEE
Power
Negative Supply
8
NC
-
N/A
9
EN-SEL
Input
Enable Polarity Select
10
Q
¯ HG
Output
Inverting LVDS Output
11
QHG
Output
LVDS Output
12
CS-SEL
Input
Current Source Select
13
VCC
Power
Positive Supply
14
NC
-
N/A
15
Q
Output
PECL Output
16
Q
¯
Output
Inverting PECL Output
Table 5 - Pin Description for AZV99T
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
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Q
1
8
VCC
D
2
7
QHG
VBB 3
6
QHG
EN 4
5
VEE
3
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
ENGINEERING NOTES
FUNCTIONALITY MLP16 PACKAGE (AZV99L)
The AZV99L provides a selectable enable (EN). Enable polarity and threshold can be selected to accommodate either
CMOS/TTL or PECL input levels. If enable pull-up is desired in the CMOS/TTL mode, an external ≤ 20kΩ resistor
connecting EN to VCC will override the on-chip pull-down resistor.
Outputs Q/Q
¯ each have a selectable on-chip pull-down current source. External resistors may also be used to increase
pull-down current to a maximum of 25mA (includes internal on-chip current source).
The AZV99 also provides input biasing which is accomplished with a VBB and 470Ω internal resistors from D to VBB and D
¯ to
VBB. The VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground with a 0.01µF capacitor.
FUNCTIONALITY MLP8 PACKAGE (AZV99NB & AZV99ND)
The AZV99NB and AZV99NB provide a PECL/ECL level enable input (EN
¯¯¯). When the ¯¯¯
EN input is LOW, the Q
¯ and
QHG/Q
¯ HG outputs pass data from the inputs. When ¯¯¯
EN is HIGH, the Q
¯ output continues to pass data while the QHG output
is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current
source).
The AZV99NB and AZV99ND versions operate with a single ended data input (D). The D
¯ input is internally bonded
directly to the VBB pin bypassing the 470Ω bias resistor.
FUNCTIONALITY MLP8 PACKAGE (AZV99N) & MSOP8 PACKAGE (AZV99T)
The AZV99N and AZV99T provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q
¯ and
QHG/Q
¯ HG outputs pass data from the inputs. When EN is LOW, the Q
¯ output continues to pass data while the QHG output is
forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current
source).
The MSOP8 (T) and MLP8 (N) AZV99 operate with a single ended data input (D). The D
¯ input is internally bonded
directly to the VBB pin bypassing the 470Ω bias resistor.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 6 – Enable Truth Table
EN/ EN
Q/ Q
QHG
Q
PECL Low, VEE or NC
Data
Data
Data
PECL High or VCC
Data
High
Low
CMOS/TTL Low, VEE or NC
Data
High
Low
Data
Data
Data
EN-SEL
NC
VEE1
CMOS/TTL High or
VCC2
HG
1
EN-SEL connections must be less than 1Ω.
An external ≤20kΩ pull-up resistor between EN and VCC ensures a High when the
2
EN pin is not driven.
D
EN
{
EN-SEL OPEN
(PECL)
EN-SEL SHORTED TO VEE
(CMOS)
Q
Q
QHG
QHG
Figure 1 – Timing Diagram
Table 7 - Current Source Truth Table
CS-SEL
Q
Q
NC
4mA typ
4mA typ
VEE
8mA typ
8mA typ
VCC1
0
4mA typ
1
1 Connection must be less than 1Ω
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
AC Coupling Capacitor
C2
R1
See table
EL16VO
Front End
3.3 or 5 V
CMOS
D
R2
470 Ω
D
VBB
C1
0.01 μF
Figure 2 - Application circuit for CMOS inputs
Table 8 – Recommended Component Values for CMOS Single Ended Inputs
R11 Value
AC Coupled (C2 in circuit)
DC Coupled (C2 shorted)
3.3 V CMOS
1.1 kΩ
2.0 kΩ
5.0 V CMOS
1.6 kΩ
3.3 kΩ
1. R1 should be chosen so that the input swing on the D input with respect to D
¯
is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the
D input is < ±750 mV with respect to VBB.
Input Type
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Figure 3 - S11, 50Ω AC load
Figure 4 - S12, 50Ω AC load
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Figure 5 – S21, 50Ω AC load
Figure 6 – S22, 50Ω AC load
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PERFORMANCE DATA
Table 9 – Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Condition
Rating
Unit
VCC
PECL Power Supply
VEE = 0V
0 to + 6.0
V
VI
PECL Input Voltage
VEE = 0V
0 to + 6.0
V
VD/D¯
D/D
¯ Input Voltage
Referenced to VBB
±0.75
V
Continuous Q/Q
¯
50
Surge Q/Q
¯
100
Continuous QHG/Q
¯ HG
5
Surge QHG/Q
¯ HG
10
IOUT
Output Current
mA
TA
Operating Temperature Range
-
-40 to +85
°C
TSTG
Storage Temperature Range
-
-65 to +150
°C
ESDHBM
Human Body Model Electro Static Discharge
-
2500
V
ESDMM
Machine Model Electro Static Discharge
-
200
V
ESDCDM
Charged Device Model Electro Static Discharge
-
2000
V
Table 10 - 100K LVPECL DC Characteristics
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
Characteristic
VOH
VOL
Output LOW Voltage
VBB
Reference Voltage1
-40°C
IIH
IIL
IEE
1.
2.
3.
4.
85°C
Unit
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
2255
2465
2275
2465
2275
2465
2275
2465
mV
1,2
1375
1745
1400
1680
1400
1680
1400
1680
mV
1910
2050
1910
2050
1910
2050
1910
2050
mV
Input HIGH Voltage D/D
¯ , EN (ECL)
2135
2560
2135
2560
2135
2560
2135
2560
mV
Input HIGH Voltage EN (CMOS)4
2000
VCC
2000
VCC
2000
VCC
2000
VCC
mV
1400
1825
1400
1825
1400
1825
1400
1825
mV
GND
800
GND
800
GND
800
GND
800
mV
150
µA
3
VIL
25°C
Min
3
VIH
0°C
Input LOW Voltage D/D
¯ , EN (ECL)
4
Input LOW Voltage EN (CMOS)
Input HIGH Current EN
150
150
150
Input LOW Current EN (ECL)
0.5
0.5
0.5
0.5
µA
Input LOW Current EN (CMOS)
-150
-150
-150
-150
µA
2
Power Supply Current
48
48
48
54
mA
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
¯ HG terminated through 50Ω resistors to VCC - 2V.
Specified with VEEP and CS-SEL NC, QHG/Q
EN-SEL = NC.
EN-SEL = VCC or VEE.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 11 - 100K PECL DC Characteristics
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
-40°C
Symbol
Characteristic
VOH
VOL
Output LOW Voltage
VBB
Reference Voltage1
VIL
IIH
IIL
IEE
1.
2.
3.
4.
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
3955
4165
3975
4165
3975
4165
3975
4165
mV
1,2
3075
3445
3100
3380
3100
3380
3100
3380
mV
3610
3750
3610
3750
3610
3750
3610
3750
mV
3835
4260
3835
4260
3835
4260
3835
4260
mV
Input HIGH Voltage EN (CMOS)
2000
VCC
2000
VCC
2000
VCC
2000
VCC
mV
Input LOW Voltage D/D
¯ , EN (ECL)3
3100
3525
3100
3525
3100
3525
3100
3525
mV
GND
800
GND
800
GND
800
GND
800
mV
150
µA
3
VIH
0°C
Input HIGH Voltage D/D
¯ , EN (ECL)
4
4
Input LOW Voltage EN (CMOS)
Input HIGH Current EN
150
150
150
Input LOW Current EN (ECL)
0.5
0.5
0.5
0.5
µA
Input LOW Current EN (CMOS)
-150
-150
-150
-150
µA
2
Power Supply Current
48
48
48
54
mA
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
¯ HG terminated through 50Ω resistors to VCC - 2V.
Specified with VEEP and CS-SEL NC, QHG/Q
EN-SEL = NC.
EN-SEL = VCC or VEE.
Table 12 – LVDS DC Characteristics
LVDS DC Characteristics for QHG/Q
¯ HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V)
Symbol
-40°C
Characteristic
Min
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOC
Output Common Mode Voltage2
0°C
Max
Min
1600
25°C
Max
Min
1600
900
900
85°C
Max
Min
1600
900
Unit
Max
1600
900
mV
mV
1125
1375
1125
1375
1125
1375
1125
1375
mV
-50
50
-50
50
-50
50
-50
50
mV
∆VOC
Change in Common Mode Voltage
VOUT
Single-Ended Output Swing
250
450
250
450
250
450
250
450
mV
VDIFF_OUT
Differential Output Swing
500
900
500
900
500
900
500
900
mV
1.
2.
3.
3
Specified with 100Ω resistor connecting QHG and Q
¯ HG together.
¯ HG during a steady state.
Common mode voltage is the center voltage between QHG and Q
Change in common mode voltage is the difference between common mode voltages at opposite binary states.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 13 – AC Characteristics
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
-40°C
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Propagation Delay
tPLH/tPHL
D to Q/Q
¯1
D to QHG/Q
¯ HG
tSKEW
2
Duty Cycle Skew3
5
400
400
400
400
ps
450
450
450
450
ps
20
ps
20
5
20
5
20
5
4
Input Swing
Vpp (AC)
tr/tf
1.
2.
3.
4.
Differential
80
1000
80
1000
80
1000
80
1000
mV
Single Ended
Output Rise/Fall1,2
(20%-80%)
150
2000
150
2000
150
2000
150
2000
mV
Q/Q
¯1
100
260
100
260
100
260
100
260
ps
QHG/Q
¯ HG2
180
280
180
280
180
280
180
280
ps
Specified with CS-SEL connected to VEE and Q/Q
¯ with AC coupled 50Ω loads.
Specified with 100Ω resistor connecting QHG and Q
¯ HG together.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and VD¯ must remain within the
range of ±750 mV with respect to VBB.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MLP8
Green/RoHS compliant/Pb-Free
MSL=1
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MLP16
Green/RoHS compliant/Pb-Free
MSL=1
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13
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MSOP8
Green/RoHS compliant/Pb-Free
MSL=1
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of
any product or circuit and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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May 2012, Rev 2.0