AN47 S i321 X L INEFEED P OWER M ONITORING AND P ROTECTION The Silicon Laboratories’ ProSLIC products are designed to continuously monitor the power dissipated in each of the six external bipolar transistors in the linefeed circuit. These power measurement results are available to the user in software registers and are also used by the ProSLIC to protect linefeed transistors from damage due to overpower conditions. Using proper power threshold and thermal low-pass filter settings, the ProSLIC will either alert the user or automatically transition the open state in the event of an overpower condition. 1.1. Power Threshold As the dissipated power in linefeed transistors increases, so does the junction temperature of the transistor die. The maximum admissible junction temperature must not be exceeded because this could damage or destroy the transistor die. In the Si321x, the measured power consumed in each of the transistors is compared to the power threshold values in the corresponding indirect registers. If the power in any external transistor exceeds the programmed threshold (after passing through a user-programmable low pass filter which will be explained in the next section), a power alarm is triggered to indicate line fault condition. Unless the auto-open feature is disabled (direct register 67, bit 0), the ProSLIC automatically goes into the open state. The value of the power threshold is calculated based on the characteristic of the transistors used. Transistor manufacturers provide this information in terms of thermal resistance for each transistor package. The relationship between the maximum junction temperature and the maximum power that can be dissipated by the transistor package is defined in the following equation: T JMAX = T AMB + P MAX × R THJA where TJMAX is the maximum junction temperature (usually 150 °C), TAMB is the ambient temperature (70 °C for commercial rating), and PMAX is the maximum power allowance on the transistor package. RTHJA is the junction to ambient thermal resistance of the transistor package. Rev. 0.3 4/08 The thermal resistance (RTHJA) of the transistor is improved when it is mounted on a PCB board. This improvement depends on the PCB size, the material it is made of, and the amount of the copper surface on the PCB board. Figure 1 illustrates how the board material, available board area, and the amount of copper present influence the thermal resistance of the transistors. This chart can be obtained from the transistor manufacturer if not included in the transistor data sheet. 450 Thermal Resistance (°C/W) 1. Introduction FR4 Min. Copper 300 SRBP Min. Copper SRBP Max. Copper 150 FR4 Max. Copper 0 0.01 0.1 1 10 P.C.B. Area (Sq.Ins.) Thermal Resistance v P.C.B. Area Figure 1. SOT23 In practice, the transistors are normally mounted on a PCB with several square inches area, but for illustration purposes consider a model in which the transistor package is mounted on 1-inch square of FR4 PCB with 0.25-inch square of copper surface. This 1-inch square PCB model and the thermal resistance vs. PCB area charts provide the practical thermal resistances for the following transistor packages: SOT23: RTHJA = 200 °C/W The thermal resistance can also be obtained from the transient thermal resistance curve with D = 1 as shown in Figure 2 and Figure 3. SOT89: RTHJA = 82.5 °C/W SOT223: RTHJA = 62.5 °C/W Copyright © 2008 by Silicon Laboratories AN47 AN47 where P12 and P56 may range from 0 to 7.752 W, and P34 may range from 0 to 0.923 W !" The following is an example of how to calculate the power thresholds for Q1=Q2=Q5=Q6=SOT223 and Q3=Q4=SOT23 with a maximum ambient temperature of 70 °C and a maximum allowable junction temperature of 150 °C T JMAX – T AMB 150 °C – 70 °C P SOT223 = -------------------------------------- = --------------------------------------- = 1.28 W R THJA 62.5 °C/W T JMAX – T AMB 150 °C – 70 °C P SOT23 = -------------------------------------- = --------------------------------------- = 400 mW 200 °C/W R THJA therefore, P12 = P56 = PSOT223 and P34 = PSOT23 1.28 PPT12[7:0] = round ⎛⎝ ------------------⎞⎠ = 42 (d), therefore: 0.0304 Figure 2. SOT89 7 Indirect Reg 32[15:0] = 42 × 2 = 5376(d) = 0x1500 0.4 PPT34[7:0] = round ⎛⎝ ---------------------⎞⎠ = 110 (d), therefore: 0.00362 7 Indirect Reg 33[15:0] = 110 × 2 = 14080(d) = 0x3700 1.28 PPT56[7:0] = round ⎛ ------------------⎞ = 42 (d), therefore: ⎝ 0.0304⎠ 7 Indirect Reg 34[15:0] = 42 × 2 = 5376(d) = 0x1500 1.2. Thermal Low Pass Filter Figure 3. SOT223 The power threshold for each transistor pair (Q1/Q2, Q3/Q4, Q5/Q6) may be set by programming Indirect Register 32-34 (Indirect Registers 19-21 for the Si3215/16). The equations for these parameters follow: P 12 PPT12[7:0] = round ⎛ ------------------⎞ , ⎝ 0.0304⎠ therefore Indirect Reg32[15:0] = PPT12[7:0] × 2 7 P 34 PPT34[7:0] = round ⎛⎝ ------------------⎞⎠ , 0.0304 therefore Indirect Reg33[15:0] = PPT34[7:0] × 2 2 Calculation of the thermal low pass filter is based on the characteristic of the transistor package. The heating process of the transistor package is an exponential phenomenon which can be described by the following equation: 7 P 56 PPT56[7:0] = round ⎛ ------------------⎞ , ⎝ 0.0304⎠ therefore Indirect Reg34[15:0] = PPT56[7:0] × 2 While the power threshold coefficient sets the absolute maximum dc power that the transistor can handle for an indefinite period of time, it only provides a static maximum dc trip point. In the Si321x circuit application, the transistors are subjected to complex power dissipation, which is comprised of dc biasing current and ac signaling. The ac part of the power dissipation may be limited to short times and with repeated pulse (ringing). A static maximum power threshold setting does not provide an adequate model for real operating conditions. In conjunction with the power threshold setting, the Si321x also provides the thermal low pass filter setting which models the operating condition more accurately. 7 T ( t ) = T DC ( 1 – e –t ⁄ τ ) Where TDC is the final temperature and, τ is the thermal time constant. Thermal resistance (θ) may replace the temperature (T) in this equation since they both represent the temperature of the transistor package. Rev. 0.3 AN47 θ ( t ) = θ DC ( 1 – e –t ⁄ τ allowing the setting of the thermal constants (τ) to the registers. Figure 4 shows the heating and cooling of the transistor package. Power is applied to the transistor and heats it up during t1. It is allowed to cool during t2. ) Equation 1 Where θDC is the dc thermal resistance. The Si321x implements this transfer function by P P MAX t1 t2 T t 2 = 4 t1 T MAX Figure 4. Transistor Package Heating and Cooling The θEFF is defined as the thermal resistance of the transistor package at t = τ (one time constant). θ EFF = θ ( τ ) = θ DC ( 1 – e –τ ⁄ τ –1 ) = θ DC ( 1 – e ) = 0.63θ DC Equation 2 The cooling process of the transistor is also an exponential process which can be described by the following equation: θ ( t ) = θ DC × e θ ( 4τ ) = θ DC × e Below is the calculation example of the power threshold coefficient for the SOT223 package. From Figure 2: θDC = 62.5 (D = 1 line) From Equation 2: θEFF = .63θDC = 39.4 Using θEFF = 39.4 to find the thermal period (tP) in Figure 3, using D = .2, curve: tP = 15 s –t ⁄ τ When t = 4τ the θDC (initial condition) is decayed to almost zero. –4τ ⁄ τ This estimation process is graphically illustrated in Figure 5. = 0.18θ DC τ = 0.2t P = 3 s The equation for calculating the thermal LPF register is given in the Si321x data sheet: Equation 3 The thermal time constant (τ) can be estimated by calculating the θEFF with Equation 2 and the θDC data from the Transient Thermal Resistance curves. The thermal period (tP) can then can be found on the Transient Thermal Resistance graph using the θEFF value and the D = .2 curve. Rev. 0.3 4096 3 Thermal LPF register = ⎛ -------------⎞ × 2 ⎝ 800τ⎠ 3 4096 = ⎛ ------------------⎞ × 2 = 13.7 ⎝ 800 ( 3 )⎠ = 0x0E (hex) 3 AN47 θ J-A θ DC D=1 θ EFF (63% of θ DC ) D = .2 tP t Figure 5. Thermal Time Constant (τ) Estimation Table 1. Power Coefficients for Some Transistor Packages Indirect Register SOT23 SOT89 SOT223 32 (Q1/Q2 Power Threshold) 0x0700 0x0FF0 0x1500 33 (Q3/Q4 Power Threshold) 0x3700 0x7F80 0x7F80 34 (Q5/Q6 Power Threshold) — 0x0FF0 0x1500 37 (Q1/Q2 Power LPF) 0x0088 0x0010 0x0008 38 (Q3/Q4 Power LPF) 0x0088 0x0010 0x0008 39 (Q5/Q6 Power LPF) — 0x0010 0x0008 *Note: While the maximum power threshold for these transistors falls outside the range of Indirect Register 33, 0x7F80 is a conservative estimate of a threshold above the maximum power Q3 and Q4 would be dissipating in a normal application. 1.3. Power Dissipation in the Si3201 The Si3201 is a line-side IC that replaces the discrete transistors in the Si321x schematic. Because the Si3201 circuitry differs from that of the discrete components, it is difficult to compute a maximum power threshold per transistor. Silicon Laboratories recommends SOT89 register settings (as shown in Table 1) when using the Si3201 linefeed IC. 4 Rev. 0.3 AN47 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Changed power threshold values for SOT89/223 transistors Corrected calculations Added information for the Si3201 Revision 0.2 to Revision 0.3 Rewrote equations to distinguish PPTxx parameter value from the Indirect Register value. Corrected calculation results that indicated that the PPTxx field extended into bits 6:0 of the register. Corrected recommended settings in Table 1 on page 4. Rev. 0.3 5 AN47 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 6 Rev. 0.3

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