TS9002 Low-Power Single/Dual-Supply Dual Comparator with Reference FEATURES ♦ Ultra-Low Quiescent Current: 4μA (max), Both Comparators plus Reference ♦ Single or Dual Power Supplies: Single: +2.5V to +11V Dual: ±1.25V to ±5.5V ♦ Input Voltage Range Includes Negative Supply ♦ 7μs Propagation Delay ♦ Push-pull TTL/CMOS-Compatible Outputs ♦ Crowbar-Current-Free Switching ♦ Continuous Source Current Capability: 40mA ♦ Internal 1.182V ±0.75% Reference ♦ Adjustable Hysteresis ♦ 8-pin MSOP Package APPLICATIONS Threshold Detectors Window Comparator Level Translators Oscillator Circuits Battery-Powered Systems DESCRIPTION The TS9002 low-voltage, micropower dual analog comparator is form-factor identical to the MAX923 analog comparator with improved electrical specifications. Ideal for 3V or 5V single-supply applications, the TS9002 draws 11% lower supply current with a 25%-better initial accuracy reference voltage. The TS9002 joins the TS9001-1/2 analog comparators in the “NanoWatt Analog™” high performance analog integrated circuits portfolio. The TS9002 can operate from single +2.5V to +11V supplies or from ±1.25V to ±5.5V dual supplies. The TS9002 exhibits an input voltage range from the negative supply rail to within 1.3V of the positive supply rail. In addition, its push-pull output stage is TTL/CMOS compatible and capable of sinking and sourcing current. It also incorporates an internal 1.182V ±0.75% voltage reference. Without complicated feedback configurations and only requiring two additional resistors, adding external hysteresis via a separate pin is available on the TS9002’s HYST pin. The TS9002 is fully specified over the -40ºC to +85ºC temperature range and is available in an 8-pin MSOP package. TYPICAL APPLICATION CIRCUIT A 5V, Low-Parts-Count, High-Accuracy Window Detector Page 1 © 2014 Silicon Laboratories, Inc. All rights reserved. TS9002 ABSOLUTE MAXIMUM RATINGS Supply Voltage (V+ to V-, V+ to GND, GND to V-)......-0.3V, +12V Voltage Inputs (IN+, IN-)..............................................(V+ + 0.3V) to (V- - 0.3V) HYST…………………………………….(REF + 5V) to (V- - 0.3V) Output Voltage REF.....................................................(V+ + 0.3V) to (V- - 0.3V) OUT ....................................................(V+ + 0.3V) to (V- - 0.3V) Input Current (IN+, IN-, HYST)...............................................20mA Output Current REF…………………………………………………………….20mA OUT…………………………………………………………….40mA Output Short-Circuit Duration (V+ ≤ 5.5V) ...................Continuous Continuous Power Dissipation (TA = +70°C) 8-Pin MSOP (derate 4.1mW/°C above +70°C) ................330mW Operating Temperature Ranges..............................-40°C to +85°C Storage Temperature Range ................................-65°C to +150°C Lead Temperature (soldering, 10s) .....................................+300°C Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART CARRIER QUANTITY MARKING TS9002IM8 Tube 50 Tape & Reel 2500 TADG TS9002IM8T Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges. Page 2 TS9002 Rev. 1.0 TS9002 ELECTRICAL CHARACTERISTICS – 5V OPERATION V+ = 5V, V- = GND = 0V; TA = -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC. See Note 1. PARAMETER POWER REQUIREMENTS Supply Voltage Range CONDITIONS Supply Current IN+ = IN- + 100mV COMPARATOR Input Offset Voltage VCM = 2.5V Input Leakage Current (IN-, IN+) IN+ = IN- = 2.5V Input Leakage Current (HYST) Input Common-Mode Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Output Voltage Noise Hysteresis Input Voltage Range Response Time (High-to-Low Transition) Response Time (Low-to-High Transition) Output High Voltage Output Low Voltage REFERENCE TA = +25°C HYST = REF -40°C to +85°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C V- to (V+ – 1.3V) V+ = 2.5V to 11V 100Hz to 100kHz Overdrive = 10 mV TA = +25°C, 100pF load Overdrive = 100 mV Overdrive = 10 mV TA = +25°C, 100pF Load Overdrive = 100 mV -40°C to +85°C; IOUT = 17mA -40°C to +85°C; IOUT = 1.8mA Dual Supply -40°C to +85°C; IOUT = 1.8mA Reference Voltage Reference Line Regulation 2.5V ≤ (V+ - V-) ≤ 11V Source Current ΔVREF = 1% Sink Current ΔVREF = 1% Output Voltage Noise 100Hz to 100kHz TS9002 Rev. 1.0 MIN TA = +25°C -40°C to +85°C TA = +25°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C 2.5 V- REF- 0.05V V+ – 0.4 1.173 1.164 20 6 10 4 TYP MAX UNITS 2.6 11 4 5.2 V ±0.01 ±0.01 ±0.02 ±0.02 0.1 0.1 20 17 7 17 7 µA ±3.5 ±10 ±2 ±5 mV V+ – 1.3V 1 1 REF μs μs GND + 0.4 V- + 0.4 1.182 0.25 25 15 100 nA nA nA nA V mV/V mV/V μVRMS V 1.191 1.199 V V V V mV/V μA μA μVRMS Page 3 TS9002 ELECTRICAL CHARACTERISTICS – 3V OPERATION V+ = 3V, V- = GND = 0V; TA = -40ºC to +85ºC, unless otherwise noted. Typical values are at TA = +25ºC. See Note 1. PARAMETER POWER REQUIREMENTS CONDITIONS Supply Current IN+ = IN- + 100mV COMPARATOR Input Offset Voltage VCM = 1.5V Input Leakage Current (IN-, IN+) IN+ = IN- = 1.5V Input Leakage Current (at HYST Pin) Input Common-Mode Voltage Range Common-Mode Rejection Ratio Power-Supply Rejection Ratio Output Voltage Noise Hysteresis Input Voltage Range Response Time (High-to-Low Transition) Response Time (Low-to-High Transition) Output High Voltage Output Low Voltage REFERENCE HYST = REF TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C V- to (V+ – 1.3V) V+ = 2.5V to 11V 100Hz to 100kHz Overdrive = 10 mV TA = +25°C, 100pF load Overdrive = 100 mV Overdrive = 10 mV TA = +25°C, 100pF Load Overdrive = 100 mV -40°C to +85°C; IOUT = 10mA -40°C to +85°C; IOUT = 1.8mA Dual Supply -40°C to +85°C; IOUT = 1.8mA Reference Voltage Reference Line Regulation 2.5V ≤ (V+ - V-) ≤ 5V Source Current ΔVREF = 1% Sink Current MIN ΔVREF = 1% TA = +25°C -40°C to +85°C TA = +25°C TA = +25°C -40°C to +85°C TA = +25°C -40°C to +85°C V- REF- 0.05V V+ – 0.4 1.173 1.164 20 6 10 4 TYP MAX UNITS 2 3.8 5.3 µA ±0.01 ±0.01 ±0.02 ±0.02 0.1 0.1 20 17 7 17 7 ±3.5 ±10 ±2 ±5 V+ – 1.3V 1 1 REF 0.25 25 15 nA nA nA nA V mV/V mV/V μVRMS V μs μs GND + 0.4 V- + 0.4 1.182 mV 1.191 1.199 V V V V mV/V μA μA Output Voltage Noise 100Hz to 100kHz 100 μVRMS Note 1: All specifications are 100% tested at TA = +25°C. Specification limits over temperature (TA = TMIN to TMAX) are guaranteed by device characterization, not production tested. Page 4 TS9002 Rev. 1.0 TS9002 TYPICAL PERFORMANCE CHARACTERISTICS V+ = 5V; V- = GND; TA = +25°C, unless otherwise noted. Output Voltage Low vs Load Current 2.5 Output Voltage High vs Load Current 5 V+ = 5V V+ = 5V 4.5 2 1.5 V+ = 3V VOH - V VOL - V 4 1 3.5 3 2.5 0.5 0 V+ = 3V 2 0 4 8 12 16 20 24 1.5 28 0 LOAD CURRENT - mA V+ = 3V or 5V 1.175 1.170 SOURCE 1.160 0 5 10 15 20 25 1.20 1.19 1.18 1.17 1.16 1.15 1.14 30 -40 Supply Current vs Temperature 10 35 60 85 Hysteresis Control 80 4.5 60 4 OUTPUT HIGH 40 3.5 IN+ - IN- - mV SUPPLY CURRENT - µA -15 TEMPERATURE - ºC LOAD CURRENT - µA V+ = 5V, V- = 0V 3 V+ = 3V, V- = 0V 2.5 2 1.5 50 1.21 1.180 1.155 40 1.22 SINK 1.165 30 Reference Voltage vs Temperature REFERENCE VOLTAGE - V REFERENCE VOLTAGE - V 1.185 20 LOAD CURRENT - mA Reference Output Voltage vs Output Load Current 1.190 10 20 0 NO CHANGE -20 -40 OUTPUT LOW -60 -40 -15 10 35 TEMPERATURE - ºC TS9002 Rev. 1.0 60 85 -80 0 10 20 30 40 50 VREF - VHYST - mV Page 5 TS9002 TYPICAL PERFORMANCE CHARACTERISTICS Response Time For Various Input Overdrives (High-to-Low) 50mV 4 10mV 3 2 1 20mV 100mV 0 100 0 -2 0 2 4 6 V- = 0V 16 RESPONSE TIME - µs 5 Response Time vs Load Capacitance 18 14 12 VOHL 10 8 VOLH 6 4 2 8 10 12 14 16 18 0 20 40 60 80 RESPONSE TIME - µs LOAD CAPACITANCE - nF Response Time For Various Input Overdrives (Low-to-High) Short-Circuit Sink Current vs Supply Voltage 5 100mV 4 23 3 2 1 50mV 0 10mV 100 100 OUT CONNECTED TO V+ GND CONNECTED TO V- 20mV SINK CURRENT - mA INPUT VOLTAGE - mV OUTPUT VOLTAGE - V INPUT VOLTAGE - mV OUTPUT VOLTAGE - V V+ = 5V; V- = GND; TA = +25°C, unless otherwise noted. 22 21 0 -2 0 2 4 6 20 8 10 12 14 16 18 20 2.5 RESPONSE TIME - µs 4.5 6.5 8.5 10 TOTAL SUPPLY VOLTAGE - V Short-Circuit Source Current vs Supply Voltage 200 SOURCE CURRENT - mA 180 160 140 OUT CONNECTED TO V- 120 100 80 60 2.5 3 3.5 4 4.5 5 5.5 TOTAL SUPPLY VOLTAGE - V Page 6 TS9002 Rev. 1.0 TS9002 PIN FUNCTIONS TS9002 MSOP-8 1 2 3 4 NAME OUTA VINA+ INB- 5 HYST 6 7 8 REF V+ OUTB FUNCTION Comparator A Output. Sinks and sources current. Swings from V+ to V-. Negative Supply Voltage. Connect to ground for single-supply operation. Comparator A Noninverting Input Comparator B Inverting Input Hysteresis Input. Connect to REF if not used. Input voltage range is from VREF to (VREF - 50mV). 1.182V Reference Output with respect to V-. Positive Supply Voltage Comparator B Output. Sinks and sources current. Swings from V+ to V-. BLOCK DIAGRAM THEORY OF OPERATION The TS9002 dual, low-voltage, micropower analog comparator provides excellent flexibility and performance while sourcing continuously up to 40mA of current. The TS9002 draws less than 5.5µA (total) over temperature for both comparators, including the reference. It also exhibits an input offset voltage of ±3.5mV, and has an on-board +1.182V ±0.75% voltage reference. To minimize glitches that can occur with parasitic feedback or a less than optimal board layout, the design of the TS9002 output stage is optimized to eliminate crowbar glitches as the output switches. To minimize current consumption while providing flexibility, TS9002 has an on-board HYST pin in order to add additional hysteresis. TS9002 Rev. 1.0 Power-Supply and Input Signal Ranges The TS9002 can operate from a single supply voltage range of +2.5V to +11V, provides a wide common mode input voltage range of V- to V+-1.3V, and accepts input signals ranging from V- to V+ - 1V. The inputs can accept an input as much as 300mV above and below the power supply rails without damage to the part. The TS9002 is TTL compatible with a single +5V supply. Comparator Output The output design of the TS9002 can source and sink more than 40mA and 5mA, respectively, while simultaneously maintaining a quiescent current less Page 7 TS9002 than 3µA. If the power dissipation of the package is maintained within the max limit, the output can source pulses of 100mA of current with V+ set to +5V. In an effort to minimize external components needed to address power supply feedback, the TS9002 output does not produce crowbar switching current as the output switches. At a power supply voltage of 3V, the propagation delay of the TS9002 is 6μs when the output switches from high-to-low and low-to-high. Voltage Reference The TS9002 has an on-board +1.182V voltage reference with an accuracy of ±0.75%. The REF pin is able to source and sink 20μA and 10μA of current, APPLICATIONS INFORMATION Hysteresis As a result of circuit noise or unintended parasitic feedback, many analog comparators often break into oscillation within their linear region of operation especially when the applied differential input voltage approaches 0V (zero volt). Externally-introduced hysteresis is a well-established technique to stabilizing analog comparator behavior and requires external components. As shown in Figure 1, adding comparator hysteresis creates two trip points: VTHR (for the rising input voltage) and VTHF (for the falling input voltage). The hysteresis band (VHB) is defined as the voltage difference between the two trip points. When a comparator’s input voltages are equal, hysteresis effectively forces one comparator input to move quickly past the other input, moving the input out of the region where oscillation occurs. Figure 1 illustrates the case in which an IN- input is a fixed Figure 1. Threshold Hysteresis Band Page 8 respectively. The REF pin is referenced to V- and it should not be bypassed. Noise Considerations Noise can play a role in the overall performance of the TS9002. Despite having a large gain, if the input voltage is near or equal to the input offset voltage, the output will randomly switch HIGH and LOW. As a result, the TS9002 produces a peak-to-peak noise of about 0.3mVPP while the reference voltage produces a peak-to-peak noise of about 1mvPP. Furthermore, it is important to design a layout that minimizes capacitive coupling from a given output to the reference pin as crosstalk can add noise and as a result, degrade performance. voltage and an IN+ is varied. If the input signals were reversed, the figure would be the same with an inverted output. Hysteresis can be generated with two external resistors using positive feedback as shown in Figure 2. Resistor R1 is connected between REF and HYST and R2 is connected between HYST and V-. This will increase the trip Figure 2. Programming the HYST Pin point for the rising input voltage, VTHR, and decrease the trip point for the falling input voltage, VTHF, by the same amount. If no hysteresis is required, connect HYST to REF. The hysteresis band, VHB, is voltage across the REF and HYST pin multiplied by a factor of 2. The HYST pin can accept a voltage between REF and REF-50mV, where a voltage of REF-50mV generates the maximum voltage across R1 and thus, the maximum hysteresis and hysteresis band of 50mV and 100mV, respectively. To design the circuit for a desired hysteresis band, consider the equations below to acquire the values for resistors R1 and R2: TS9002 Rev. 1.0 TS9002 1. As described below, determine the desired hysteresis and select resistors R4 and R5 accordingly. This circuit has ±5mV of hysteresis at the input where the input voltage VIN will appear larger due to the input resistor divider. VHB R1 = (2 x IREF ) R2 = 1.182 IREF VHB 2 where IREF is the primary source of current out of the reference pin and should be maintained within the maximum current the reference can source. It is safe to maintain the current within 20µA. It is also important to ensure that the current from reference is much larger than the HYST pin input current. Given R2 = 2.4MΩ, the current sourced by the reference is 0.5μA. This allows the hysteresis band and R1 to be approximated as follows: R1(kΩ) = VHB(mv) Note the hysteresis comparators. Figure 3. Window Detector is the same for both Board Layout and Bypassing While power-supply bypass capacitors are not typically required, it is good engineering practice to use 0.1μF bypass capacitors close to the device’s power supply pins when the power supply impedance is high, the power supply leads are long, or there is excessive noise on the power supply traces. To reduce stray capacitance, it is also good engineering practice to make signal trace lengths as short as possible. Also recommended are a ground plane and surface mount resistors and capacitors. 2. Choosing R1. As the leakage current at the INB- pin is less than 1nA, the current through R1 should be at least 100nA to minimize offset voltage errors caused by the input leakage current. Values within 100kΩ and 1MΩ are recommended. In this example, a 294kΩ, 1% standard value resistor is selected for R1. 3. Calculating R2 + R3. As the input voltage VIN rises, the overvoltage threshold should be 5.5V. Choose R2 + R3 as follows: R1 + R3 = R1 x ( Window Detector The schematic shown in Figure 3 is for a 4.5V undervoltage threshold detector and a 5.5V overvoltage threshold detector using the TS9002. Resistor components R1, R2, and R3 can be selected based on the threshold voltage desired while resistors R4 and R5 can be selected based on the hysteresis desired. Adding hysteresis to the circuit will minimize chattering on the output when the input voltage is close to the trip point. OUTA and OUTB generate the active low undervoltage indication and active-low overvoltage indication, respectively. If both OUTA and OUTB signals are ANDed together, the resulting output of the AND gate is an active-high, power-good signal. To design the circuit, the following procedure needs to be followed: TS9002 Rev. 1.0 = 294kΩ x ( VOTH - 1) VREF +VHYS 5.5V - 1) 1.182V + 5mV = 1.068MΩ 4. Calculating R2. As the input voltage VIN falls, the undervoltage threshold should be 4.5V. Choose R2 as follows: R2 = (R1 + R2+ R3) x = (294kΩ + 1.068MΩ) x (VREF -VHYS ) - 294k VUTH (1.182V-5mV) - 294k 4.5 = 62.2kΩ Page 9 TS9002 In this example, a 61.9kΩ, 1% standard value resistor is selected for R2. = 5.474V VOTH = (VREF - VHYS ) x 5. Calculating R3. R3 = (R2 + R3) - R2 = 1.068MΩ – 61.9kΩ (R1 + R2 + R3) (R1+R2) = 4.484V Where the hysteresis voltage is given by: = 1.006MΩ In this example, a 1MΩ, 1% standard value resistor is selected for R3. VHYS = VREF x R5 R4 6. Using the equations below, verify all resistor values selected: VOTH = (VREF + VHYS ) x Page 10 (R1 + R2 + R3) R1 TS9002 Rev. 1.0 TS9002 PACKAGE OUTLINE DRAWING 8-Pin MSOP Package Outline Drawing (N.B., Drawings are not to scale) 3.10 Max 2.90 Min 0.38 Max 0.28 Min 0.65 REF 8 0.23 Max 0.13 Min 0.127 0.27 REF 3.10 Max 2.90 Min 5.08 Max 4.67 Min GAUGE PLANE 0' -- 6' 1 2 0.70 Max 0.40 Min 0.25 0.38 Max 0.28 Min DETAIL “A” DETAIL ‘A’ 0.95 Max 0.75 Min 1.10 Max SEATING PLANE 0.10 Max 0.15 Max 0.05 Min 0.23 max 0.13 Min NOTE: 1. PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 2. PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTUSIONS. 3. CONTROLLING DIMENSION IN MILIMETERS. 4. THIS PART IS COMPLIANT WITH JEDEC MO-187 VARIATIONS AA 5. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. Silicon Laboratories, Inc. 400 West Cesar Chavez, Austin, TX 78701 +1 (512) 416-8500 ▪ www.silabs.com Page 11 TS9002 Rev. 1.0