Si53321 1 : 1 0 L OW J I T T E R LVPECL C LOCK B U F F E R W I T H 2:1 I NPUT M UX (< 1.25 GH Z ) Features 10 LVPECL outputs Ultra-low additive jitter: 45 fs rms typ Wide frequency range: dc to 1.25 GHz Input compatible with LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 input mux Low output-output skew: 25 ps (typ) RoHS compliant, Pb-free 32-QFN, 32-eLQFP Industrial temperature range: –40 to +85°C Footprint-compatible with MC100LVEP111, CDCLVP111, MAX9311, ICS853S111BI, ICS85310-1 Applications 31 30 29 28 VDD Q0 32 Q2 VDD 27 26 25 VDD 1 24 Q3 CLK_SEL 2 23 Q3 CLK0 3 CLK0 4 Exposed GND Pad 22 Q4 21 Q4 20 Q5 NC 5 CLK1 6 19 Q5 CLK1 7 18 Q6 GND 8 17 Q6 VDD 9 10 11 12 13 14 15 16 VDD Functional Block Diagram Q7 The Si53321 is an ultra-low jitter ten output differential buffer. The Si53321 features a 2:1 input mux, making it ideal for redundant clocking applications. The Si53321 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53321 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Q0 Description Q2 Pin Assignments (Top View) Q7 Q1 Q1 Ordering Information: See page 19. Q8 Storage Telecom Industrial Servers Backplane clock distribution Q8 Q9 High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 Q9 Q1 Q1 Q2 Q2 VDD 25 24 Q3 2 23 Q3 CLK0 3 22 Q4 CLK0 4 NC 5 CLK1 6 19 Q5 CLK1 7 18 Q6 GND 8 Q4 Exposed GND Pad 21 Q4 20 Q5 Q5 Q8 11 12 13 14 15 Q7 16 VDD 10 Q7 Q7 17 Q6 9 Q8 Q6 Q7 Q8 GND 26 CLK_SEL Q6 CLK_SEL 27 Q8 CLK1 28 Q2 Q4 Q5 1 29 Q9 CLK1 30 1 Q9 0 31 VDD Q3 CLK0 32 Q1 Q2 Q3 CLK0 Q0 Q1 VDD VDD Q0 Q0 Power Supply Filtering VDD Q0 Patents pending Q9 Q9 Rev. 1.0 4/15 Copyright © 2015 by Silicon Laboratories Si53321 Si53321 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3. Input Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.4. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.5. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.7. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.8. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. Pin Description: 32-eLQFP, 32-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1. 32-eLQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2. 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.1. 32-eLQFP Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2. 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 7.1. Si53321 32-eLQFP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2. Top Marking Explanation (32-eLQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3. Si53321 32-QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4. Top Marking Explanation (32-QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2 Rev. 1.0 Si53321 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Operating Temperature Test Condition TA Supply Voltage Range LVPECL VDD Min Typ Max Unit –40 — 85 °C 2.38 2.5 2.63 V 2.97 3.3 3.63 V Table 2. Input Clock Specifications (2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V 5%, 3.3 V 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V 5%, 3.3 V 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V 5%, 3.3 V 10% — — VDD x 0.3 V Input Capacitance CIN CLK0 and CLK1 pins with respect to GND — 5 — pF Table 3. DC Common Characteristics (2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Symbol Test Condition Min Typ Max Unit Supply Current IDD Measured using accoupled termination shown in Figure 6 — 440 — mA Input High Voltage VIH CLK_SEL 0.8 x VDD — — V Input Low Voltage VIL CLK_SEL — — 0.2 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL — 25 — k Parameter Rev. 1.0 3 Si53321 Table 4. Output Characteristics (LVPECL) (VDD = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Min Typ Max Unit VCOM VDD – 1.595 — VDD – 1.245 V VSE 0.40 0.80 1.050 V Single-Ended Output Swing* Test Condition *Note: Unused outputs can be left floating. Do not short unused outputs to ground. Table 5. AC Characteristics (VDD = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit dc — 1250 MHz Frequency F Duty Cycle DC 20/80% TR/TF<10% of period (Differential input clock) 47 50 53 % DC 20/80% TR/TF<10% of period (Single-Ended input clock) 45 50 55 % Minimum Input Clock Slew Rate SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF 20–80% — — 350 ps Minimum Input Pulse Width TW 360 — — ps TPLH, TPHL 600 800 1000 ps Output to Output Skew1 TSK — 25 60 ps Part to Part Skew2 TPS Differential — — 150 ps PSRR 10 kHz sinusoidal noise — –65 — dBc 100 kHz sinusoidal noise — –62.5 — dBc 500 kHz sinusoidal noise — –60 — dBc 1 MHz sinusoidal noise — –55 — dBc Note: 50% input duty cycle. Duty Cycle Note: 50% input duty cycle. Propagation Delay Power Supply Noise Rejection3 Notes: 1. Output-to-output skew specified for outputs with identical configuration. 2. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 3. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDD (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 4 Rev. 1.0 Si53321 Table 6. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Differential Clock Format 20%-80% Slew Rate (V/ns) Amplitude VIN (Single-Ended, Peak-to-Peak) Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. Table 7. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. PSPL 5310A CLK SYNTH SMA103A 50 Si533xx DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm 50 /CLKx Balun Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 5 Si53321 Table 8. Thermal Conditions Parameter Symbol Test Condition Value Unit 32-eLQFP Thermal Resistance, Junction to Ambient JA Still air 54.9 °C/W 32-eLQFP Thermal Resistance, Junction to Case JC Still air 10.0 °C/W 32-QFN Thermal Resistance, Junction to Ambient JA Still air 99.6 °C/W 32-QFN Thermal Resistance, Junction to Case JC Still air 10.3 °C/W Table 9. Absolute Maximum Ratings Parameter Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM 2000 — — V ESD Sensitivity CDM 500 — — V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Storage Temperature Maximum Junction Temperature Symbol Test Condition HBM, 100 pF, 1.5 kΩ Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 6 Rev. 1.0 Si53321 2. Functional Description The Si53321 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The selected clock input is routed to ten high-performance, low-jitter outputs. 2.1. Universal, Any-Format Input The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, lowpower LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 10 and 11 summarize the various ac- and dc-coupling options supported by the device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. Table 10. LVPECL, LVCMOS, and LVDS Input Clock Options LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 11. HCSL and CML Input Clock Options HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes (3.3 V) Yes (3.3 V) Yes No 0.1 µF Si533xx CLKx 100 /CLKx 0.1 µF Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input Termination VDD 1 k VDD = 3.3 V or 2.5 V VDD Si533xx CMOS Driver CLKx 50 /CLKx Rs VTERM = VDD/2 1 k VREF Figure 3. LVCMOS DC-Coupled Input Termination Rev. 1.0 7 Si53321 VDD DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDD = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 VTERM = VDD – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDD = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDD – 2V DC Coupled LVDS Termination VDD VDD = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Source Termination Scheme VDD = 3.3V 33 Si533xx 50 Standard HCSL Driver VDD CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 4. Differential DC-Coupled Input Terminations 8 Rev. 1.0 Si53321 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting input is biased with a 18.75 k pull-down to GND and a 75 k pull-up to VDD. The inverting input is biased with a 75 k pull-up to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 k RPD = 18.75 k Figure 5. Input Bias Resistors 2.3. Input Mux The Si53321 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 12. Input Mux Logic CLK_SEL CLK0 CLK1 Q1 Q L L X L H L H X H L H X L L H H X H H L Notes: 1. On the next negative transition of CLK0 or CLK1. Rev. 1.0 9 Si53321 2.4. Output Clock Termination Options The recommended output clock termination options are shown below. Unused outputs should be left unconnected. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si533xx R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 V DDO = 3.3V or 2.5V Si533xx 0.1 uF V DD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb 50 Rb 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 6. LVPECL Output Termination 10 Rev. 1.0 Si53321 2.5. AC Timing Waveforms TPHL TSK CLK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 7. AC Waveforms Rev. 1.0 11 Si53321 2.6. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 5. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 8. Source Jitter (156.25 MHz) 12 Rev. 1.0 Si53321 Figure 9. Single-Ended Total Jitter (312.5 MHz) Rev. 1.0 13 Si53321 Figure 10. Differential Total Jitter (625 MHz) 14 Rev. 1.0 Si53321 2.7. Input Mux Noise Isolation The input clock mux is designed to minimize crosstalk between the CLK0 and CLK1. This improves phase jitter performance when clocks are present at both the CLK0 and CLK1 inputs. Figure 11 below is a measurement the input mux’s noise isolation. LVPECL [email protected]; Selected clk is active Unselected clk is static Mux Isolation = 61dB LVPECL [email protected]; Selected clk is static Unselected clk is active Figure 11. Input Mux Noise Isolation 2.8. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks”. Rev. 1.0 15 Si53321 VDD Q0 Q0 Q1 Q1 Q2 Q2 VDD 3. Pin Description: 32-eLQFP, 32-QFN 32 31 30 29 28 27 26 25 VDD 1 24 Q3 CLK_SEL 2 23 Q3 CLK0 3 22 Q4 CLK0 4 21 Q4 NC 5 20 Q5 CLK1 6 19 Q5 CLK1 7 18 Q6 GND 8 17 Q6 13 Q8 Q8 14 15 16 VDD 12 Q7 11 Q7 10 Q9 VDD 9 Q9 Exposed GND Pad VDD Q0 Q0 Q1 Q1 Q2 Q2 VDD Figure 12. 32-eLQFP Pin Diagram (Top View) 32 31 30 29 28 27 26 25 VDD 1 24 Q3 CLK_SEL 2 23 Q3 CLK0 3 22 Q4 CLK0 4 NC 5 CLK1 6 19 Q5 CLK1 7 18 Q6 GND 8 17 Q6 Exposed GND Pad 21 Q4 9 10 11 12 13 14 15 16 VDD Q9 Q9 Q8 Q8 Q7 Q7 VDD 20 Q5 Figure 13. 32-QFN Pin Diagram (Top View) 16 Rev. 1.0 Si53321 Table 13. Si53321 32-eLQFP and 32-QFN Pin Descriptions Pin # Name Type* Description 1 VDD P Core voltage supply. Bypass with 1.0 F capacitor and place as close to the VDD pin as possible. 2 CLK_SEL I Mux input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. 3 CLK0 I Input clock 0. 4 CLK0 I Input clock 0 (complement) When CLK0 is driven by a single-ended input, connect CLK0 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). 5 NC 6 CLK1 I Input clock 1. 7 CLK1 I Input clock 1 (complement) When CLK1 is driven by a single-ended input, connect CLK1 to an appropriate bias voltage (e.g., for a CMOS input apply VDD/2). 8 GND GND 9 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. 10 Q9 O Output clock 9 (complement). 11 Q9 O Output clock 9. 12 Q8 O Output clock 8 (complement). 13 Q8 O Output clock 8. 14 Q7 O Output clock 7 (complement). 15 Q7 O Output clock 7. 16 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. 17 Q6 O Output clock 6 (complement). 18 Q6 O Output clock 6. 19 Q5 O Output clock 5 (complement). 20 Q5 O Output clock 5. 21 Q4 O Output clock 4 (complement). 22 Q4 O Output clock 4. 23 Q3 O Output clock 3 (complement). No connect. Leave this pin unconnected. Ground. Rev. 1.0 17 Si53321 Table 13. Si53321 32-eLQFP and 32-QFN Pin Descriptions (Continued) Pin # Name Type* Description 24 Q3 O Output clock 3. 25 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. 26 Q2 O Output clock 2 (complement). 27 Q2 O Output clock 2. 28 Q1 O Output clock 1 (complement). 29 Q1 O Output clock 1. 30 Q0 O Output clock 0 (complement). 31 Q0 O Output clock 0. 32 VDD P Core voltage supply. Bypass with 1.0 µF capacitor and place as close to the VDD pin as possible. GND Pad Exposed ground pad GND Ground Pad - Power supply ground and thermal relief. The exposed ground pad is thermally connected to the die to improve the heat transfer out of the package. The ground pad must be connected to GND to ensure device specifications are met. *Pin types are: I = input, O = output, P = power, GND = ground. 18 Rev. 1.0 Si53321 4. Ordering Guide Part Number Package PB-Free, ROHS-6 Temperature Si53321-B-GQ 32-eLQFP Yes –40 to 85 C SI53321-B-GM 32-QFN Yes –40 to 85 C Rev. 1.0 19 Si53321 5. Package Outline 5.1. 32-eLQFP Package Diagram Figure 14. Si53321 32-eLQFP Package Diagram Table 14. Package Dimensions Dimension Min Nom Max Dimension Min Nom A — — 1.60 E1 A1 0.05 — 0.15 E2 1.87 1.92 1.97 A2 1.35 1.40 1.45 L 0.45 0.60 0.75 b 0.30 0.37 0.45 0 3.5 7 c 0.09 — 0.20 aaa 0.20 7.00 BSC D 9.00 BSC bbb 0.20 D1 7.00 BSC ccc 0.10 ddd 0.20 eee 0.05 D2 1.87 1.92 e 0.80 BSC E 9.00 BSC 1.97 Max Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC MS-026. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 20 Rev. 1.0 Si53321 5.2. 32-QFN Package Diagram Figure 15. Si53321 32-QFN Package Diagram Table 15. Package Dimensions MIN NOM MAX A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 c 0.20 0.25 0.30 Dimension D D2 5.00 BSC 2.00 2.15 e 0.50 BSC E 5.00 BSC 2.30 E2 2.00 2.15 2.30 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC Solid State Outline MO-220. Rev. 1.0 21 Si53321 6. PCB Land Pattern 6.1. 32-eLQFP Package Land Pattern Figure 16. Si53321 32-eLQFP Package Land Pattern Table 16. PCB Land Pattern Dimension Min Max C1 8.40 8.50 C2 8.40 8.50 D1 1.84 2.00 D2 1.84 2.00 E 0.80 BSC X1 0.40 0.50 Y1 1.25 1.35 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A single 1.5 x 1.5 mm stencil aperture should be used for the center ground pad to achieve between 50-60% solder coverage. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 22 Rev. 1.0 Si53321 6.2. 32-QFN Package Land Pattern Figure 17. Si53321 32-QFN Package Land Pattern Rev. 1.0 23 Si53321 Table 17. PCB Land Pattern Dimension Min Max Dimension Min Max C1 4.52 4.62 X2 2.20 2.30 C2 4.52 4.62 Y1 0.59 0.69 Y2 2.20 2.30 E X1 0.50 BSC 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 0.75 mm square openings on 1.15 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 24 Rev. 1.0 Si53321 7. Top Markings 7.1. Si53321 32-eLQFP Top Marking 7.2. Top Marking Explanation (32-eLQFP) Mark Method: Laser Font Size: 1.9 Point (26 mils) Right-Justified Line 1 Marking: Device Part Number 53321-B-GQ Line 2 Marking: YY = Year WW = Work Week Corresponds to the year and work week of the mold date. TTTTTT = Mfg Code Line 3 Marking: Circle = 1.3 mm Diameter Center-Justified Country of Origin ISO Code Abbreviation Rev. 1.0 Manufacturing Code from the Assembly Purchase Order form. “e3” Pb-Free Symbol TW 25 Si53321 7.3. Si53321 32-QFN Top Marking 7.4. Top Marking Explanation (32-QFN) 26 Mark Method: Laser Font Size: 2.0 Point (28 mils) Center-Justified Line 1 Marking: Device Part Number 53321 Line 2 Marking: Device Revision/Type B-GM Line 3 Marking: TTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase Order form. Line 4 Marking Circle = 0.50 mm Diameter Lower-Left Justified Pin 1 Identifier YY = Year WW = Work Week Corresponds to the year and work week of the mold date. Rev. 1.0 Si53321 DOCUMENT CHANGE LIST Revision 0.4 to 1.0 Update operating conditions, including LVCMOS and HCSL voltage support. Removed voltage reference feature. Updated Table 2, “Input Clock Specifications,” on page 3. Updated Table 3, “DC Common Characteristics,” on page 5. Updated Table 4, “Output Characteristics (LVPECL),” on page 6. Updated Table 10, “AC Characteristics,” on page 7. Updated output voltage specifications Improved data for additive jitter specifications. Improved typical phase noise plots. Updated input/output termination recommendations. Improved performance specifications with more detail. Added pin type description to the pin descriptions table Rev. 1.0 27 Si53321 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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