Si30xxPPT-EVB - Silicon Labs

S i 3 0 x x P P T- E V B
EVALUATION BOARD
Si30XX
FOR THE
Description
Features
The Si30xxPPT-EVB provides the telecommunications
system engineer an easy way to evaluate the
functionality of Silicon Laboratories’ Si30xx (Si3034,
Si3035, Si3044, Si3056/18, and Si3056/19) integrated
voice direct access arrangement (DAA) solution. The
digital side of the chipset (Si3021 or Si3056) has a DSP
serial interface as well as system-side DAA
functionality. In conjunction with the Si3012/14/15 or
Si3018/19 global line-side silicon DAA chip, it provides
a low-cost, solid-state, globally-compliant voice DAA
solution. The Si30xx chipset can be easily controlled
from a PC using the supplied application software
(requires software Rev 2.0 or above and FPGA Rev 2.0
or above).
!
Ability to read and write DAA registers
DAC waveform generation from a series of standard
waveforms or from a .wav file
! ADC data capture and display in either time or
frequency domain
! Recommended layout for key components
! Daisy-chain support
!
Functional Block Diagram
Motherboard
Daughter Card
FPGA
PPT
Preliminary Rev. 1.0 1/03
SSI
DSP side
DAA
Copyright © 2003 by Silicon Laboratories
Line Side
DAA
BOM
TIP
RING
Si30xxPPT-EVB-10
Si30xxPPT-EVB
Functional Description
clock to the DAA. The FPGA is designed to use a
18.432 MHz oscillator (included with the board).
The Si30xxPPT-EVB provides the telecommunications
system engineer an easy way to evaluate the Si30xx
solution. Silicon Labs’ DAAs are integrated direct
access arrangements that provide a digital, low-cost,
solid-state interface to worldwide telephone lines.
Through the patented ISOcap technology, the Si30xx
eliminates the need for an analog frond end (AFE), an
isolation transformer, relays, opto-isolators, and a 2 to
4-wire hybrid.
The Si30xxPPT-EVB also supports the connection of
multiple devices on an SSI interface. The evaluation
board provides a straightforward means of evaluating
this feature.
The evaluation board consists of the Si30xxPPT-EVB
Si-LINK (mother) board and the Si30xxDC_EVB
daughter card. A custom ribbon cable is also provided
to connect to the parallel port of a PC. Contact a Silicon
Laboratories representative for more information.
Motherboard-Daughter Card Connection
The Si30xxDC-EVB connects to the Si30xxPPT-EVB
through two sockets: JP1 and JP2. JP1 is a 3x8 socket
connection to the digital signals of the DSP-side chip, as
well as to the analog AOUT pin. In addition, a 3.3 V
regulated supply is routed to this socket and supplies
the power to the digital-side device. JP1 of the daughter
card connects to JP2 of the Si30xxPPT-EVB. JP2 is a
2x5 socket connection from the TIP and RING and
chassis ground of the line interface to the line-side
device. JP2 of the Si30xx DC-EVB connects to JP1 of
the Si30xx PPT EVB.
Power Supply
Power is supplied to the EVB by means of J3 or J4. J3
is a euroblock header that allows for connection to a
bench power supply. J4 is a 2.1 mm power jack that
allows the use of a wall transformer. A 9 V supply/
300 mA is typically used, but the onboard voltage
regulator also works with a dc voltage between 7.5 V
and 20 V. A diode bridge is used to correct polarity. The
on-board regulator, U7, provides 5 V to the call progress
circuit, the on-board oscillator, and other boards daisy
chained to the Si30xxPPT-EVB. This 5 V is further
regulated to 3.3 V to power the daughter card and the
input/output ports of the FPGA. A third regulator
provides 2.5 V for the core voltage of the FPGA.
Optional Call Progress Speaker
The AOUT pin of the digital-side device provides a call
monitoring feature. U3 provides 25 dB of signal gain on
this output. The AOUT pin has an output impedance of
10 kW. R9 and R10 form a voltage divider that provides
a gain of –24.4 dB. This divider is necessary so the
LM386, which is operating from a +5 V supply, is not
overdriven. The LM386 is a cost-effective low-power
amplifier capable of driving many different buzzers or
speakers. In the case of cascaded evaluation boards,
the AOUT signal is local to each board.
Reset Circuit
The Si30xx requires an active low pulse on RESET
following powerup and whenever all registers need to
be reset. For development purposes, the Si30xxPPTEVB includes a reset push button, SW1, that is used by
the FPGA to generate a reset pulse of the DAA.
If multiple boards are cascaded together, the reset
signal should be generated by the master board. Using
the SW1 pushbutton on slave boards does not reset
that slave board.
Serial Modes
The Si30xx supports several different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si30xx can be
selected by JP3 and JP4.
Line Connection
J1 is provided to connect the EVB to a standard RJ-11
connector. The system cannot execute an off-hook
command without the phone line connected. This
condition can be detected by examining the FDT bit of
register 12 or by simply observing that there is no dial
tone on the DSP or ASIC.
PC Parallel Port
JP13 connects through the Silicon Labs custom ribbon
cable to the parallel port of the PC. The parallel port
connection allows the designer to read and write the
DAA register using the evaluation software included
with the Si30xxPPT-EVB.
Clock Generation
The Si30xx requires an MCLK input. An on-board
oscillator (Y1) is used by the FPGA to clock all the
subsystems as well as generate and provide the master
2
Preliminary Rev. 1.0
Si30xxPPT-EVB
Configuring the Si30xxPPT-EVB
The S30xxPPT-EVB is used to interface the Si30xx
chipset to a PC or other audio system for easy
evaluation. It uses an FPGA to translate the parallel port
interface to the SSI bus to communicate to the Si30xx.
The audio data and control data are communicated from
the controlling PC using the aforementioned software.
This mode allows the user to evaluate the DAA without
any lab equipment other than a PC.
When in mode 0, the negative edge of FSYNC indicates
the starting of the frame, and FSYNC is low until the end
of data transfer. By selecting mode 1 operation, the
rising edge of FSYNC indicates the start of the frame,
but is only high for one cycle. To evaluate the Si30xx’s
multiple device operation, chain the slave boards with
JP3 and JP4 set to mode 2. See Table 1 for a
description of these operating modes.
The Si30xxPPT-EVB has the ability to interface in two
different modes of the SSI bus: 5-bit address space
operation is used for the Si3034/35/44, and 7-bit
address space operation is used for the Si3056. Table 2
shows how to configure the Si30xxPPT-EVB to operate
in a desired SSI operational mode.
Table 2. SSI Operational Mode Configuration
Mode
Sel0
Description
5-bit Addr
0
For Si3021 digital side
7-bit Addr
1
For Si3056 digital side
Table 1. Mode Configuration
Mode M1 M2
Description
0
0
0
FSYNC frames data
1
0
1
FSYNC pulse starts data frame
2
1
0
Slave mode
3
1
1
Reserved
Preliminary Rev. 1.0
3
Si30xxPPT-EVB
Evaluation Software
!
The Si30xxPPT-EVB includes an easy-to-use graphical
interface for controlling the evaluation platform. This
software allows the system designer to characterize the
Si30xx DAA performance without constructing any
custom hardware. The evaluation software includes the
following features:
!
!
!
!
!
!
!
Ability to read and write DAA registers using the SSI
bus
DAC waveform generation from a series of standard
waveforms or from a .wav file
ADC data capture and display in either time or
frequency domain using the SSI bus
Daisy-chain support
Transmit and receive path attenuation and gain
settings
Ring detection
Loop current measurement
Run:
"
"
!
Exit: Stops the program
Save: Stores the audio waveform into .wav files
Configure:
" Configure DAA: Display hardware status and user
configuration. User can set advanced software options.
" Reset DAA: Resets DAA and executes basic
initialization sequences on Reg 1, Reg 6–10, and Reg 14.
!
Design Tool
Register Map: Displays Register Map of Si30xx
Signal Flow Diagram: Displays Signal Flow Diagram of
Si30xx.
" Transhybrid Loss Calculation: Calculate transhybrid loss
over frequency
" Ringing: Helps user program ring validation registers.
"
"
!
Help: Displays information about the evaluation
board
PC System Requirements
The application software for the Si30xxPPT-EVB has
the following system requirements:
!
Windows98 or Windows2000
! Available parallel port
"
"
EPP or ECP parallel port mode for Windows 98
EPP parallel port mode for Windows 2000
!
450 MHz Pentium II or greater recommended
! 64 MB of memory or greater recommended
Installation
The supplied CD contains the Si30xxPPT-EVB windows
driver files as well as a setup utility for installing the
evaluation software.
To install the Si30xxPPT-EVB software, run the
installation program on the “Silicon Laboratories
Wireline Software CD.” The path for the installation
program is Si30xx Evaluation Software\setup.exe. The
installer guides the user through the installation process
for Si30xxPPT-EVB.exe and the LabVIEW Run-Time
engine.
Using the Si30xxPPT-EVB
Application Software
A shortcut for starting the application software that
controls the Si30xxPPT-EVB is installed in the Windows
Start Menu under the Programs folder in the “Si30xx
Evaluation Software” folder.
Application Menus
Three pulldown menus are used to configure the
operation of the software:
4
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 1. Si30xxPPT-EVB Evaluation Software in the Audio Data Monitoring View
Audio Data Monitoring View
!
The audio data monitoring view is discussed in the
following sections.
Receive Audio Data of Channel#
Allows selection of channel to control and view. The
Audio Data Monitoring view allows the generation of
DAC data and the capture and display of ADC data.
Operation of the front panel in Line Monitoring view is
detailed in the following list. See Figure 1.
TX Control
!
DAC Waveform: Selects the waveform to be
generated by the DAC. The waveform types are as
follows: dc, Sine, Square, Ramp, and .wav file.
! TX Gain (dB): Selects the transmit path gain/
attenuation.
! TX Mute: Mutes the transmit path.
Sampling Rate: Sets the sampling rate of the DAA
and performs writes to corresponding registers.
! Amplitude: Sets the amplitude of the DAC
waveform in either volts or the units of DAC codes.
The units are determined by the Amplitude Units
control.
! Frequency: Selects the frequency (Hz) of the
waveform to generate. The actual waveform
frequency may vary slightly from the entered value.
This variation is due to the requirement to fit an
integer number of samples into the transmit buffer.
The control is updated to reflect the actual waveform
frequency generated. The equation for calculating
the frequency of the waveform is as follows:
Actual Frequency = round ((Waveform Frequency/DAC
Sample Rate) x BufferSize) x (DAC Sample Rate/
BufferSize)
Preliminary Rev. 1.0
5
Si30xxPPT-EVB
!
RX Control
!
Monitor Mode: Allows the selection of several data
modes. Digital Loopback mode routes the DAC data
back to the receive path. On-hook mode configures
the DAA to the on-hook mode. Off-hook mode
configures the DAA to the off-hook mode. On-hook
line monitoring mode configures the DAA to the line
monitoring state.
! RX Gain/Attn (dB): Selects the receive path gain/
attenuation.
! RX Mute: Mutes the receive path
! Ring Detect Mode: Allows selection of full-wave or
half-wave ring detection.
Wave Display Controls
!
!
!
Dialer
!
!
Dial Number: Inputs dial number.
Dial: Executes dial.
!
Measurement
!
!
!
!
!
6
!
Loop Current: Displays the loop current when in offhook mode.
Ring Detect Bits: Displays the state of the ring
detect bits when in on-hook mode.
Off-Hook: Indicates that the DAA is in the off-hook
state.
DC Level/SINAD: Displays either the dc level of the
time domain waveform or the SINAD of the
frequency domain waveform.
RMS Level/Frequency: Displays either the RMS
level of the time domain waveform or the frequency
of the largest peak in the frequency domain
waveform.
Num Avg for FFT: When in FFT display, the
software automatically averages waveforms. This
panel selects the number of averages to take.
!
!
!
Display Type: Selects how the ADC data is
displayed on the Waveform Graph (time or
frequency domain).
Amplitude Units: Sets the amplitude units for the
Waveform Graph and Amplitude control to either
volts or codes.
Acquisition: Used to run or pause the CODEC data
stream. Upon pausing the acquisition of the data, it
displays measurement values regardless of the
status of “display measurement” under the configure
menu.
X Autoscale: Automatically scales the X-axis of the
graph to fit the entire waveform.
Y Autoscale: Automatically scales the Y-axis to fit
the entire vertical range of the waveform.
Xmin: Sets the origin of the X-axis when the X
Autoscale is disabled.
X Zoom: Used to zoom a portion of the displayed
waveform when X Autoscale is disabled. The
waveform starts at Xmin and 1/X Zoom of the total
waveform is displayed.
Yo: Sets the origin of the Y-axis when Y Autoscale is
disabled. Half of the waveform is displayed above
Yo, and half is displayed below Yo.
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 2. Si3056 System-Side Device Signal Flow Diagram
Preliminary Rev. 1.0
7
Si30xxPPT-EVB
Figure 3. Si3021 System-Side Device Signal Flow Diagram
Register Table Display View
The DAA Register view allows the Si30xx DAA registers
to be read or written. The user interface for the DAA
Register view is shown in Figure 2 for the Si3056 and
Figure 3 for the Si3021. Operation of the front panel in
the DAA Register view is detailed in the following list:
!
!
!
!
!
!
8
Si3019.
! Off-Hook: Shows the status of the off-hook bit, DAA
Register 5, bit 1.
! DCE: Shows the status of the daisy chain enable bit,
DAA Register 14, bit 0.
Table: This table displays the contents of the Si30xx
DAA registers in realtime.
DAA Reg Num: The Si30xx DAA register number to
write (in decimal).
DAA Reg Value: The contents to write to the register
selected by the DAA Reg Num control (in
hexadecimal).
Write DAA Regs: Causes the contents of the DAA
Reg Value control to be written to the DAA Reg Num
register.
Broadcast: Turns on the broadcast bit (SPI only).
FDT: Shows the status of the FDT bit, which
indicates that the Si30xx is communicating with the
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 4. Configure DAA Panel
Advanced Configuration
Advanced configuration of the application software is
accomplished by using the “Configure DAA” selection in
the “Configure” menu. The configuration panel is shown
in Figure 4. The panel contents are detailed in the
following list:
!
FFT Window: The FFT window applied to the time
domain data before calculating the FFT.
! Acquisition Buffer Size: This is the size of the
buffer, in samples, that is acquired and displayed on
the Line Monitoring mode waveform graph. The
buffer size can be set between 1024 and 65536
samples in increments of 512 samples.
! Display Measurement: Takes realtime
measurements of audio waveform.
Preliminary Rev. 1.0
9
Si30xxPPT-EVB
Figure 5. Si30xx Signal Flow Diagram for the Si3056
Signal Flow Diagrams
!
The signal flow diagrams of the Si30xx application
software for the Si3056 device, shown in Figure 5 and
Figure 6, assist users with programming DAA.
ATM: Writes to ATM on Register 21.
! INTE: Turns on/off INTE bit on Register 2, bit 7.
! INTP: Turns on/off INTP bit on Register 2, bit 6.
! AOUT: Writes to PWMM and PWEM on Register 1.
Si30xx Signal Path Control
!
!
!
!
!
!
!
!
10
TX Mute: Turns on/off the TXM bit on DAA Register
15, bit 7.
TX Gain: Writes to ATX on DAA Register 15 or
TGA2, TXG2, TGA3, and TXG3 on DAA Register 38
and 40.
IIRE: Turns on/off IIRE bit on Register 16, bit 4.
DDL: Turns on/off DDL bit on Register 10, bit 1.
RX Mute: Turns on/off RXM bit on Register 15, bit 0.
RX Gain: Writes to ARX on DAA Register 15 or
RGA2, RXG2, RGA3, and RXG3 on DAA Register
39 and 41.
FILT: Turns on/off FILT bit on Register 31, bit 1 (Bit is
available for Si3019 line-side device only).
ARM: Writes to ARM on Register 20.
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 6. Si30xx Signal Flow Diagram for Si3021
Signal Flow Diagrams
The signal flow diagrams of the application software
shown in Figure 6 assist users with programming DAA.
Si30xx Signal Path Control
!
!
!
!
!
!
!
!
TX Mute: Turns on/off the TXM bit on DAA Register
15, bit 7.
TX Gain: Writes to TGA2, TXG2, TGA3, and TXG3
on DAA Register 38 and 40.
IIRE: Turns on/off IIRE bit on Register 16, bit 4.
RX Mute: Turns on/off RXM bit on Register 15, bit 0.
RX Gain: Writes to RGA2, RXG2, RGA3, and RXG3
on DAA Register 39 and 41.
ARM: Writes to ARM on Register 20.
ATM: Writes to ATM on Register 21.
AOUT: Writes to PWMM and PWEM on Register 1
Si3019 Signal Path Control.
Preliminary Rev. 1.0
11
Si30xxPPT-EVB
Figure 7. Si3018/19 Line-side Device Signal Flow Diagram
Line-Side Device Signal Path Control
!
AL: Turns on/off AL bit on Register 2, bit 3.
! HBE: Turns on/off HBE bit on Register 2, bit 1.
! RXE: Turns on/off RXE bit on Register 2, bit 0.
! IDL: Turns on/off IDL bit on Register 1, bit 1.
12
Preliminary Rev. 1.0
Si30xxPPT-EVB
Figure 8. Si3012/14/15 Line Side Device Signal Flow Diagram
Line-Side Device Signal Path Control
!
!
!
!
!
!
AL: Turns on/off AL bit on Register 2, bit 3.
HBE: Turns on/off HBE bit on Register 2, bit 1.
RXE: Turns on/off RXE bit on Register 2, bit 0.
IDL/DL: Turns on/off IDL/DL bit on Register 1, bit 1.
PDL: Turns on/off PDL bit on Register 6, bit 4.
FULL: Turns on/off FULL bit on Register 31, bit 7.
Preliminary Rev. 1.0
13
Si30xxPPT-EVB
Figure 9. Transhybrid Loss
Transhybrid Loss Calculation
When “Transhybrid Loss Calculation” is selected, the
Si3050PPT-EVB software will drive a signal with
different frequencies and measure the transhybrid loss
based on the following equation: TL = 20Log(TXpk-pk/
RXpk-pk). Frequencies used to measure this start
from100 Hz to 4000 Hz in 20 Hz steps.
14
Preliminary Rev. 1.0
Si30xxPPT-EVB
Ringing
!
!
!
!
!
!
!
!
!
!
!
RNGV-Enable: Turns on/off RNGV bit on Register
24, bit7
RAS[5:0]: Update RAS bits on Register 24
RMX[5:0]: Update RMX bits on Register 22
RCC[2:0]: Update RCC bits on Register 23
RTO[3:0]: Update RTO bits on Register 23
RDLY[2:0]: Update RDLY bits on Register 22 & 23
Fmin(Hz): Calculate fmin based on RAS bits
Fmin(Hz): Calculate fmax based on RAS bits and
RMX bits
Ring confirmation count (ms): Shows ring
confirmation count based on RCC bits
Ring timeout(ms): Displays ring timeout based on
RTO bits
Ring delay(ms): displays ring delay based on RDLY
bits
Figure 10. Ringing
Preliminary Rev. 1.0
15
Si30xxPPT-EVB
16
VCC
No Ground Plane In DAA Section
C50
Q1
Decou pling cap for
U 1 VA
R10
C51
R3
R11
Q4
R5
+
M0
RGDTb
OFHKb
MCLK
FSYNCb
SCLK
SDO
SDI
FC
RESETb
Q2
R1
R2
C4
R4
C10
Q5
1
2
3
4
5
6
7
8
MCLK
OFHK
FSYNC
RGDT/FSD/M1
SCLK
M0
VD
VA
SDO
GND
SDI
AOUT/INT
FC/RGDT
C1A
RESET
C2A
U1
16
15
14
13
12
11
10
9
U2
C1
R12
1
2
3
4
5
6
7
8
C2
R13
Si3056
C5
QE
DCT2
DCT
IGND
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG VREG2
RNG1 RNG2
R6
16
15
14
13
12
11
10
9
Q3
Si3018/19
C6
R14
AOUT
R9
C7
Z1
C3
R8
Preliminary Rev. 1.0
RING
FB2
R33
R16
R32
C9
C31
Optional CID Enhancement
D1
-
RV1
+
C30
C8
R31
R30
R7
TIP
FB1
Figure 11. Si3034/35/44 Daughter Card Schematic (1 of 2)
R15
JP1
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
21
22
23
24
Preliminary Rev. 1.0
Footprint of JP1
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
M0
RGDTb
OFHKb
MCLK
SCLK
FSYNCb
VCC
JP2
SDO
FC
SDI
TIP
R50
1
3
5
7
9
2
4
6
8
10
RING
HEADER 5X2
RESETb
M1
AOUT
CON24
Figure 12. Si3034/35/44 Daughter Card Schematic (2 of 2)
Si30xxPPT-EVB
17
Si30xxPPT-EVB
Bill of Materials: Si3034-EVB Daughter Card
Quantity Reference
18
Part
2
C4,C1
1
C3
150 pF, 3 kV, ±20%, 1812, , C1808X7R302-151MNE, Venkel
0.22 uF, 25 V, ±20%, 0805, , C0805X7R250-224MNE, Venkel
1
C5
0.1 uF, 50 V, ±20%, Case A, , TA050TCM104-MAL, Venkel
3
C6,C10,C16
0.1 uF, 16 V, ±10%, 0603, , C0603X7R160-104KNE, Venkel
2
C7,C8
560 pF, 250 V, ±10%, 0805, , C0805X7R251-561KNE, Venkel
1
C9
10 nF, 250 V, ±20%, 0805, , C0805X7R251-103KNE, Venkel
4
R4,C11,R21,C30
NI, , , 0603, , ,
1
C12
0.22 uF, 35 V, ±10%, Case A, , TA035TCM224-KAL, Venkel
1
C13
0.47 uF, 25 V, ±10%, 0805, , C0805X7R250-474KNE, Venkel
1
C14
0.68 uF, 16 V, ±10%, 1206, , 1206YC684KATMA, AVX
2
C18,C19
3.9 nF, 16 V, ±10%, 0603, , C0603X7R160-392KNE, Venkel
1
C20
0.01 uF, 16 V, ±20%, 0603, , C0603X7R160-103KNE, Venkel
1
C22
1800 pF, 50 V, ±10%, 0603, , C0603X7R500-182KNE, Venkel
1
C23
NI, , , Case A, , ,
2
C24,C25
1000 pF, 3 kV, ±10%, 1812, , C1808X7R302-102KNE, Venkel
4
R22,R23,C28,C29
NI, , , 0805, , ,
2
D1,D2
Dual Diode, 225 mA, 300 V, SOT-23, , CMPD2004S, Central Semiconductor
2
D3,D4
BAV99, 300 mA, 100 V, SOT-23, , BAV99, Diodes Inc.
2
FB1,FB2
Ferrite Bead, , , 1206, , BLM31A601S, Murata
1
JP1
CON24, , , 8x3 100 mil, , SSW-108-01-T-T,
1
JP2
HEADER 5X2, , , 5x2 100 mil, , SSW-105-01-T-D,
2
L2,L1
330 uH, 150 mA, , Thru Hole, , EL0607-331J, TDK
2
Q3,Q1
NPN, 300 V, , SOT-23, , MMBTA42LT1, Motorola
1
Q2
PNP, 300 V, , SOT-23, , MMBTA92LT1, Motorola
1
Q4
NPN, 80 V, , SOT-223, , BCP56T1, Motorola
1
RV1
SiDactor, 275 V, 100 A, SOD 6, , P3100SB, Teccor
1
RV2
NI, , , Thru-Hole, , ,
1
R1
NI, , , 2010, , ,
1
R2
402, 1/8 W, ±1%, 1206, , CR1206-8W-4020FT, Venkel
1
R3
NI, , , 0805, , , Venkel
1
R5
36 K, 1/16 W, ±5%, 0603, , CR0603-16W-363JT, Venkel
1
R6
120 K, 1/16 W, ±5%, 0603, , CR0603-16W-124JT, Venkel
6
R7,R8,R15,R16,R17,R19
4.87 K, 1/4 W, ±1%, 1206, , CR1206-4W-4871FT, Venkel
2
R10,R9
56 K, 1/10 W, ±5%, 0805, , CR0805-10W-563JT, Venkel
1
R11
10 K, 1/10 W, ±1%, 0603, , CR0603-16W-1002FT, Venkel
1
R12
78.7, 1/16 W, ±1%, 0603, , CR0603-16W-78R7FT, Venkel
1
R13
215, 1/16 W, ±1%, 0603, , CR0603-16W-2150FT, Venkel
1
R18
2.2 K, 1/10 W, ±5%, 0805, , CR0805-10W-222JT, Venkel
1
R24
150, 1/10 W, ±5%, 0603, , CR0603-10W-150JT, Venkel
2
R25,R26
NI, , , 0805, , ,
2
R28,R27
10, 1/10 W, ±5%, RC05, , CR0805-10W-100JT, Venkel
1
R29
NI, , , 0603, , ,
1
R30
0, 1/10 W, ±5%, 0603, , CR0603-10W-000JT, Venkel
1
U1
Si3021, , , 16SOIC, , Si3021-KS Rev. C, Silicon Labs
1
U2
Si301x, , , 16SOIC, , Si3014-KS Rev. C, Silicon Labs
1
Z1
Zener Diode, 43 V, , SOD-80, , ZMM43, General Semi
2
Z4,Z5
Zener Diode, 5.6 V, 500 mW, SOD123, , MMSZ5232B, Diodes Inc.
Preliminary Rev. 1.0
Si30xxPPT-EVB
Bill of Materials: Si3035-EVB Daughter Card
Quantity Reference
Part
2
C4,C1
1
C3
150 pF, 3 kV, ±20%, 1812, , C1808X7R302-151MNE, Venkel
0.22 uF, 25 V, ±20%, 0805, , C0805X7R250-224MNE, Venkel
1
C5
1.0 uF, 16 V, ±20%, Case A, , TA016TCM105-MAL, Venkel
3
C6,C10,C16
0.1 uF, 16 V, ±10%, 0603, , C0603X7R160-104KNE, Venkel
6
R3,C7,C8,C13,R25,R26
NI, , , 0805, , ,
3
C9,C28,C29
15 nF, 250 V, ±20%, 0805, , C0805X7R251-153KNE, Venkel
1
C11
39 nF, 16 V, ±10%, 0603, , C0603X7R160-393KNE, Venkel
1
C12
NI, , , Case A, , ,
7
R7,R8,C14,R15,R16,R17,
NI, , , 1206, , ,
R19
9
R12,R13,C18,C19,C20,C22,
NI, , , 0603, , ,
R24,R30,C30
1
C23
NI, 35V, ±10%, Case A, , TA035TCM105-KAL, Venkel
2
C24,C25
1000 pF, 3 kV, ±10%, 1812, , C1808X7R302-102KNE, Venkel
2
D1,D2
Dual Diode, 225 mA, 300 V, SOT-23, , CMPD2004S, Central Semiconductor
2
D3,D4
BAV99, 300 mA, 100 V, SOT-23, , BAV99, Diodes Inc.
2
FB1,FB2
Ferrite Bead, , , 1206, , BLM31A601S, MuRata
1
JP1
CON24, , , 8x3 100 mil, , SSW-108-01-T-T,
1
JP2
HEADER 5X2, , , 5x2 100 mil, , SSW-105-01-T-D,
2
L2,L1
0 ohm,, , Thru Hole, , Wire Jumper
2
Q3,Q1
NPN, 300 V, , SOT-23, , MMBTA42LT1, Motorola
1
Q2
PNP, 300 V, , SOT-23, , MMBTA92LT1, Motorola
1
Q4
NI, , , SOT-223, , ,
1
RV1
SiDactor, 275 V, 100 A, SOD 6, , P3100SB, Teccor
1
RV2
MOV, 240 V, 1250 A, Thru-Hole, , ERZ-V07D241, Panasonic
1
R1
51, 1/2 W, ±5%, 2010, , C2010-2W-510JT, Venkel
1
R2
15, 1/4 W, ±5%, 1206, , CR1206-4W-150JT, Venkel
2
R4,R21
301, 1/16 W, ±1%, 0603, , CR0603-16W-3010FT, Venkel
2
R6,R5
36 K, 1/16 W, ±5%, 0603, , CR0603-16W-363JT, Venkel
2
R10,R9
2 K, 1/10 W, ±5%, 0805, , CR0805-10W-202JT, Venkel
1
R11
NI, 16 V, ±10%, 0603, , C0603X7R160-272KNE, Venkel
1
R18
300, 1/10 W, ±5%, 0805, , CR0805-10W-301JT, Venkel
2
R23,R22
20 K, 1/10 W, ±5%, 0805, , CR0805-10W-203JT, Venkel
2
R28,R27
10, 1/10 W, ±5%, RC05, , CR0805-10W-100JT, Venkel
1
R29
0, 1/10 W, ±5%, 0603, , CR0603-10W-000JT, Venkel
1
U1
Si3021, , , 16SOIC, , Si3021-KS Rev. C, Silicon Labs
1
U2
Si3012/5, , , 16SOIC, , Si3012-KS Rev. G, Silicon Labs
1
Z1
Zener Diode, 18 V, , SOD-80, , ZMM18, General Semi
2
Z4,Z5
Zener Diode, 5.6 V, 500 mW, SOD123, , MMSZ5232B, General Semi
Preliminary Rev. 1.0
19
Si30xxPPT-EVB
Bill of Materials: Si3044-EVB Daughter Card
Quantity Reference
20
Part
2
C4,C1
150 pF, 3 kV, ±20%, 1812, , C1808X7R302-151MNE, Venkel
1
C3
0.22 uF, 25 V, ±20%, 0805, , C0805X7R250-224MNE, Venkel
1
C5
0.1 uF, 50 V, ±20%, Case A, , TA050TCM104-MAL, Venkel
3
C6,C10,C16
0.1 uF, 16 V, ±10%, 0603, , C0603X7R160-104KNE, Venkel
2
C7,C8
560 pF, 250 V, ±10%, 0805, , C0805X7R251-561KNE, Venkel
1
C9
10 nF, 250 V, ±20%, 0805, , C0805X7R251-103KNE, Venkel
4
R4,C11,R21,C30
NI, , , 0603, , ,
1
C12
1.0 uF, 35 V, ±10%, Case A, , TA035TCM105-KAL, Venkel
1
C13
0.22 uF, 25 V, ±10%, 0805, , C0805X7R250-224KNE, Venkel
1
C14
0.68 uF, 16 V, ±10%, 1206, , 1206YC684KATMA, AVX
2
C18,C19
3.9 nF, 16 V, ±10%, 0603, , C0603X7R160-392KNE, Venkel
1
C20
0.01 uF, 16 V, ±20%, 0603, , C0603X7R160-103KNE, Venkel
1
C22
1800 pF, 50 V, ±10%, 0603, , C0603X7R500-182KNE, Venkel
1
C23
NI, , , Case A, , ,
2
C24,C25
1000 pF, 3 kV, ±10%, 1812, , C1808X7R302-102KNE, Venkel
4
R22,R23,C28,C29
NI, , , 0805, , ,
2
D1,D2
Dual Diode, 225 mA, 300 V, SOT-23, , CMPD2004S, Central Semiconductor
2
D3,D4
BAV99, 300 mA, 100 V, SOT-23, , BAV99, Diodes Inc.
2
FB1,FB2
Ferrite Bead, , , 1206, , BLM31A601S, Murata
1
JP1
CON24, , , 8x3 100 mil, , SSW-108-01-T-T,
1
JP2
HEADER 5X2, , , 5x2 100 mil, , SSW-105-01-T-D,
2
L2,L1
330 uH, 150 mA, , Thru Hole, , EL0607-331J, TDK
2
Q3,Q1
NPN, 300 V, , SOT-23, , MMBTA42LT1, Motorola
1
Q2
PNP, 300 V, , SOT-23, , MMBTA92LT1, Motorola
1
Q4
NPN, 80 V, , SOT-223, , BCP56T1, Motorola
1
RV1
SiDactor, 275 V, 100 A, SOD 6, , P3100SB, Teccor
1
RV2
NI, , , Thru-Hole, , ,
1
R1
NI, , , 2010, , ,
1
R2
402, 1/8 W, ±1%, 1206, , CR1206-8W-4020FT, Venkel
1
R3
NI, , , 0805, , , Venkel
1
R5
100 K, 1/16 W, ±1%, 0603, , CR0603-16W-104FT, Venkel
1
R6
120 K, 1/16 W, ±5%, 0603, , CR0603-16W-124JT, Venkel
6
R7,R8,R15,R16,R17,R19
5.36 K, 1/4 W, ±1%, 1206, , CR1206-4W-5361FT, Venkel
2
R10,R9
56 K, 1/10 W, ±5%, 0805, , CR0805-10W-563JT, Venkel
1
R11
9.31 K, 1/10 W, ±1%, 0603, , CR0603-16W-9311FT, Venkel
1
R12
78.7, 1/16 W, ±1%, 0603, , CR0603-16W-78R7FT, Venkel
1
R13
215, 1/16 W, ±1%, 0603, , CR0603-16W-2150FT, Venkel
1
R18
2.2 K, 1/10 W, ±5%, 0805, , CR0805-10W-222JT, Venkel
1
R24
150, 1/10 W, ±5%, 0603, , CR0603-10W-150JT, Venkel
2
R25,R26
10 M, 1/10 W, ±5%, 0805, , CR0805-10W-106JT, Venkel
2
R28,R27
10, 1/10 W, ±5%, RC05, , CR0805-10W-100JT, Venkel
1
R29
NI, , , 0603, , ,
1
R30
0, 1/10 W, ±5%, 0603, , CR0603-10W-000JT, Venkel
1
U1
Si3021, , , 16SOIC, , Si3021-KS Rev. C, Silicon Labs
1
U2
Si301x, , , 16SOIC, , Si3015-KS Rev. D, Silicon Labs
1
Z1
Zener Diode, 43 V, , SOD-80, , ZMM43, General Semi
2
Z4,Z5
Zener Diode, 5.6 V, 500 mW, SOD123, , MMSZ5232B, Diodes Inc.
Preliminary Rev. 1.0
Preliminary Rev. 1.0
21
Si30xxPPT-EVB
Figure 1. Si3034/35/44 Daughter Card Silkscreen
Si30xxPPT-EVB
22
Preliminary Rev. 1.0
Figure 2. Si3034/35/44 Daughter Card Component Layer
Preliminary Rev. 1.0
23
Si30xxPPT-EVB
Figure 3. Si3034/35/44 Daughter Card Solder Layer
Si30xxPPT-EVB
24
VCC
No Ground Plane In DAA Section
C50
Q1
Decou pling cap for
U 1 VA
R10
C51
R3
R11
Q4
R5
+
M0
RGDTb
OFHKb
MCLK
FSYNCb
SCLK
SDO
SDI
FC
RESETb
Q2
R1
R2
C4
R4
C10
Q5
1
2
3
4
5
6
7
8
MCLK
OFHK
FSYNC
RGDT/FSD/M1
SCLK
M0
VD
VA
SDO
GND
SDI
AOUT/INT
FC/RGDT
C1A
RESET
C2A
U1
16
15
14
13
12
11
10
9
U2
C1
R12
1
2
3
4
5
6
7
8
C2
R13
Si3056
C5
QE
DCT2
DCT
IGND
RX
DCT3
IB
QB
C1B
QE2
C2B
SC
VREG VREG2
RNG1 RNG2
R6
16
15
14
13
12
11
10
9
Q3
Si3018/19
C6
R14
AOUT
R9
C7
Z1
C3
R8
Preliminary Rev. 1.0
RING
FB2
R33
R16
R32
C9
C31
Optional CID Enhancement
D1
-
RV1
+
C30
C8
R31
R30
R7
TIP
FB1
Figure 13. Si3056 Daughter Card Schematic (1 of 2)
R15
JP1
2
3
4
5
6
7
8
9
1
10 11
12
13
14
15
16
17
18
19
20
21
22
23
24
Preliminary Rev. 1.0
Footprint of JP1
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
M0
RGDTb
OFHKb
MCLK
SCLK
FSYNCb
VCC
JP2
SDO
FC
SDI
TIP
R50
1
3
5
7
9
2
4
6
8
10
RING
HEADER 5X2
RESETb
M1
AOUT
CON24
Figure 14. Si3056 Daughter Card Schematic (2 of 2)
Si30xxPPT-EVB
25
Si30xxPPT-EVB
Bill of Materials: Si3056-EVB Daughter Card
Reference
Value
Tolerance
Rating
Part Number
Manufacturer
PCB Footprint
C2,C1
33 pF
±20%
Y2
ECCAVS330KGS
Panasonic
Thru-hole
C3
10 nF
±20%
250 V
C0805X7R251-103MNE
Venkel
805
C4
1.0 uF
±20%
50 V
ECE-V1HS010SR
Panasonic
Size A
C6,C5
0.1 uF
±20%
16 V
C0603X7R160-104MNE
Venkel
603
C7
2.7 nF
±20%
50 V
C0603X7R500-272MNE
Venkel
603
C9,C8
680 pF
±10%
Y2
ECKATS681KBS
Panasonic
Thru-hole
C10
0.01 uF
±20%
16 V
C0603X7R160-103MNE
Venkel
603
C30,C31
DNP 120pF
±20%
250 V
C0805X7R251-121MNE
Venkel
805
C51,C50
0.1 uF
±20%
D1
HD04
FB1,FB2
Ferrite Bead
JP1
CON24
JP2
HEADER 5X2
16 V
C0805X7R160-104MNE
Venkel
805
400 V
HD04-T
Diodes, Inc.
Mini-DIP
BLM21A601S
MuRata
805
SSW-108-02-G-T
Samtec
3x8 100 mil
SSW-105-01-T-D
Samtec
5x2 100 mil
Q3,Q1
NPN
300 V
MMBTA42LT1
Motorola
SOT-23
Q2
PNP
300 V
MMBTA92LT1
Motorola
SOT-23
Q4,Q5
NPN
80 V
MMBTA06LT1
Motorola
SOT-23
RV1
SiDactor
100 A
275 V
P3100SB
Teccor
SOD 6
R1
1.07 K
±1%
1/2 W
CR1210-2W-1071FT
Venkel
1210
R2
150
±5%
1/16 W
CR0402-16W-150JT
Venkel
402
R3
3.65 K
±1%
1/2 W
CR1210-2W-3651FT
Venkel
1210
R4
2.49 K
±1%
1/2 W
CR1210-2W-2491FT
Venkel
1210
R6,R5
100 K
±5%
1/16 W
CR0402-16W-104JT
Venkel
402
R8,R7
20 M
±1%
1/8 W
CR0805-8W-2005FT
Venkel
805
R9
1M
±1%
1/16 W
CR0402-16W-1004FT
Venkel
402
R10
536
±1%
1/4 W
CR1206-4W-5360FT
Venkel
1206
R11
73.2
±1%
1/2 W
CR1210-2W-73R2FT
Venkel
1210
R12,R13,R14
0
±1%
1/16 W
CR0603-16W-000F
Venkel
603
R16,R15
0
±1%
1/16 W
CR0805-16W-000F
Venkel
805
R32,R30
DNP 15M
±5%
1/8 W
CR0805-8W-156JT
Venkel
805
R31,R33
DNP 5.1M
±5%
1/8 W
CR0805-8W-515JT
Venkel
805
R50
47 K
±5%
1/16 W
CR0603-16W-473JT
Venkel
603
U1
Si3056
Si3056-KS Rev C
Silicon Labs
16SOIC
U2
Si3018/19
Si3018-KS Rev C
Silicon Labs
16SOIC
Z1
43 V
ZMM43
General Semi
SOD-80
26
1/2 W
Preliminary Rev. 1.0
Preliminary Rev. 1.0
27
Si30xxPPT-EVB
Figure 15. Si3056 Daughter Card Silkscreen
Si30xxPPT-EVB
28
Preliminary Rev. 1.0
Figure 16. Si3056 Daughter Card Component Layer
Preliminary Rev. 1.0
29
Si30xxPPT-EVB
Figure 17. Si3056 Daughter Card Solder Layer
3
Footprint of JP7
Top View
C5
0.1 uF
SDO
FC/RGDT
SDI
C6
0.1 uF
M1
AOUT
C3
10uF
C8
0.1 uF
C13
0.1 uF
C9
10uF
C14
0.1 uF
GND25
JP3
JP4
M0
VA
Vio
Vcore
J4
2.1 mm Power jack
U1
JP6
D2
U7
R13
1
IN
OUT
3
GND
1.6
+
C17
470 uF
C30
.33uF
7805
2
Preliminary Rev. 1.0
Power Connector
D4
C10
10uF
C15
0.1 uF
C11
10uF
C16
0.1 uF
R1
2.2K
M1
D3
C7
0.1 uF
C4
10uF
Vio
Vio
D1
C2
10uF
FPGA VCCIO Bypass Caps
R4
2.2K
1
2
C1
10uF
RESETb
CON24
J3
VCC127
24
GND129
23
Vio
VCC134
22
RJ-11
HEADER 5X2
MCLK
SCLK
FSYNCb
1
GND RESET/PG
8
2
EN
FB/NC
7
3
IN(1)
OUT(1)
6
4
IN(2)
OUT(2)
5
FB1
U2
R5
196k
1
IN
2
GND
3
EN
OUT
5
NC/FB
4
TPS77601DR
C18
.1uF
R6
110k
C21
10uF
C22
.1uF
TPS76325DBVR
Figure 18. Si30xx Motherboard Schematic (1 of 3)
C19
4.7uF
C20
10uF
GND139
21
VCC85
18
20
GND84
17
19
RGDT/FSD
OFHKb
VCC94
16
M0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
FPGA VCCINT Bypass Caps
1
2
3
4
5
6
2
4
6
8
10
GND93
15
1
3
5
7
9
VCC50
12
14
J1
JP1
GND52
10 11
13
R3
2.2K
JP2
VCC61
9
GND66
6
8
VCC16
5
7
GND15
4
R2
2.2K
VCC24
2
C12
10uF
Si30xxPPT-EVB
30
Vio
1
VA
Vio
C23
0.1 uF
pbRESETb
C24
SW1
R9
AOUT
100
0.1 uF
C27
1uF
47 k
C26
R10
3k
3
7
2
820 pF
TP1
C25
+
5
-
100 uF
U3
1
C28
2
R8
+
20 k
6
1
R7
4
8
D5
0.1 uF
LM386M-1
J5
RCA JACK
TP2
R11
10
Preliminary Rev. 1.0
8
11
OSC
VA
JP7
1
3
5
7
9
SCLK
SDO
RESETb
FSD_OUT
2
4
6
8
10
VA
Y1
R12
To Slave
14
4
7
51
SDI
C29
0.1 uF
OSC
Place PC Recepticle for Oscillator Pins
Mouser Part #575-066700 .038" Diameter
HEADER 5X2
Vio
VA
JP8
SCLK_IN
1
3
5
7
9
RESET_INb
2
4
6
8
10
FSYNC_INb
SDI_IN
HEADER 5X2
R53
10K
From
Master
R54
10K
R55
10K
Figure 19. Si30xx Motherboard Schematic (2 of 3)
31
Si30xxPPT-EVB
R52
2.2K
Vio
GND
GND
Vio
Vio
GND
GND
Vio
Slave
GND
Vio
JP10
Vio
Vio
Vio
mSel0
Vio
R56
1K
R39
1K
R40
1K
R41
10K
JP14
R42
10K
R43
10K
R44
10K
Vio
1
3
5
7
9
TCK
TDO
TMS
TDI
2
4
6
8
10
OSC
TCK
TMS
Vio
R47
1K
Vio
R48
1K
R49
1K
R50
1K
U5
DCLK
DATA
OE
nCS
nCASC
2
1
3
4
6
EPC1PC8
R57
0K
Install R57 only if
U8 is not populated
Vio
VA
Vio
U8
1
2
3
4
5
6
7
8
9
10
TDO
VCC
DATA
TMS
TCK
VPP
DCLK
NC5
VCCSEL
NC4
NC1
NC3
NC2
VPPSEL
OE nINIT_CONF
nCS
nCASC
GND
TDI
20
19
18
17
16
15
14
13
12
11
C32
0.1 uF
VCC134
VCC94
68
69
70
72
73
78
79
80
nDSTB
nWRITE
s3
D0
c2
D1
nASTB
D2
109
110
111
112
113
114
116
DATA(1)
DATA(2)
DATA(3)
DATA(4)
DATA(5)
DATA(6)
DATA(7)
81
82
83
86
87
88
89
90
D3
D4
D5
D6
D7
nIRQ
nWAIT
s5
54
56
124
126
I/O(49)
I/O(50)
I/O(51)
I/O(52)
I/O(53)
I/O(54)
I/O(55)
I/O(56)
INPUT(1)
INPUT(2)
INPUT(3)
INPUT(4)
CLK(1)
CLK(2)
TCK
CLKUSR
91
92
95
96
97
98
99
100
s4
55
125
1
7
I/O(57)
I/O(58)
I/O(59)
I/O(60)
I/O(61)
I/O(62)
I/O(63)
I/O(64)
I/O(65)
I/O(66)
I/O(67)
I/O(68)
I/O(69)
I/O(70)
I/O(71)
I/O(72)
101
102
117
118
119
120
121
130
I/O(73)
I/O(74)
I/O(75)
I/O(76)
I/O(77)
I/O(78)
I/O(79)
I/O(80)
131
132
133
135
136
137
138
140
VCCIO(1)
VCCIO(2)
VCCIO(3)
VCCIO(4)
VCCIO(5)
VCCIO(6)
VCCIO(7)
VCCIO(8)
I/O(41)
I/O(42)
I/O(43)
I/O(44)
I/O(45)
I/O(46)
I/O(47)
I/O(48)
U4
105
34
141
142
144
106
TDI
TMS
NRS
NWS
NCS
NCE
122
128
DEV_CLRn
DEV_OE
77
76
143
MSEL0
MSEL1
CS
107
108
35
2
74
DCLK
DATA0
NSTATUS
CONF_DONE
NCONFIG
R15
47K
R16
47K
R17
47K
R18
47K
R19
47K
R20
47K
R21
47K
R22
47K
R23
47K
R24
47K
R27
47K
R28
47K
R29
47K
R30
47K
R31
47K
R32
47K
R33
47K
R34
47K
R35
47K
R36
47K
R37
47K
5
24
45
61
71
94
115
134
I/O(17)
I/O(18)
I/O(19)
I/O(20)
I/O(21)
I/O(22)
I/O(23)
I/O(24)
6
15
25
40
52
58
Use Socket for EPC1441_3.
Mill-Max 110-99-308-41-001
m OH
mRGDT
m FC
GNDINT(1)
GNDINT(2)
GNDINT(3)
GNDINT(4)
GNDINT(5)
GNDINT(6)
GND
C31
0.1 uF
VCC
VCC
8
7
CFG Dev Select
5
Preliminary Rev. 1.0
HEADER 5X2
Master Blaster Header
R51
1K
51
59
60
62
63
64
65
67
39
38
37
36
33
32
31
30
modeSel0
modeSel1
mSel1
I/O(33)
I/O(34)
I/O(35)
I/O(36)
I/O(37)
I/O(38)
I/O(39)
I/O(40)
20
21
22
23
26
27
28
29
M0
M1
Vio
I/O(9)
I/O(10)
I/O(11)
I/O(12)
I/O(13)
I/O(14)
I/O(15)
I/O(16)
RESETb
SCLK_IN
FSD_OUT
pbRESETb
RESET_INb
FSYNC_INb
SDI_IN
GND
JP9
mFS
mSCLK
mRST
m C1A
mS DI
m SDO
mM0
mM1
I/O(1)
I/O(2)
I/O(3)
I/O(4)
I/O(5)
I/O(6)
I/O(7)
I/O(8)
NCEO
TDO
INIT_DONE
RDYNBUSY
3
4
14
11
R25
47K
R26
47K
R38
47K
JP11
Test Point Connector
JP12
1
3
5
7
9
2
4
6
8
10
HEADER 5X2
TDO
EP1K30TC144
GND129
GND139
GND
41
42
43
44
46
47
48
49
8
9
10
12
13
17
18
19
GNDINT(7)
GNDINT(8)
GNDINT(9)
GNDINT(10)
GNDINT(11)
GNDINT(12)
GNDINT(13)
Stand Alone
Master w/ slaves
I/O(25)
I/O(26)
I/O(27)
I/O(28)
I/O(29)
I/O(30)
I/O(31)
I/O(32)
RGDT/FSD
OFHKb
MCLK
SCLK
FSYNCb
SDO
FC/RGDT
SDI
66
84
93
104
123
129
139
M0
GND66
GND84
GND93
M1
VCCINT(1)
VCCINT(2)
VCCINT(3)
VCCINT(4)
VCCINT(5)
VCCINT(6)
mSel1
GND52
mSel0
GND15
GND25
Board Config.
VCC61
VCC24
VCC127
VCC85
16
50
75
85
103
127
VCC16
VCC50
Vio
R14
47K
TDI
EPC2LC20
Use Socket for EPC2LC20.
Mill-Max 540-99-020-400000
Figure 20. Si30xx Motherboard Schematic (3 of 3)
mFS
mRST
DG ND
mS DI
mM0
DG ND
m OH
m FC
1
3
5
7
9
11
13
15
mSCLK
m C1A
DG ND
m SDO
DG ND
mM1
DG ND
mRGDT
2
4
6
8
10
12
14
16
HEADER 8X2
Chip Signal Connector
JP13
nWRITE 1
D0
3
D1
5
D2
7
D3
9
D4
11
D5
13
D6
15
D7
17
nIRQ 19
nWAIT 21
s5
23
s4
25
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
2
4
6
8
10
12
14
16
18
20
22
24
26
nDSTB
s3
c2
nASTB
HEADER 13X2
Parallel Port Connector
Si30xxPPT-EVB
32
Vcore
Si30xxPPT-EVB
Bill of Materials: Si30XX Motherboard
Item
Qty
Reference
1
10
2
14
3
1
4
2
5
1
6
1
7
1
8
1
9
1
10
4
11
1
12
1
13
1
14
1
15
4
16
1
17
1
18
1
19
1
20
2
21
1
22
1
23
1
24
1
25
1
26
5
27
1
28
1
29
1
30
1
31
1
32
1
33
34
35
36
1
1
1
25
37
38
2
39
40
41
42
43
44
45
46
47
48
49
50
51
52
6
7
1
1
1
1
1
1
1
1
1
6
1
4
4
C1,C2,C3,C4,C9,C10,C11,
C12,C20,C21
C5,C6,C7,C8,C13,C14,C15,
C16,C23,C24,C28,C29,C31,
C32
C17
C18,C22
C19
C25
C26
C27
C30
D1,D2,D3,D4
D5
FB1
JP1
JP2
JP3,JP4,JP9,JP10
JP6
JP7
JP8
JP11
JP14,JP12
JP13
J1
J3
J4
J5
R1,R2,R3,R4,R52
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14,R15,R16,R17,R18,R19,
R20,R21,R22,R23,R24,R25,
R26,R27,R28,R29,R30,R31,
R32,R33,R34,R35,R36,R37,
R38
R40,R39
R41,R42,R43,R44,R53,R54,
R55
R47,R48,R49,R50,R51,R56
SW1
TP1
TP2
U1
U2
U3
U4
U7
U5
Y1
R57
N/A
N/A
Part
10uF, 10 V, ±10%, 1206, , C1206X7R100-106KNE, Venkel
0.1 uF, 16 V, ±10%, 0603, , C0603X7R160-104KNE, Venkel
470 uF, 25 V, ±20%, radial 10x16, , UVX1E471MPA, NIC Components
.1uF, 25V, , 0805, , C0805X7R250-104KNE, Venkel
4.7uF, 10V, +/-10%, 1206, , TDKC3216X5RA475KT, CLASSIC COMP
100 uF, 16 V, ±10%, radial 6.3x11, , , TTI
820 pF, 50 V, ±5%, 0805, , C0805COG500-821JNE, Venkel
1uF, 10 V, ±10%, 1206, , C1206X7R100-105KNE, Venkel
.33uF, 25V, , 0805, , C0805G334Z3NT, CLASSIC COMP
DIODE, 30 V, 0.5 A, SOD-123, , MBR0530T1, Motorola
DIODE, 400 mA, 75 V, DO-35, , 1N4148, Diodes, Inc.
Ferrite Bead on wire, 3x1x4 (mm), , thru-hole 2, , 2743015112, Fair-Rite
HEADER 5X2, , , 5x2 100 mil, , TMM-105-01-G-D, Samtec
CON24, , , 3x8 100 mil, , TSW-108-07-G-T, Samtec
3X1 Header, , , 3x1 100 mil, , 68000-403, Berg Electronics
2X1 Header, , , 2x1 100 mil, , 517-6111TN, Mouser
HEADER 5X2, , , 10 pin thru-hole, , TSW-105-08-T-D-RA, Samtec
HEADER 5X2, , , 10 pin thru-hole, , SSW-105-02-T-D-RA, Samtec
HEADER 8X2, , , 8x2 100 mil, , ,
HEADER 5X2, , , 5x2 100 mil, , ,
HEADER 13X2, , , 13X2 100 mil, , 13x2 pin Header with Shroud, Mouser
RJ-11, , , thru-hole 6, , 154-0L6641, Mouser
Power Connector, , , thru-hole 2, , TSA-2, Adam Tech
2.1 mm Power jack, , , thru-hole 3, , ADC-002-1, Adam Tech
RCA JACK, , , thru-hole, , 16J097, Mouser
2.2K, , , 0805, , CR0805-10W-222JT, Venkel
196k, , , 0805, , MCHRIDEZHFX1963E, Classic Comp
110k, , , 0805, , CR21-114J-T, Classic Comp
20 k, 1/10 W, ±1%, 0805, , NRC10F2002TR, NIC Components
100, 1/4 W, ±1%, 1206, , MCR18EZHMFX1000, Rohm
47 k, 1/10 W, ±5%, 0805, , NRC10J473TR, NIC Components
3 k, 1/10 W, ±5%, 0805, , NRC10J302TR, NIC Components
10, 1/10 W, ±1%, 0805, , NRC10F10R0TR, NIC Components
51, 1/10 W, ±5%, 0805, , CR21-510J-T, AVX
1.6, , +-5%, 1206, , CR1206-8W-1R6JT, Venkel
47K, , , 0603, , CR0603-16W-473JT, Venkel
1K, , , 0603, , CR0603-16W-1002FT, Venkel
10K, , , 0603, , CR0603-16W-1002FT, Venkel
1K, , , 0603, , MCR03FZHJ102, TTI
SW PUSHBUTTON, , , thru-hole 4, , 101-0161, Mouser
Test Point, , , thru-hole, , 151-207, Mouser
Test Point, , , thru-hole, , 151-203, Mouser
TPS77601DR, , , 8-Pin SOIC, , , Texas Instruments
TPS76325DBVR, , , 5-Pin SOT-23, , , Texas Instruments
OP-AMP, , , M, , LM386M-1, National Semi
EP1K30TC144, , , TQFP-144, , EP1K30TC144-3, Altera
7805, , , TO-220AB, , uA7805CKC, Texas Instruments
Socket, , , DIP-8, ,110-99-308-41-001, Mill-Max
PC Recepticle, .038" Diameter, 575-06670, Mouser
0K, , , 0603, , CR0603-16W-000T, Venkel
1/2" Plastic Standoff
Plastic Screw
Preliminary Rev. 1.0
33
Si30xxPPT-EVB
34
Preliminary Rev. 1.0
Figure 21. Si30xx Motherboard Silkscreen
Preliminary Rev. 1.0
35
Si30xxPPT-EVB
Figure 22. Si30xx Motherboard Component Layer
Si30xxPPT-EVB
36
Preliminary Rev. 1.0
Figure 23. Si30xx Motherboard Solder Layer
Si30xxPPT-EVB
Notes:
Preliminary Rev. 1.0
37
Si30xxPPT-EVB
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Si-LINK, Silicon Laboratories, and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
38
Preliminary Rev. 1.0