Si4133/33G-EVB E VALUATION B OA RD F O R T H E S YNTHESIZER F AMILIES Description The Si4133/Si4133G synthesizer family evaluation board is a complete, PC-based evaluation platform for the following Silicon Laboratories devices and their derivatives: Si4133 Si4133G Si4133G-X2 Si4113G-X5 Si4114G Si4135 Si4136 The board includes all support circuitry necessary to evaluate the synthesizer including a reference clock, SMA connections for external measurement equipment, and an interface to a personal computer for controlling the device. The PC software is a graphical, easy-to-use interface that allows the user to directly enter frequencies, set divider ratios, and toggle power control options by a parallel port connection. A PC and power supply are all that is needed for a complete evaluation system. Features Single board evaluation platform PC-based graphical control software included on CD-ROM for Windows 95/98 On-board frequency reference; SMA for external reference SMA connections for synthesizer outputs For use with Silicon Laboratories Si4133, Si4133G, Si4133G-X2, Si4113G-X5, Si4114G, Si4135 and Si4136 synthesizer families (TSSOP or MLP) Function Block Diagram PC Interface PC + – AUXOUT SCLK SDATA SENB RFLB RFLC RF1 RFLD RF2 JRF1 +5 V VDD + – RFLA RFOUT Si41xx PW DNB +3 V JIF1 Reference Clock IF XIN RFLC IFOUT RFLD J1EXT Rev. 0.6 11/11 Copyright © 2011 by Silicon Laboratories Si4133/33G-EVB Si4133/33G-EVB Functional Description The evaluation board accommodates the synthesizer by providing clock circuitry, a PC interface, and other support circuitry necessary for operation. Synthesizer The heart of the evaluation board is the Silicon Laboratories frequency synthesizer. This section includes the synthesizer integrated circuit (IC), external tuning components, output matching, and power supply decoupling circuitry. For devices requiring an external inductor to establish the center frequency for the RF1 and RF2 synthesizers, the inductor is implemented with a printed trace. The IF synthesizer inductor is set by an 0402-size chip inductor. The inductors are set for the nominal center frequencies shown in Table 1. Outputs of the synthesizers are ac-coupled and matched to a 50 load impedance. SMA connectors are provided for easy connection to measurement equipment or to target systems. Output JRF1 is multiplexed between the RF1 and RF2 synthesizers and is toggled through the evaluation software. See the synthesizer data sheet for more detail. The second output, JIF1, is connected to the IF synthesizer output. Both the multiplexed RF output and the IF output can be active simultaneously. Synthesizers are independently enabled using the radio buttons in the evaluation software. The synthesizer IC is supplied by three different power supplies. VDDR supplies the analog circuitry for the RF1 and RF2 synthesizers. VDDI supplies the analog circuitry for the IF synthesizer, and VDDD supplies the digital prescaler, serial interface, and reference input circuitry. Each of these supplies is bypassed to ground with a 22 nF capacitor close to the body of the IC. PC Interface The frequency synthesizer IC uses a serial interface for programming. The three primary signals are serial data (SDATA), serial clock (SCLK), and serial enable (SENB). These are all mapped to data pins of the PC’s parallel port. Data is read back from the IC using the BUSY input of the parallel port and SCLK. One additional signal, GPO, is a multipurpose signal used to control the synthesizer’s hardware power-down enable (PWDNB) and/or to trigger external test equipment. The intended use is for power-up and channel-to-channel settling time measurements. See the "Evaluation Software" section for more detail. Table 1. Center Frequencies Device RF1 Center Frequency (MHz) RF2 Center Frequency (MHz) IF Center Frequency (MHz) Si4133 1600 1200 550 Si4133G 1600 1200 550 Si4133G-X2 1600 1200 1080 Si4113G-X5 1540 1365 N/A Si4114G 1920 1780 N/A Si4135 1750 967 170.76, 420.76 Si4136 2400 2100 550 Clock Circuitry The reference frequency for the synthesizer is generated on-board by a temperature-compensated, voltage-tuned, crystal oscillator. The circuit is flexible to allow evaluation with an external reference source or with different frequency oscillators in varying packages. Header JP6 selects the reference frequency source to the frequency synthesizer IC. Either the on-board oscillator or the external SMA input, J8, can be selected. noise reduction on the tuning input. Test points JP9 and JP10 allow easy connection to the tuning voltage for external frequency trimming or reference modulation. Power Supplies The evaluation board requires a 5 V supply at JP11 to power the digital interface to the PC. The synthesizer’s supply voltage can be taken from the on-board 3 V regulator or a user-supplied voltage at JP11 depending on the jumper setting at JP4. The tuning control of the oscillator, Vc, is fixed at (Vsupply/2) by R19 and R20. C14 provides filtering for 2 Rev. 0.6 Si4133/33G-EVB AUXOUT The AUXOUT pin of the frequency synthesizer can be programmed for a variety of functions. The evaluation board is normally populated so that this pin can be read by the PC for serial reads from the IC. Other functions can be monitored on the AUXOUT test point as well. Refer to the appropriate synthesizer data sheet for details of AUXOUT’s functionality and configuration. Hardware Power Down The hardware power-down input, PWDNB, can be driven several different ways on the evaluation board. The default configuration is pulled high (enabled) through a resistive pull-up, R21. This pin may be controlled through an external source or via evaluation software. To control PWDNB with an external generator, place a shorting block on JP3. There should not be a shorting block on JP2. Connect the output of the generator to test point PWDNB. The test point labeled GND should be connected to the shield of the cable. The evaluation software can power down the synthesizer through the PWDNB pin. JP2 and JP3 must both be jumpered to use this feature. The PWDNB test point can then be used to monitor the PWDNB signal. Refer to the appropriate synthesizer data sheet for a complete explanation of software and hardware power management options. Table 2. Jumper Settings Function Synthesizer and Reference Clock Power Reference Clock Option Jumper Settings Notes On-board regulator JP4: jumper REG to 3 V No supply required on JP11 3 V pin User-supplied JP4: jumper UNREG to 3V Supply required on JP11 3 V pin On-board reference clock JP5: jumper TCXO to ON JP6: TCXO to XIN No clock required on J8 User-supplied PWDNB JP5: jumper TCXO to OFF Clock signal required on J8; JP6: EXT to XIN Check data sheet for requirements. Always high JP2: no jumper JP3: no jumper Power-up/down controlled by register settings. Driven by PC JP2: jumper JP3: jumper PWDNB controlled by evaluation software; Connect instrumentation trigger to PWDNB/GND test points. Driven by external generator JP2: no jumper JP3: jumper PWDNB provided by external generator connected to PWDNB/GND test points. Rev. 0.6 3 Si4133/33G-EVB Table 3. Test Points Function Auxiliary Output PC Interface Power PWDNB Reference Frequency Control Designator Signal AUXOUT AUXOUT signal from synthesizer SCLK Serial clock from PC parallel port SDATA Serial data from PC parallel port SENB Serial enable from PC parallel port GPO General purpose output from PC parallel port 3V Power supply to synthesizer and on-board reference oscillator GND Ground reference for 3 V test point PWDNB PWDNB signal from synthesizer or GPO from PC parallel port GND Ground reference for PWDNB test point VC Frequency control input on TCVCXO GND Ground reference for VC test point Table 4. Connectors Function Designator Signal PC Parallel Port Interface JP1 Parallel port connection to PC Power JP11 5 V supply for parallel port interface and optional 3 V supply for synthesizer and reference oscillator RF Outputs JIF1 IF synthesizer output, nominal 50 JRF1 RF synthesizer output, nominal 50 J8 External reference frequency input, selected by JP6 External Reference Input 4 Rev. 0.6 Si4133/33G-EVB Evaluation Software The Silicon Laboratories evaluation software is a graphical, Windows-based user interface to the Silicon Laboratories synthesizer family. The interface allows the user to directly enter counter integers, frequencies, or control bits without the need to compute and format bitlevel register information. Hardware connection to the evaluation board is through a standard parallel port. Installation After the CD is inserted into the computer, the installer should run automatically. The installer can also be invoked by running the “Installer.exe” program at the root directory of the CD. The CD contains installers for several programs. Select the appropriate device from the list. Window Overview Control data may be entered in a variety of ways. Each numerical parameter can either be entered directly from the keyboard by selecting the box and typing or can be stepped using the up/down arrow keys. Control bits are selected or deselected by radio buttons. Note: The windows shown in these figures are specific to the Si4133 Programmer, version 1.3.6. Evaluation software and options may vary for other synthesizers and software versions. Figure 1. Evaluation Software Rev. 0.6 5 Si4133/33G-EVB Controls Auxiliary Output Control The various controls are described below. Auxiliary Output Control selects the function of the AUXOUT pin. This pin can be used to monitor various functions internal to the synthesizer. Refer to the appropriate synthesizer data sheet for details. Reference Divider, Update Rate Reference Frequency, and The reference divider value sets the update rate of the phase detector for a given reference frequency. This value can be set by either using the R-Divider input, the Reference input, or the Update Rate input. All of these controls are linked to set the R Divider in the synthesizer. Writing to any of these registers for RF1 or RF2 will select the associated synthesizer at the RFOUT output. The R-Divider input directly sets the R Divider of the synthesizer. Changes made to this value will then change the update rate and the synthesized frequency. The Reference input changes all R Dividers to values such that the update rate and synthesized frequency remain at approximately the same value for the entered reference frequency. Note that this changes only the R Divider not the actual reference frequency of the onboard oscillator. Changing the Update Rate input changes the R and N Dividers to maintain the same synthesized frequency for a given reference frequency. Phase Detector This pin also performs the serial read function of the synthesizer registers by the PC. Serial data will appear at this pin if “Verify Device Writes” or if the VCO Tuning Meters are enabled in the SiLabs pull-down menu. Power Down Control The Power Down Control radio buttons select the various software power-down options of the frequency synthesizer IC. (See Figure 2.) The label for each radio button corresponds to the name of the control bit being programmed. See the appropriate synthesizer data sheet for a complete description of power control options. Figure 2. Power-Down Control Radio Buttons The phase detector value window sets the relative gain of the phase detector. Refer to the appropriate synthesizer data sheet for further information about setting of the phase detector gain. AUTOPDB, Force All On, forces the reference amplifier, the RF synthesizers, and the IF synthesizer on. These synthesizers can be enabled independently of each other using PDIB and PDRB. The Auto KP option will automatically select the best KP for phase noise, settling time, and loop stability. The hardware PWDNB input overrides all power-up settings selected in this window. The serial interface remains active when powered down. VCO and N Divider The N Divider can be set by an integer in the N-Divider register or by a decimal frequency in the VCO window. Writing to either of these registers for RF1 or RF2 will select the associated synthesizer at the JRF1 connector. The N-Divider window writes directly to the N Divider of the synthesizer. The values entered in the VCO register will cause the software to automatically compute and set the N register to generate the specified frequency. Menus and Options Menus and options are described below. File Menu The File menu allows register configurations to be saved and restored. By default, configurations are stored as .cfg files in the Configurations folder within the Si4133 Programmer folder. (See Figure 3.) RF Select The RF Select toggle switch selects the RF1 or RF2 synthesizer output on the JRF1 connector. This control does not correspond to an actual control bit. Synthesizers are toggled by writing to the N Divider of the selected synthesizer. User applications should select the active synthesizer by writing to the N or R register as outlined in the appropriate synthesizer data sheet. 6 Rev. 0.6 Si4133/33G-EVB Figure 5. SiLabs Menu Figure 3. File Menu The configuration files are text files and can be viewed and edited with a text editor such as Microsoft Notepad™ or Wordpad™. Edit Menu The Edit menu allows for copy and paste operations between input windows. (See Figure 4.) Selecting Write All Registers refreshes all registers of the frequency synthesizer IC. This should be selected upon power up to ensure all registers are refreshed. Selecting Verify Device Writes reads and verifies the content of the registers as they are written. If a discrepancy occurs, a pop-up window will show “Device Write Verification Failed.” (See Figure 6.) Figure 6. Write Fail The data is read from the frequency synthesizer to the PC through the AUXOUT port. Data read from this register temporarily overrides the function programmed to this pin. Figure 4. Edit Menu SiLabs Menu The SiLabs menu contains the controls specific to the Silicon Laboratories evaluation software and its hardware interface. (See Figure 5.) Show VCO Tuning enables graphical, meter-type displays of the self-tuning results of each VCO. The VCO tuning meters are useful when selecting the values for external inductances or monitoring lock behavior. When the needle is at the extreme left of the display, the VCO is operating at the lower end of its frequency range. Similarly, when the needle is at the extreme right of the display, the VCO is operating at the upper end of its frequency range. (See Figure 7.) Rev. 0.6 7 Si4133/33G-EVB Figure 7. VCO Tuning Detailed information on the operation and interpretation of the self-tuning algorithm is available in the appendix of the frequency synthesizer data sheet entitled, “Evaluating Self Tuning Results.” The Show Register Values option enables a display of the contents of the synthesizer registers. (See Figure 8.) This is useful in computing register values for application software or for debugging. Refer to the Control Register section of the applicable synthesizer data sheet for definition of the values shown. Figure 8. Show Registers The Loop Utility allows the user to automatically toggle between two register settings as shown in Figure 9. Applications include power-up settling time and channel-to-channel settling time measurements. The GPO hardware port is also controlled through the Utility switch in this window to either power down the synthesizer through its hardware port or to trigger external test equipment to correspond to a register write. Figure 9. Loop Utility 8 Rev. 0.6 Si4133/33G-EVB The loop executes sequentially when the green Loop button is selected and repeats until the red Stop button is pressed. There are four steps. In the first, the register selected in the First Register pull-down box is written with the value in the First Value box. The GPO hardware signal on the evaluation board is set high or low dependent on the First Utility switch setting. Help Menu The version number of the software appears in Help About. Contact Silicon Laboratories directly for evaluation software support. The second step is a delay, entered in milliseconds. The third and fourth steps are set similarly to the first and second. The configuration shown in Figure 9 could be used to measure channel-to-channel settling time. Steps 1 and 2 set the N counter of the RF1 synthesizer to a given frequency, set the GPO utility signal low, and then pause for 100 milliseconds. Steps 3 and 4 then reprogram the N counter for a different frequency, set the GPO utility port high to trigger measurement equipment, and delay for another 100 ms. The loop repeats so that the measurement equipment can average over several channel changes. In this measurement, the evaluation board should have J2 and JP3 jumpered so that the GPO signal is routed to the PWDNB test point for connection to the test equipment trigger port and also to the PWDNB pin of the synthesizer. The Open Loop... menu selection invokes the window shown in Figure 10. By setting the VCO to operate at its minimum and maximum frequencies, the center frequency can be calculated by averaging these two extremes. Figure 10. Open Loop Menu Selecting Device ID... causes a pop-up window to appear with an internal device code displayed. Selecting Set Parallel Port allows the user to select either LPT1 or LPT2 to control the evaluation board. Rev. 0.6 9 Si4133/33G-EVB Schematics and Layouts Table 5. Guide to Schematics and Layouts 10 Evaluation Kit Device Schematic Figures Layout Figures Si4133-EVB Si4133-BT Figures 11 and 12 Figures 21 through 25 Si4133M-EVB Si4133-BM Figures 13 and 14 Figures 26 through 30 Si4133G-EVB Si4133G-BT Figures 11 and 12 Figures 21 through 25 Si4133GM-EVB Si4133G-BM Figures 13 and 14 Figures 26 through 30 Si4133GT2-EVB Si4133G-XT2 Figures 11 and 12 Figures 21 through 25 Si4133GM2-EVB Si4133G-XM2 Figures 13 and 14 Figures 26 through 30 Si4113GX5-EVB Si4113GX5-BM Figures 15 and 16 Figures 31 through 35 Si4114G-EVB Si4114G-BM Figures 15 and 16 Figures 31 through 35 Si4135M-EVB Si4135-BM Figures 17 and 18 Figures 36 through 40 Si4136-EVB Si4136-BT Figures 19 and 20 Figures 41 through 45 Rev. 0.6 Rev. 0.6 GND JRF1 L4 2nH C4 560pF Trace Inductor L1 +3VDDRF GND Trace Inductor L2 SENB VDDI IFOUT GNDI IFLB IFLA GNDD VDDD GNDD XIN PDNB AUXO Si4133TSSOP SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR U1 24 23 22 21 20 19 18 17 16 15 14 13 GND 560pF 40nH Pad 1.5 mm Trace 0.156 mm GND C3 22nF JIF1 GND 2.035 mm Trace Pad 1.5 mm Trace Inductor L2 300 um +3VDDRF C5 L5 Trace Inductor L1 10nH 300 um L3 GND +3VDDRF Figure 11. Si4133 TSSOP (1 of 2) GND C1 22nF 1 2 3 4 5 6 7 8 9 10 11 12 C2 22nF R1 0R AUXOUT PWDNB XIN SENB SCLK SDATA Si4133/33G-EVB 11 Rev. 0.6 1 2 3 JP11 Euro_term Si41aj-PCB 4 Layer FR4 1 3 5 7 9 11 13 15 17 19 21 23 25 120k R10 1k R15 120k R13 1 3 2 LP2980AIM-3.0 Vin Vout ON/OFF GND N/C 4 5 GND C10 100pF + GND C17 10uF 1OE 2OE 2Y1 2Y2 2Y3 2Y4 GND Vcc 2A1 2A2 2A3 2A4 JP4 1 2 3 74LVTH241 Reg 3V Unreg GND 10 11 13 15 17 20 1 19 9 7 5 3 C19 10uF C15 10uF + +3VDDRF GND C12 22nF +3VDD GND C18 10uF R24 0R + JP5 GND C13 22nF GND TCXO ON OFF GND C14 10uF + R19 47k 4 3 1 2 GND R25 0R 2.6 6.5 GND 1 1 VC J7 AUXOUT GND GND TCXO Footprint GND R20 47k 13.0MHz TCXO VDD AFC OUTGND U12 J6 SCLK PWDNB J5 SDATA JP2 J4 SENB Note 1: Header test point spacing : 200 mil GND R23 0R +3VDD +3VDD J3 GND J2 +3VDD Figure 12. Si4133 TSSOP (2 of 2) top copper: 35 microns (1 oz final copper + plating thickness) first dielectric: FR4, 210 microns, tolerance +/- 10% ground: 35 microns second dielectric: FR4, 1025 microns, tolerance +/- 20% Vdd: 35 microns third dielectric: FR4, 210 microns, tolerance +/- 10% bottom copper: 35 microns ----------------------------------------------------------------------Total thickness: 1585 microns C16 10uF 120k 120k R11 + U11 R14 1k PC_AUXOUT PC_PWDNB PC_SEND PC_SDATA PC_SCLK 2 4 6 8 1 R12 +5VCC PCB1 HEADER 13X2 +5VCC GND +3VDD GND 2 4 6 8 10 12 14 16 18 20 22 24 26 JP1 1A1 1A2 1A3 1A4 1 1Y1 1Y2 1Y3 1Y4 1 1 +3VDDRF GND 1.1 8.0 Units : mm JP10 JP9 See Note 1 R26 n/f JP3 PWDNB Enable R22 0R GPO / External PWDNB See JP7 JP8 Note 1 1 18 16 14 12 1 2 1 1 1 1 2 3 R16 47K GPO Enable 1 1 2 R17 47K J1 GPO R18 47K U10 JP6 C11 100pF GND External Reference Input J8 XIN TCXO EXT R21 47k +3VDDRF 1 2 3 12 + +5VCC XIN AUXOUT SCLK SDATA SENB PWDNB Si4133/33G-EVB GND JRF1 Trace Inductor L1 L4 2nH C4 560pF GND Trace Inductor L2 GNDR RFLD RFLC GNDR RFLB RFLA GNDR U1 Rev. 0.6 GND C1 22nF 21 20 19 18 17 16 15 GND Si4133MLP GNDI IFLB IFLA GNDD VDDD GNDD XIN GND C2 22nF L3 10nH GND 40nH L5 +3VDDRF Pad 0.8 mm Trace 1.58 mm Trace Inductor L1 GND 0R R1 Figure 13. Si4133 MLP (1 of 2) +3VDDRF GND 1 2 3 4 5 6 7 28 27 26 25 24 23 22 GNDR SDATA SCLK SENB VDDI IFOUT GNDI GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD 8 9 10 11 12 13 14 JIF1 GND C3 22nF +3VDDRF 560pF C5 4.17 mm Trace 0.8 mm Pad Trace Inductor L2 GND AUXOUT PWDNB XIN SENB SCLK SDATA Si4133/33G-EVB 13 Rev. 0.6 1 2 3 JP11 Euro_term Si41ai-PCB 4 Layer FR4 1 3 5 7 9 11 13 15 17 19 21 23 25 120k R10 1k R15 120k R13 1 3 2 LP2980AIM-3.0 Vin Vout ON/OFF GND N/C U11 R14 1k 4 5 GND C10 100pF + GND C17 10uF PC_PWDNB PC_SEND PC_SDATA PC_SCLK PC_AUXOUT 1OE 2OE 2Y1 2Y2 2Y3 2Y4 GND Vcc 2A1 2A2 2A3 2A4 JP4 1 2 3 74LVTH241 Reg 3V Unreg GND 10 11 13 15 17 20 1 19 9 7 5 3 C19 10uF C15 10uF + +3VDDRF GND C12 22nF +3VDD GND GND C18 10uF R24 0R + JP5 GND C13 22nF GND TCXO ON OFF C14 10uF + R19 47k Note 1: Header test point spacing : 200 mil GND R23 0R +3VDD +3VDD 4 3 1 2 GND R25 0R 2.6 6.5 R22 0R 1.1 8.0 Units : mm JP10 JP9 GND R26 n/f JP3 PWDNB Enable +3VDDRF See Note 1 GND 1 1 VC J7 AUXOUT GND GND TCXO Footprint GND R20 47k 13.0MHz TCXO VDD AFC OUTGND U12 J6 SCLK J5 SDATA J4 SENB J3 GND PWDNB J2 +3VDD Figure 14. Si4133 MLP (2 of 2) top copper: 35 microns (1 oz final copper + plating thickness) first dielectric: FR4, 210 microns, tolerance +/- 10% ground: 35 microns second dielectric: FR4, 1025 microns, tolerance +/- 20% Vdd: 35 microns third dielectric: FR4, 210 microns, tolerance +/- 10% bottom copper: 35 microns ----------------------------------------------------------------------Total thickness: 1585 microns C16 10uF 120k R11 + 120k R12 +5VCC PCB1 HEADER 13X2 +5VCC GND +3VDD GND 2 4 6 8 10 12 14 16 18 20 22 24 26 JP1 1A1 1A2 1A3 1A4 1 1Y1 1Y2 1Y3 1Y4 GPO / External PWDNB See JP7 JP8 Note 1 1 JP2 1 GPO Enable 1 1 1 1 J1 GPO 1 2 1 1 2 3 R16 47K 2 4 6 8 R18 47K U10 1 1 2 R17 47K 18 16 14 12 JP6 C11 100pF GND External Reference Input J8 XIN TCXO EXT R21 47k +3VDDRF 1 2 3 14 + +5VCC XIN AUXOUT SCLK SDATA SENB PWDNB Si4133/33G-EVB 1 3 5 7 9 11 13 15 17 19 21 23 25 Rev. 0.6 120k R11 120k R10 C16 10uF 120k R12 + 120k R13 +5VCC 1k R15 1 3 2 Si41ao-PCB 4 Layer FR4 PCB1 TPS76030DBV Vin Vout ON/OFF GND N/C U11 R14 1k 4 5 10uF C19 GND C10 100pF GND + + PC_GPO PC_SEND PC_SDATA PC_SCLK GND C17 10uF PC_AUXOUT 1OE 2OE 2Y1 2Y2 2Y3 2Y4 GND Vcc 2A1 2A2 2A3 2A4 JP4 1 2 3 74LVTH241 Reg 3V Unreg GND 10 11 13 15 17 1A1 1A2 1A3 1A4 20 1 19 9 7 5 3 + GND 2.6 6.5 TCXO Footprint C15 10uF +3VDDRF GND C12 22nF +3VDD GND + 1.1 8.0 Units : mm C18 10uF R24 0R R23 0R +3VDD +3VDD GND C13 22nF GND JP5 GND TCXO ON OFF J3 GND J2 +3VDD C14 10uF + R19 47k 4 3 1 2 GND R20 47k 13.0MHz TCXO VDD AFC OUTGND U12 J6 SCLK PWDNB 1 1 GND R25 0R R22 0R 1 GND JP10 JP3 PWDNB Enable +3VDDRF See Note VC 1 JP9 1 J7 AUXOUT GND GND GPO / External PWDNB See JP7 JP8 Note 1 J5 SDATA JP2 J4 SENB Figure 15. Si4113GX5 MLP (1 of 2) top copper: 35 microns (1 oz final copper + plating thickness) first dielectric: FR4, 210 microns, tolerance +/- 10% ground: 35 microns second dielectric: FR4, 1025 microns, tolerance +/- 20% Vdd: 35 microns third dielectric: FR4, 210 microns, tolerance +/- 10% bottom copper: 35 microns ----------------------------------------------------------------------Total thickness: 1585 microns Note 1: Header test point spacing : 200 mil Euro_term 1 2 3 JP11 HEADER 13X2 +5VCC GND +3VDD GND 2 4 6 8 10 12 14 16 18 20 22 24 26 JP1 1Y1 1Y2 1Y3 1Y4 1 GPO Enable 1 J1 GPO 1 2 4 6 8 1 2 1 U10 R16 47K 18 16 14 12 1 GND R26 n/f AUXOUT SCLK SDATA SENB PWDNB GND J8 R27 50 XIN External Reference Input GND C11 100pF JP6 R21 47k +3VDDRF XIN TCXO EXT 1 2 R17 47K 1 1 1 2 3 R18 47K 1 2 3 +5VCC Si4133/33G-EVB 15 Rev. 0.6 Pad 0.8 mm Trace 1.75 mm Trace Inductor L1 L4 2nH C4 560pF 2.33 mm Trace +3VDDRF GND GNDR RFLD RFLC GNDR RFLB RFLA GNDR U1 GND C1 22nF 21 20 19 18 17 16 15 GND Si4113GX5-BM GNDD GNDD GNDD GNDD VDDD GNDD XIN Figure 16. Si4113GX5 MLP (2 of 2) 0.8 mm Pad Trace Inductor L2 GND JRF1 Trace Inductor L1 GND Trace Inductor L2 1 2 3 4 5 6 7 +3VDDRF 28 27 26 25 24 23 22 GNDR SDATA SCLK SENB VDDD GNDD GNDD GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD 16 8 9 10 11 12 13 14 GND GND C3 22nF +3VDDRF AUXOUT PWDNB XIN SENB SCLK SDATA Si4133/33G-EVB 1 3 5 7 9 11 13 15 17 19 21 23 25 Rev. 0.6 120k R11 120k R10 C16 10uF 120k R12 + 120k R13 +5VCC 1k R15 R29 1k 1 3 2 Si41ap-PCB 4 Layer FR4 PCB1 R30 1k R28 1k C21 100pF 4 5 10uF C23 C22 100pF GND + + GND GND C17 10uF C10 100pF PC_GPO PC_SENB PC_SDATA PC_SCLK PC_AUXOUT 1OE 2OE 2Y1 2Y2 2Y3 2Y4 GND Vcc 2A1 2A2 2A3 2A4 JP4 1 2 3 74LVTH241 Reg 3V Unreg GND 10 11 13 15 17 1A1 1A2 1A3 1A4 20 1 19 9 7 5 3 C15 10uF GND C12 22nF + GND +3VDD GND C18 10uF R24 0R R23 0R +3VDD +3VDD + GND C13 22nF GND JP5 GND TCXO ON OFF J3 GND J2 +3VDD Figure 17. Si4135 MLP (1 of 2) top copper: 35 microns (1 oz final copper + plating thickness) first dielectric: FR4, 210 microns, tolerance +/- 10% ground: 35 microns second dielectric: FR4, 1025 microns, tolerance +/- 20% Vdd: 35 microns third dielectric: FR4, 210 microns, tolerance +/- 10% bottom copper: 35 microns ----------------------------------------------------------------------Total thickness: 1585 microns TPS76030DBV Vin Vout ON/OFF GND N/C U11 C20 100pF R14 1k Note 1: Header test point spacing : 200 mil Euro_term 1 2 3 JP11 HEADER 13X2 +5VCC GND +3VDD GND 2 4 6 8 10 12 14 16 18 20 22 24 26 JP1 1Y1 1Y2 1Y3 1Y4 1 C14 10uF R19 47k + 4 3 1 2 1.1 8.0 TCXO Footprint GND R20 47k GND JP10 JP9 2.6 6.5 GND R26 n/f GND J8 R27 50 XIN AUXOUT SCLK SDATA SENB PWDNB External Reference Input GND C11 100pF JP6 R21 47k +3VDD XIN TCXO EXT JP3 PWDNB Enable R22 0R Units : mm See Note 1 GND 1 1 VC J7 AUXOUT GND GND R25 0R 19.68 MHz TCXO VDD AFC OUTGND U12 J6 SCLK J5 SDATA PWDNB See GPO / External Note PWDNB 1 JP7 JP8 J4 SENB JP2 1 GPO Enable 1 1 J1 GPO 1 2 4 6 8 1 2 1 1 1 1 2 3 1 2 U10 1 18 16 14 12 1 2 3 +5VCC Si4133/33G-EVB 17 Rev. 0.6 0.6 mm 0.8 mm RFLD NC RFLC RFLB RFLA GND RFOUT 560pF place close to U1 C4 5.6nH 1 2 3 4 5 6 7 U1 L4 GND C1 22nF 560pF C5 VDDI IFLA IFLB PTSTEN VDDD GND XIN Si4135-BM 21 20 19 18 17 16 15 GND 27nH GND close to U1.17 L3 close to U1.21 C2 22nF C3 22nF place close to U1 47nH GND L5 GND See Note 1 Figure 18. Si4135 MLP (2 of 2) Pad Pad Pad Pad 0.72 mm 0.8 mm 0.3 mm Fill Pad Trace Inductor L1 Trace Inductor L1 Trace Inductor L2 Trace Inductor L2 close to U1.28 +3VDD GND 1 GND PWDNB SENB SCLK SDATA DAUX GND 8 9 10 11 12 13 14 make cuttable AAUX 1 28 27 26 25 24 23 22 VDDR TEST NC AAUX GND IFOUT GND JTST1 AAUX 120k R31 JP12 VDD PTSTEN 1 2 18 J10 J9 JRF1 GND JIF1 GND PWDNB SENB SCLK SDATA AUXOUT XIN GND Si4133/33G-EVB Rev. 0.6 GND JRF1 470pF C4 L4 0R +3VDDRF GND GND SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR U1 Si4136-BT SEND VDDI IFOUT GNDI IFLB IFLA GNDD VDDD GNDD XIN PDNB AUXO 24 23 22 21 20 19 18 17 16 15 14 13 L3 10nH GND GND 40nH L5 560pF C5 +3VDDRF C3 22nF GND +3VDDRF Figure 19. Si4136 TSSOP (1 of 2) C1 22nF 1 2 3 4 5 6 7 8 9 10 11 12 C2 22nF R1 0R JIF1 GND AUXOUT PWDNB XIN SENB SCLK SDATA Si4133/33G-EVB 19 Rev. 0.6 1 2 3 JP11 Euro_term Si41ak-PCB 4 Layer FR4 1 3 5 7 9 11 13 15 17 19 21 23 25 120k R10 1k R15 120k R13 1 3 2 LP2980AIM-3.0 Vin Vout ON/OFF GND N/C U11 R14 1k 4 5 GND C10 100pF + GND C17 10uF PC_PWDNB PC_SEND PC_SDATA PC_SCLK PC_AUXOUT 1OE 2OE 2Y1 2Y2 2Y3 2Y4 GND Vcc 2A1 2A2 2A3 2A4 JP4 1 2 3 74LVTH241 Reg 3V Unreg GND 10 11 13 15 17 20 1 19 9 7 5 3 C19 10uF C15 10uF + +3VDDRF GND C12 22nF +3VDD GND GND GND + JP5 GND C13 22nF GND TCXO ON OFF C14 10uF + R19 47k 4 3 Note 1: Header test point spacing : 200 mil C18 10uF R24 0R R23 0R +3VDD +3VDD 1 2 GND R25 0R 2.6 6.5 GND 1 1 VC J7 AUXOUT GND GND TCXO Footprint GND R20 47k 13.0MHz TCXO VDD AFC OUTGND U12 J6 SCLK J5 SDATA J4 SENB J3 GND PWDNB J2 +3VDD Figure 20. Si4136 TSSOP (2 of 2) top copper: 35 microns (1 oz final copper + plating thickness) first dielectric: FR4, 210 microns, tolerance +/- 10% ground: 35 microns second dielectric: FR4, 1025 microns, tolerance +/- 20% Vdd: 35 microns third dielectric: FR4, 210 microns, tolerance +/- 10% bottom copper: 35 microns ----------------------------------------------------------------------Total thickness: 1585 microns C16 10uF 120k R11 + 120k R12 +5VCC PCB1 HEADER 13X2 +5VCC GND +3VDD GND 2 4 6 8 10 12 14 16 18 20 22 24 26 JP1 1A1 1A2 1A3 1A4 1 1Y1 1Y2 1Y3 1Y4 +3VDDRF GND 1.1 8.0 Units : mm JP10 JP9 See Note 1 R26 n/f JP3 PWDNB Enable R22 0R GPO / External PWDNB See Note 1 JP7 JP8 1 JP2 1 GPO Enable 1 1 1 1 J1 GPO 1 2 1 1 2 3 R16 47K 2 4 6 8 R18 47K U10 1 1 2 R17 47K 18 16 14 12 JP6 C11 100pF GND External Reference Input J8 XIN TCXO EXT R21 47k +3VDDRF 1 2 3 20 + +5VCC XIN AUXOUT SCLK SDATA SENB PWDNB Si4133/33G-EVB Si4133/33G-EVB Figure 21. Si4133BT Silkscreen Figure 22. Si4133BT Component Rev. 0.6 21 Si4133/33G-EVB Figure 23. Si4133BT Ground Figure 24. Si4133BT Power 22 Rev. 0.6 Si4133/33G-EVB Figure 25. Si4133BT Solder Figure 26. Si4133M Silkscreen Rev. 0.6 23 Si4133/33G-EVB Figure 27. Si4133M Component Figure 28. Si4133M Ground 24 Rev. 0.6 Si4133/33G-EVB Figure 29. Si4133M Power Figure 30. Si4133M Solder Rev. 0.6 25 Si4133/33G-EVB Figure 31. Si4113GX5-BM Silkscreen Figure 32. Si4113GX5-BM Component 26 Rev. 0.6 Si4133/33G-EVB Figure 33. Si4113GX5-BM Ground Figure 34. Si4113GX5-BM Power Rev. 0.6 27 Si4133/33G-EVB Figure 35. Si4113GX5-BM Solder Figure 36. Si4135M Silkscreen 28 Rev. 0.6 Si4133/33G-EVB Figure 37. Si4135M Component Figure 38. Si4135M Ground Rev. 0.6 29 Si4133/33G-EVB Figure 39. Si4135M Power Figure 40. Si4135M Solder 30 Rev. 0.6 Si4133/33G-EVB Figure 41. Si4136BT Silkscreen Figure 42. Si4136BT Component Rev. 0.6 31 Si4133/33G-EVB Figure 43. Si4136BT Ground Figure 44. Si4136BT Power 32 Rev. 0.6 Si4133/33G-EVB Figure 45. Si4136BT Solder Rev. 0.6 33 Si4133/33G-EVB Bill of Materials Part Reference Value C1,C2*,C3,C12,C13 C4,C5 * C10,C11 C14,C15,C16,C17,C18,C19 JRF1,JIF1*,J8 JP1 JP2,JP3 JP4,JP5,JP6 JP7 JP8 JP9 J3,JP10 JP11 J1 J2 J4 J5 J6 J7 L1 L2 L3 L3 L4 L4 L5 R1 R10,R11,R12,R13 R14,R15 R16,R17,R18,R19,R20,R21 R22,R23,R24,R25 R26 U1 U1 U1 U1 U1 U1 U1 U1 U10 U11 U12 22nF 560pF 100pF 10uF SMA_E HEADER 13X2 HEADER 2 HEADER 3 PWDNB GND VC GND Euro_term GPO +3VDD SENB SDATA SCLK AUXOUT Trace Inductor Trace Inductor 10nH 0R 2nH 0R 40nH 0R 120k 1k 47k 0R n/f Si4133-BT Si4133-BM Si4133G-BT Si4133G-BM Si4133G-XT2 Si4133G-XM2 Si4136-BT Si4113G-X5 74LVTH241 TPS76030DBV 13.0MHz TCXO Dielectric X7R X7R COG X7R ---------------------------------------- Tolerance 20% 10% 5% 10% -----------------5% -5% -5% -5% 1% 5% -----------+/- .75% 2.5ppm Working Voltage/ Power 25V 50V 50V 10V -----------------100V .063W 100V .063W 100V .063W -.125W -.1W ----------16V 3V Notes: * Not used on the Si4113GX5-EVB. 1. Used on all evaluation boards. 2. Used on the Si4133-EVB. 3. Used on the Si4133M-EVB. 4. Used on the Si4133G-EVB. 5. Used on the Si4133GM-EVB. 6. Used on the Si4133GT2-EVB. 7. Used on the Si4133GM2-EVB. 8. Used on the Si4136-EVB. 9. Used on the Si4113GX5-EVB. 34 Rev. 0.6 Number C0402X7R250-223MNE C0402X7R500-561KNE C0402COG500-101JNE C1206X7R100-106KNE RA2EJ2-6G 13x2 pin Header with Shroud 68000-402 68000-402 040/SO1BK2F 040/SO1BK2F not installed not installed MKDSN 1,5/3 not installed not installed not installed not installed not installed not installed --0402CS-10NXJBX CR0402-16W-000T 0402CS-2N0XJBX CR0402-16W-000T 0402CS-40NXJBX CR0402-16W-000T CR0805-10W-124JT CR0805-10W-1001FT CR0805-10W-473JT CR0805-10W-000T not installed Si4133-BT Si4133-BM Si4133G-BT Si4133G-BM Si4133G-XT2 Si4133G-XM2 Si4136-BT Si4113G-X5 SN74LVTH241PW TPS76030DBV RTVY-174-13.0MHz Vendor Venkel Venkel Venkel Venkel Y-Connect Mouser Berg Berg Oxley Oxley --Phoenix Contact --------Coilcraft Venkel Coilcraft Venkel Coilcraft Venkel Venkel Venkel Venkel Venkel -Silicon Labs Silicon Labs Silicon Labs Silicon Labs Silicon Labs Silicon Labs Silicon Labs Silicon Labs Texas Instruments Texas Instruments Raltron Package 0402 0402 0402 Case A SMA_E 13x2_0.100_in 2x1 100 mil 3x1 100mil TP_1 TP_1 TP_1 TP_1 through_3 TP_1 TP_1 TP_1 TP_1 TP_1 TP_1 --0402 0402 0402 0402 0402 0402 0805 0805 0805 0805 0805 TSSOP-24 MLP-28 TSSOP-24 MLP-28 TSSOP-24 MLP-28 TSSOP-24 MLP-28 TSSOP-20 5L-SOT-23 TXCO Note 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2-7 2-8 2-5, 8 6-7 2-7, 9 9 2-8 2-8 1 1 1 1 1 2 3 4 5 6 7 8 9 1 1 1 Si4133/33G-EVB Ordering Guide Ordering Part Number Description Si4133 Family (TSSOP) Si4133-EVB Evaluation Board with Si4133-BT (TSSOP) and Evaluation Kit (PC parallel port cable, evaluation software on CD-ROM, and documentation) Si4123-EVB Si4133-EVB with Si4123-BT Sample Kit Si4122-EVB Si4133-EVB with Si4122-BT Sample Kit Si4113-EVB Si4133-EVB with Si4113-BT Sample Kit Si4112-EVB Si4133-EVB with Si4112-BT Sample Kit Si4133 Family (MLP) Si4133M-EVB Evaluation Board with Si4133-BM (MLP) and Evaluation Kit Si4123M-EVB Si4133M-EVB with Si4123-BM Sample Kit Si4122M-EVB Si4133M-EVB with Si4122-BM Sample Kit Si4113M-EVB Si4133M-EVB with Si4113-BM Sample Kit Si4112M-EVB Si4133M-EVB with Si4112-BM Sample Kit Si4133G Family (TSSOP) Si4133G-EVB Evaluation Board with Si4133G-BT (TSSOP) and Evaluation Kit Si4123G-EVB Si4133G-EVB with Si4123G-BT Sample Kit Si4122G-EVB Si4133G-EVB with Si4122G-BT Sample Kit Si4113G-EVB Si4133G-EVB with Si4113G-BT Sample Kit Si4112G-EVB Si4133G-EVB with Si4112G-BT Sample Kit Si4133G Family (MLP) Si4133GM-EVB Evaluation Board with Si4133G-BM (MLP) and Evaluation Kit Si4123GM-EVB Si4133GM-EVB with Si4123G-BM Sample Kit Si4122GM-EVB Si4133GM-EVB with Si4122G-BM Sample Kit Si4113GM-EVB Si4133GM-EVB with Si4113G-BM Sample Kit Si4112GM-EVB Si4133GM-EVB with Si4112G-BM Sample Kit Si4133G-XT2 (TSSOP) Si4133GT2-EVB Evaluation Board with Si4133G-XT2 (TSSOP) and Evaluation Kit Si4133G-XM2 (MLP) Si4133GM2-EVB Evaluation Board with Si4133G-XM2 (MLP) and Evaluation Kit Si4133G-X5 (MLP) Si4113GX5-EVB Evaluation Board with Si4113GX5-BM (MLP) and Evaluation Kit Si4135 (MLP) Si4135M-EVB Evaluation Board with Si4135-BM (MLP) and Evaluation Kit Rev. 0.6 35 Si4133/33G-EVB Document Change List Revision 0.5 to Revision 0.6 36 Removed references to Si4133W. Rev. 0.6 Si4133/33G-EVB Notes: Rev. 0.6 37 Simplicity Studio One-click access to MCU tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! www.silabs.com/simplicity MCU Portfolio www.silabs.com/mcu SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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