EFM32TG825 Errata History - F32/F16/F8

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EFM32TG825 Errata History
F32/F16/F8
This document describes known errata for all revisions of EFM32TG825 devices.
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1 Errata History
1.1 Errata Overview
Table 1.1 (p. 2) shows which erratum is applicable for each revision. The device datasheet explains how to identify chip revision, either from package
marking or electronically.
In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p1 (www.arm.com) also applies to all revisions of this device.
Table 1.1. Errata Overview
Erratum ID
Rev. C
Rev. B
AES_E101
X
X
AES_E102
X
X
CMU_E108
X
CMU_E109
X
DMA_E101
X
X
EMU_E105
X
GPIO_E101
X
LES_E101
X
LES_E102
X
LES_E103
X
PRS_E101
X
X
TIMER_E102
X
X
USART_E112
X
X
WDOG_E103
X
X
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1.2 EFM32TG825 Errata Descriptions
Table 1.2. EFM32TG825 Errata Descriptions
ID
Title/Problem
Effect
Fix/Workaround
AES_E101
BYTEORDER does not work
in combination with DATASTART/XORSTART
If BYTEORDER is used in combination with DATASTART
or XORSTART, the AES data and key are interpreted in the
wrong order.
Do not use BYTEORDER in combination with DATASTART
or XORSTART.
If BYTEORDER is used, it will take one cycle for the
AES_STATUS_RUNNING flag to be set. This means that
polling this status flag should be postponed at least one cycle
after starting encryption/decryption.
If polling the AES_STATUS_RUNNING is preferred, insert a
No Operation assembly instruction (NOP()) before starting to
poll the status flag.
For devices with PROD_REV < 15, enabling the clock for
LFA/LFB after reset and then immediately writing LFACLKEN/LFBCLKEN, may cause the write to miss its effect.
For devices with PROD_REV < 15, make sure
CMU_SYNCBUSY is not set before writing LFACLKEN/LFBCLKEN. Can temporarily switch to HFCORECLKLEDIV2 to
speed up clearing synchbusy.
For devices with PROD_REV < 15, the default value for
LFXOBOOST in CMU_CTRL are wrong.
On devices with PROD_REV < 15, change LFXOBOOST to
0.
In EM2, when sleeping with WFE (Wait for Event), an interrupt from the DMA will not wake up the system.
Use WFI (Wait for Interrupt) or EM1 instead.
DMA requests from the LEUART can trigger a DMA operation from EM2. While waiting for the DMA to fetch data from
the respective peripheral, the debugger cannot access the
system. If such a DMA request is not handled by the DMA
controller, the system will keep waiting for it while denying
debug access.
Make sure DMA requests triggered from EM2 are handled.
All EM4 wakeup cause bits for EM4 wakeup pins with high
polarity are set on wakeup.
Use low polarity if possible. For active high, slow changing inputs, a solution is to sample the inputs on wakeup.
When the BYTEORDER bit in
AES_CTRL is set, an encryption or decryption should not be started through
DATASTART or XORSTART.
AES_E102
AES_STATUS_RUNNING set one
cycle late with BYTEORDER set
When the BYTEORDER
bit in AES_CTRL is set,
AES_STATUS_RUNNING is set one
cycle late.
CMU_E108
LFxCLKEN write
First write to LFxCLKEN can be
missed.
CMU_E109
LFXO configuration incorrect
LFXO configuration incorrect.
DMA_E101
EM2 with WFE and DMA
WFE does not work for the DMA in
EM2.
EMU_E105
Debug unavailable during DMA processing from EM2
The debugger cannot access the system processing DMA request from
EM2.
GPIO_E101
GPIO wakeup from EM4
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ID
Title/Problem
Effect
Fix/Workaround
On GPIO wakeup from EM4 all cause
bits for high-polarity wakeup pins are
set.
LES_E101
LES_E102
LESENSE and Schmitt trigger
Schmitt trigger cannot be disabled on
pins used for sensor excitation
When using LESENSE to excite a pin, the pin has to be con- Keep the input voltage to pins configured as push-pull outfigured in push-pull mode, which also enables the Schmitt
side the range 0.3*VDD to 0.7*VDD when LESENSE is not
trigger. If this pin has an input voltage somewhere in between interacting with the connected sensor.
0.3*VDD and 0.7*VDD, the Schmitt trigger will consume a
considerable ammount of current.
LESENSE and DAC CH1 configuration
LESENSE control of DAC CH1 cannot be enabled if
DACCH0CONV in LESENSE_PERCTRL is set to DISABLE.
Configure DACCH0CONV in LESENSE_PERCTRL to anything but DISABLE, this enables DAC CH1 to be controlled
properly. If DAC CH0 is not to be used, set DACCH0OUT
in LESENSE_PERCTRL to DISABLE. This will disable
LESENSE control of DAC CH0, but still allow LESENSE to
control DAC CH1.
LESENSE will not work properly when used with the AUXHFRCO running at the 1 or 7 MHz band.
Do not use a AUXHFRCO frequency band of 1 or 7 MHz
when used in combination with LESENSE.
When using edge detect in PRS on signals from ACMP,
GPIO, RTC, LETIMER, LESENSE, VCMP and BURTC
edges can be missed.
Do not use edge detect on ACMP, GPIO, RTC, LETIMER,
LESENSE, VCMP and BURTC.
When DEBUGRUN is disabled, and the capture input is
HIGH it is possible to wrongly trigger a capture event by halting the MCU and starting it again (for instance by setting a
breakpoint).
Enable DEBUGRUN when using a debugger.
LESENSE cannot control
DAC CH1 if DACCH0CONV in
LESENSE_PERCTRL is set to DISABLE.
LES_E103
AUXHFRCO and LESENSE
LESENSE will not work properly at low
AUXHFRCO frequencies.
PRS_E101
Edge detect on GPIO/ACMP
Edge detect on peripherals with asynchronous edges might be missed.
TIMER_E102
Timer capture and debugger
Timer capture triggered when timer is
halted by debugger.
USART_E112
USART AUTOTX continues to transmit even with full RX buffer
When AUTOTX in USARTn_CTRL or AUTOTXEN in
USARTn_TRIGCTRL is set, the USART will continue to
transmit data even after the RX buffer is full. This may cause
USART AUTOTX continues to transmit the RX buffer to overflow if the data is not read out in time.
even with full RX buffer.
WDOG_E103
WDOG EM2 detection with LFXO
digital/sine input
No known workaround.
When the WDOG is using LFXO with digital or sine input as a When using LFXO with digital/sine input, EM3RUN must be
clock source, it will mistake EM2 for EM3. The EM2RUN and set to keep the WDOG running in EM2.
EM3RUN bits of WDOG_CTRL will behave accordingly.
The WDOG will mistake EM2 for EM3
if using LFXO with digital or sine input.
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2 Revision History
2.1 Revision 0.6
August 21st, 2013
Added AES_E102.
Updated disclaimer, trademark and contact information.
2.2 Revision 0.50
July 30th, 2013
Added DMA_E101.
Updated errata naming convention.
2.3 Revision 0.40
November 26th, 2012
Added AES1.
Added TIMER1.
Updated with chip revision C.
2.4 Revision 0.30
August 22nd, 2012
Initial verison.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system
and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples
described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon
Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications.
Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or
chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, the Silicon Labs logo, Energy Micro, EFM, EFM32, EFR, logo and combinations thereof, and others are the
registered trademarks or trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM
Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Errata History .............................................................................................................................................................................................................................
1.1. Errata Overview ................................................................................................................................................................................................................
1.2. EFM32TG825 Errata Descriptions ........................................................................................................................................................................................
2. Revision History ..........................................................................................................................................................................................................................
2.1. Revision 0.6 .....................................................................................................................................................................................................................
2.2. Revision 0.50 ...................................................................................................................................................................................................................
2.3. Revision 0.40 ...................................................................................................................................................................................................................
2.4. Revision 0.30 ...................................................................................................................................................................................................................
A. Disclaimer and Trademarks ..........................................................................................................................................................................................................
A.1. Disclaimer .......................................................................................................................................................................................................................
A.2. Trademark Information .......................................................................................................................................................................................................
B. Contact Information .....................................................................................................................................................................................................................
B.1. .....................................................................................................................................................................................................................................
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3
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List of Tables
1.1. Errata Overview ........................................................................................................................................................................................................................ 2
1.2. EFM32TG825 Errata Descriptions ................................................................................................................................................................................................ 3
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