4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM

4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Features
1.35V DDR3L SDRAM VLP RDIMM
MT18KDF51272PZ – 4GB
Features
Figure 1: 240-Pin RDIMM (MO-269 R/C M)
• DDR3L functionality and operations supported as
per the component data sheet
• 240-pin, very low profile, 18.75mm, registered dual
in-line memory module (VLP RDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 4GB (512 Meg x 72)
• VDD = 1.35V (1.283–1.45V)
• VDD = 1.5V (1.425–1.575V)
• Backward compatible to V DD = 1.5V ±0.075V
• VDDSPD = 3.0–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data and strobe signals
• Single-rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Module height: 18.75mm (0.738in)
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T A ≤ +70°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
None
Z
-1G6
-1G4
-1G1
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
-1G6
PC3-12800
1600
-1G4
PC3-10600
-1G1
PC3-8500
-1G0
-80B
tRP
tRC
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
(ns)
(ns)
(ns)
1333
1333
1066
1066
800
667
13.125
13.125
48.125
–
1333
1333
1066
1066
800
667
13.125
13.125
49.125
–
–
–
1066
1066
800
667
13.125
13.125
50.625
PC3-8500
–
–
–
1066
–
800
667
15
15
52.5
PC3-6400
–
–
–
–
–
800
667
15
15
52.5
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
PDF: 09005aef83aa7149
kdf18c512x72pz.pdf - Rev. G 4/13 EN
CL = 11 CL = 10
tRCD
Products and specifications discussed herein are subject to change by Micron without notice.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Features
Table 2: Addressing
Parameter
4GB
Refresh count
8K
Row address
32K A[14:0]
Device bank address
8 BA[2:0]
Device configuration
2Gb (512 Meg x 4)
Column address
2K A[11, 9:0]
Module rank address
1 S0#
Table 3: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41K512M4,1 2Gb DDR3 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18KDF51272PZ-1G6__
4GB
512 Meg x 72
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT18KDF51272PZ-1G4__
4GB
512 Meg x 72
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT18KDF51272PZ-1G1__
4GB
512 Meg x 72
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT18KDF51272PZ-1G4K1.
PDF: 09005aef83aa7149
kdf18c512x72pz.pdf - Rev. G 4/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
240-Pin DDR3 RDIMM Front
240-Pin DDR3 RDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
1
VREFDQ
31
DQ25
61
A2
91
DQ41
121
VSS
151
VSS
181
A1
211
VSS
2
VSS
32
VSS
62
VDD
92
VSS
122
DQ4
152
DQS12
182
VDD
212
DQS14
3
DQ0
33
DQS3#
63
NF
93
DQS5#
123
DQ5
153
DQS12#
183
VDD
213
DQS14#
4
DQ1
34
DQS3
64
NF
94
DQS5
124
VSS
154
VSS
184
CK0
214
VSS
5
VSS
35
VSS
65
VDD
95
VSS
125
DQS9
155
DQ30
185
CK0#
215
DQ46
6
DQS0#
36
DQ26
66
VDD
96
DQ42
126
DQS9#
156
DQ31
186
VDD
216
DQ47
7
DQS0
37
DQ27
67
VREFCA
97
DQ43
127
VSS
157
VSS
187
EVENT#
217
VSS
8
VSS
38
VSS
68
Par_In
98
VSS
128
DQ6
158
CB4
188
A0
218
DQ52
9
DQ2
39
CB0
69
VDD
99
DQ48
129
DQ7
159
CB5
189
VDD
219
DQ53
10
DQ3
40
CB1
70
A10
100
DQ49
130
VSS
160
VSS
190
BA1
220
VSS
11
VSS
41
VSS
71
BA0
101
VSS
131
DQ12
161
DQS17
191
VDD
221
DQS15
12
DQ8
42
DQS8#
72
VDD
102
DQS6#
132
DQ13
162
DQS17#
192
RAS#
222
DQS15#
13
DQ9
43
DQS8
73
WE#
103
DQS6
133
VSS
163
VSS
193
S0#
223
VSS
14
VSS
44
VSS
74
CAS#
104
VSS
134
DQS10
164
CB6
194
VDD
224
DQ54
15
DQS1#
45
CB2
75
VDD
105
DQ50
135
DQS10#
165
CB7
195
ODT0
225
DQ55
16
DQS1
46
CB3
76
NC
106
DQ51
136
VSS
166
VSS
196
A13
226
VSS
17
VSS
47
VSS
77
NC
107
VSS
137
DQ14
167
NU
197
VDD
227
DQ60
18
DQ10
48
VTT
78
VDD
108
DQ56
138
DQ15
168
RESET#
198
NC
228
DQ61
19
DQ11
49
VTT
79
NC
109
DQ57
139
VSS
169
NC
199
VSS
229
VSS
20
VSS
50
CKE0
80
VSS
110
VSS
140
DQ20
170
VDD
200
DQ36
230
DQS16
21
DQ16
51
VDD
81
DQ32
111
DQS7#
141
DQ21
171
A15
201
DQ37
231
DQS16#
22
DQ17
52
BA2
82
DQ33
112
DQS7
142
VSS
172
A14
202
VSS
232
VSS
23
VSS
53
Err_Out#
83
VSS
113
VSS
143
DQS11
173
VDD
203
DQS13
233
DQ62
24
DQS2#
54
VDD
84
DQS4#
114
DQ58
144
DQS11#
174
A12
204
DQS13#
234
DQ63
25
DQS2
55
A11
85
DQS4
115
DQ59
145
VSS
175
A9
205
VSS
235
VSS
26
VSS
56
A7
86
VSS
116
VSS
146
DQ22
176
VDD
206
DQ38
236
VDDSPD
27
DQ18
57
VDD
87
DQ34
117
SA0
147
DQ23#
177
A8
207
DQ39
237
SA1
28
DQ19
58
A5
88
DQ35
118
SCL
148
VSS
178
A6
208
VSS
238
SDA
29
VSS
59
A4
89
VSS
119
SA2
149
DQ28
179
VDD
209
DQ44
239
VSS
30
DQ24
60
VDD
90
DQ40
120
VTT
150
DQ29
180
A3
210
DQ45
240
VTT
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3
Symbol
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 5: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
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kdf18c512x72pz.pdf - Rev. G 4/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event: The EVENT# pin is asserted by the temperature sensor when crit(open drain) ical temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
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kdf18c512x72pz.pdf - Rev. G 4/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
DQ Map
DQ Map
Table 6: Component-to-Module DQ Map
Component
Reference
Number
Component
DQ
U1
U2
U3
U4
U5
U7
U8
U9
PDF: 09005aef83aa7149
kdf18c512x72pz.pdf - Rev. G 4/13 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
2
9
U11
0
61
228
1
1
4
1
62
233
2
3
10
2
60
227
3
0
3
3
63
234
0
10
18
0
53
219
1
9
13
1
54
224
2
11
19
2
52
218
3
8
12
3
55
225
0
18
27
0
45
210
1
17
22
1
46
215
2
19
28
2
44
209
3
16
21
3
47
216
0
26
36
0
37
201
1
25
31
1
38
206
2
27
37
2
36
200
3
24
30
3
39
207
0
CB2
45
0
CB5
159
1
CB1
40
1
CB6
164
2
CB3
46
2
CB4
158
3
CB0
39
3
CB7
165
0
34
87
0
29
150
1
33
82
1
30
155
2
35
88
2
28
149
3
32
81
3
31
156
0
42
96
0
21
141
1
41
91
1
22
146
2
43
97
2
20
140
3
40
90
3
23
147
0
50
105
0
13
132
1
49
100
1
14
137
2
51
106
2
12
131
3
48
99
3
15
138
U12
U13
U14
U16
U17
U18
U19
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
DQ Map
Table 6: Component-to-Module DQ Map (Continued)
Component
Reference
Number
Component
DQ
U10
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kdf18c512x72pz.pdf - Rev. G 4/13 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
58
114
U20
0
5
123
1
57
109
1
6
128
2
59
115
2
4
122
3
56
108
3
7
129
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
VSS
RS0#
DQS9
DQS9#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ4
DQ5
DQ6
DQ7
U1
ZQ
DQS1
DQS1#
VSS
DQ12
DQ13
DQ14
DQ15
ZQ
VSS
DQ
DQ
DQ
DQ
DQ20
DQ21
DQ22
DQ23
ZQ
VSS
DQ
DQ
DQ
DQ
ZQ
VSS
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
VSS
DQ44
DQ45
DQ46
DQ47
ZQ
VSS
DQ52
DQ53
DQ54
DQ55
ZQ
VSS
DQ
DQ
DQ
DQ
DQ60
DQ61
DQ62
DQ63
ZQ
VSS
DQ
DQ
DQ
DQ
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SPD EEPROM/
Temperature
sensor
SCL
EVT A0
SDA
A1 A2
SA0 SA1 SA2
EVENT#
ZQ
VSS
DQ
DQ
DQ
DQ
Command, control, address, and clock line terminations:
U14
ZQ
VSS
DQ
DQ
DQ
DQ
RS#, RCKE, RA[14:0],
RRAS#, RCAS#, RWE#,
RODT, RBA[2:0]
DDR3
SDRAM
VTT
DDR3
SDRAM
U13
CK
CK#
VDD
ZQ
VSS
DQ
DQ
DQ
DQ
VDDSPD
U12
ZQ
VSS
DQ
DQ
DQ
DQ
U11
SPD EEPROM/
Temperature Sensor
VDD
DDR3 SDRAM
VTT
Control, command and
address termination
VREFCA
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
ZQ
DQS17
DQS17#
VSS
DM CS# DQS DQS#
CB4
CB5
CB6
CB7
U5
ZQ
DQ
DQ
DQ
DQ
U16
ZQ
VSS
Note:
U15
U17
DQS16
DQS16#
DM CS# DQS DQS#
CB0
CB1
CB2
CB3
ZQ
DM CS# DQS DQS#
U10
DQS8
DQS8#
DDR3 SDRAM
VSS
DQ
DQ
DQ
DQ
DDR3 SDRAM
U18
DQS15
DQS15#
DM CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
U9
DQS7
DQS7#
CK
CK#
P
L
L
RESET#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
U8
DQ
DQ
DQ
DQ
DQ
DQ
VSS
DQS14
DQS14#
DM CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
ZQ
DQS13
DQS13#
DQ36
DQ37
DQ38
DQ39
ZQ
DQS6
DQS6#
a
n
d
CK0
CK0#
DM CS# DQS DQS#
U7
DQS5
DQS5#
U19
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ
DQ
DQ
DQ
DQS12
DQS12#
DQ28
DQ29
DQ30
DQ31
U4
DQS4
DQS4#
VSS
DQS11
DQS11#
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
ZQ
RS0#: DDR3 SDRAM
RBA[2:0]: DDR3 SDRAM
RA[14:0]: DDR3 SDRAM
RRAS#: DDR3 SDRAM
RCAS#: DDR3 SDRAM
RWE#: DDR3 SDRAM
RCKE0: DDR3 SDRAM
RODT0: DDR3 SDRAM
Err _Out #
R
e
g
i
s
t
e
r
DM CS# DQS DQS#
U3
DQS3
DQS3#
U20
DQS10
DQS10#
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ
DQ
DQ
DQ
S0#
BA[2:0]
A[15:0]
RAS#
CAS#
WE#
CKE0
ODT0
Par _In
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
U2
DQ
DQ
DQS2
DQS2#
U6
DM CS# DQS DQS#
DM CS# DQS DQS#
VSS
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
Registering Clock Driver Operation
Registered DDR3 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC standard
"Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications."
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The
register(s) and PLL reduce clock, control, command, and address signals loading by isolating DRAM from the system controller.
Parity Operations
The registering clock driver includes an even parity function for checking parity. The
memory controller accepts a parity bit at the Par_In input and compares it with the data
received on A[15:0], BA[2:0], RAS#, CAS#, and WE#. Valid parity is defined as an even
number of ones (1s) across the address and command inputs (A[15:0], BA[2:0], RAS#,
CAS#, and WE#) combined with Par_In. Parity errors are flagged on Err_Out#.
Address and command parity is checked during all DRAM operations and during control word WRITE operations to the registering clock driver. For SDRAM operations, the
address is still propagated to the SDRAM even when there is a parity error. When writing to the internal control words of the registering clock driver, the write will be ignored
if parity is not valid. For this reason, systems must connect the Par_In pins on the
DIMM and provide correct parity when writing to the registering clock driver control
word configuration registers.
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converts into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,
"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by
the customer. System READ/WRITE operations between the master (system logic) and
the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock)
SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently
disabling hardware write protection. For further information refer to Micron technical
note TN-04-42, "Memory Module Serial Presence-Detect."
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 7: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 8: Operating Conditions
Symbol Parameter
Min
Nom
Max
Units
1.283
1.35
1.45
V
1.425
1.5
1.575
V
VREFCA(DC) Input reference voltage command/
address bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
VREFDQ(DC) I/O reference voltage DQ bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
–600
–
600
mA
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
2
–
–
–
µA
3
VDD
VDD supply voltage
IVTT
Termination reference current from
VTT
VTT
Termination reference voltage (DC) –
command/address bus
II
Input leakage current;
Any input 0V ≤ VIN ≤
VDD; VREF input 0V ≤ VIN
≤ 0.95V (All other pins
not under test = 0V)
Address inputs, RAS#,
CAS#, WE#,
S#, CKE, ODT,
BA, CK, CK#
IOZ
Output leakage current; DQ, DQS,
0V ≤ VOUT ≤ VDD; DQ
DQS#
and ODT are disabled;
ODT is HIGH
–5
0
5
µA
IVREF
VREF supply leakage current;
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
–18
0
18
µA
Notes
1
TA
Module ambient
operating temperature
0
–
70
°C
4, 5
TC
DDR3 SDRAM component case operating temperature
0
–
95
°C
4, 5, 6
Notes:
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1. Module is backward-compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
2. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. Inputs are terminated to VDD/2. Input current is dependent on terminating resistance selected in register.
11
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Electrical Specifications
4. TA and TC are simultaneous requirements.
5. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s Web site.
6. The refresh rate is required to double when 85°C < TC ≤ 95°C.
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below.
Table 9: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G1
-093
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
IDD Specifications
IDD Specifications
Table 10: DDR3 IDD Specifications and Conditions – 4GB (Die Revision D)
Values are for the MT41K512M4 DDR3L SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4)
component data sheet
Parameter
Symbol
1333
1066
Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
1530
1350
mA
Operating current 1: One bank ACTIVATE-to-READto-PRECHARGE
IDD1
1800
1710
mA
Precharge power-down current: Slow exit
IDD2P0
216
216
mA
Precharge power-down current: Fast exit
IDD2P1
540
450
mA
Precharge quiet standby current
IDD2Q
630
540
mA
Precharge standby current
IDD2N
666
576
mA
Precharge standby ODT current
IDD2NT
810
720
mA
Active power-down current
IDD3P
630
540
mA
Active standby current
IDD3N
720
630
mA
Burst read operating current
IDD4R
2610
2250
mA
Burst write operating current
IDD4W
2790
2430
mA
Refresh current
IDD5B
3600
3420
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
216
216
mA
Self refresh temperature current (SRT-enabled):
MAX TC = 95°C
IDD6ET
270
270
mA
All banks interleaved read current
IDD7
6930
6030
mA
Reset current
IDD8
252
252
mA
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
IDD Specifications
Table 11: DDR3 IDD Specifications and Conditions – 4GB (Die Revision M)
Values are for the MT41K512M4 DDR3L SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4)
component data sheet
Parameter
Symbol
1600
1333
1066
Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
1080
990
900
mA
Operating current 1: One bank ACTIVATE-to-READto-PRECHARGE
IDD1
1350
1260
1170
mA
Precharge power-down current: Slow exit
IDD2P0
216
216
216
mA
Precharge power-down current: Fast exit
IDD2P1
594
504
414
mA
Precharge quiet standby current
IDD2Q
594
504
414
mA
Precharge standby current
IDD2N
630
540
450
mA
Precharge standby ODT current
IDD2NT
720
630
540
mA
Active power-down current
IDD3P
846
756
666
mA
Active standby current
IDD3N
936
846
756
mA
Burst read operating current
IDD4R
2250
1980
1710
mA
Burst write operating current
IDD4W
2070
1800
1530
mA
Refresh current
IDD5B
3420
3330
3240
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
216
216
216
mA
Self refresh temperature current (SRT-enabled):
MAX TC = 95°C
IDD6ET
270
270
270
mA
All banks interleaved read current
IDD7
3960
3690
3420
mA
Reset current
IDD8
252
252
252
mA
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
IDD Specifications
Table 12: DDR3 IDD Specifications and Conditions – 4GB (Die Revision K)
Values are for the MT41K512M4 DDR3L SDRAM only and are computed from values specified in the 2Gb (512 Meg x 4)
component data sheet
Parameter
Symbol
1600
1333
1066
Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
702
684
648
mA
Operating current 1: One bank ACTIVATE-to-READto-PRECHARGE
IDD1
882
846
774
mA
Precharge power-down current: Slow exit
IDD2P0
216
216
216
mA
Precharge power-down current: Fast exit
IDD2P1
252
252
252
mA
Precharge quiet standby current
IDD2Q
360
360
360
mA
Precharge standby current
IDD2N
378
378
378
mA
Precharge standby ODT current
IDD2NT
558
522
468
mA
Active power-down current
IDD3P
378
378
378
mA
Active standby current
IDD3N
576
540
504
mA
Burst read operating current
IDD4R
1620
1404
1152
mA
Burst write operating current
IDD4W
1674
1458
1242
mA
Refresh current
IDD5B
3240
3222
3186
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
216
216
216
mA
Self refresh temperature current (SRT-enabled):
MAX TC = 95°C
IDD6ET
270
270
270
mA
All banks interleaved read current
IDD7
2808
2700
2178
mA
Reset current
IDD8
252
252
252
mA
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Registering Clock Driver Specifications
Registering Clock Driver Specifications
Table 13: Registering Clock Driver Electrical Characteristics
SSTE32882 devices or equivalent; Note 1 applies to entire table
Parameter
Symbol
Pins
Min
Nom
DC supply voltage
VDD
–
Max
Units Notes
1.283
1.35
1.45
V
1.425
1.5
1.575
V
DC reference voltage
VREF
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
DC termination
voltage
VTT
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
AC high-level input
voltage
VIH(AC)
Control, command,
address
VREF + 175mV
–
VDD + 400mV
V
AC low-level input
voltage
VIL(AC)
Control, command,
address
–0.4
–
VREF - 175mV
V
DC high-level input
voltage
VIH(DC)
Control, command,
address
VREF + 100mV
–
VDD + 0.4
V
DC low-level input
voltage
VIL(DC)
Control, command,
address
–0.4
–
VREF - 100mV
V
High-level input
voltage
VIH(CMOS)
RESET#, MIRROR
0.65 × VDD
–
VDD
V
Low-level input
voltage
VIL(CMOS)
RESET#, MIRROR
0
–
0.35 × VDD
V
Differential input
crosspoint voltage
range
VIX(AC)
CK, CK#, FBIN, FBIN#
0.5 × VDD - 175mV
0.5 × VDD
0.5 × VDD + 175mV
V
Differential input
voltage
VID(AC)
CK, CK#
350
–
VDD + TBD
mV
High-level output
current
IOH
Err_Out#
–
–
TBD
mA
Low-level output
current
IOL
Err_Out#
TBD
–
TBD
mA
Notes:
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2
1. Timing and switching specifications for the register listed are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module.
2. The register is backward-compatible with 1.5V operation. Refer to device specification
for details and operation guidance.
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC
standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with
Temperature Sensor."
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 14: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
Supply current: VDD = 3.3V
IDD
–
2.0
mA
Input high voltage: Logic 1; SCL, SDA
VIH
VDDSPD x 0.7
VDDSPD + 1
V
Input low voltage: Logic 0; SCL, SDA
VIL
–0.5
VDDSPD x 0.3
V
Output low voltage: IOUT = 2.1mA
VOL
–
0.4
V
Input current
IIN
–5.0
5.0
µA
Temperature sensing range
–
–40
125
°C
Temperature sensor accuracy (class B)
–
–1.0
1.0
°C
Supply voltage
Table 15: Temperature Sensor and SPD EEPROM Serial Interface Timing
Parameter/Condition
Symbol
Min
Max
Units
tBUF
4.7
–
µs
SDA fall time
tF
20
300
ns
SDA rise time
tR
–
1000
ns
tHD:DAT
200
900
ns
Time bus must be free before a new transition can
start
Data hold time
Start condition hold time
tH:STA
4.0
–
µs
Clock HIGH period
tHIGH
4.0
50
µs
Clock LOW period
tLOW
4.7
–
µs
tSCL
10
100
kHz
Data setup time
tSU:DAT
250
–
ns
Start condition setup time
tSU:STA
4.7
–
µs
Stop condition setup time
tSU:STO
4.0
–
µs
SCL clock frequency
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
EVENT# Pin
The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD
EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be
set up in the sensor’s configuration register.
EVENT# has three defined modes of operation: interrupt mode, compare mode, and
critical temperature mode. Event thresholds are programmed in the 0x01 register using
a hysteresis. The alarm window provides a comparison window, with upper and lower
limits set in the alarm upper boundary register and the alarm lower boundary register,
respectively. When the alarm window is enabled, EVENT# will trigger whenever the
temperature is outside the MIN or MAX values set by the user.
The interrupt mode enables software to reset EVENT# after a critical temperature
threshold has been detected. Threshold points are set in the configuration register by
the user. This mode triggers the critical temperature limit and both the MIN and MAX of
the temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and returns to the logic HIGH state only when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
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4GB (x72, ECC, SR) 240-Pin 1.35V DDR3 VLP RDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR3 RDIMM
Front view
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
0.75 (0.03) R
(6X)
U1
U2
U3
U4
U5
2.5 (0.098) D
(2X)
U7
U6
U8
U9
U10
9.5 (0.374)
TYP
2.3 (0.091) TYP
0.76 (0.03) R
Pin 1
2.2 (0.087) TYP
Pin 120
1.0 (0.039)
TYP
1.45 (0.057) TYP
18.9 (0.744)
18.6 (0.732)
0.8 (0.031)
TYP
1.37 (0.054)
1.17 (0.046)
54.68 (2.15)
TYP
123.0 (4.84)
TYP
Back view
U15
U11
U12
U13
U14
U16
U17
U18
U19
U20
3.0 (0.118) 4X TYP
45°, 2X
3.05 (0.12) TYP
Pin 240
47.0 (1.85)
TYP
71.0 (2.79)
TYP
Notes:
Pin 121
5.0 (0.197) TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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