MT-056 TUTORIAL High Speed Voltage Feedback Op Amps In order to intelligently select the correct high speed op amp for a given application, an understanding of the various op amp topologies as well as the tradeoffs between them is required. The two most widely used topologies are voltage feedback (VFB) and current feedback (CFB). An overview of these topologies has been presented in previous tutorials (MT-050, MT051, MT-052), but the following discussion treats the frequency-related aspects of the two topologies in considerably more detail. HIGH SPEED VOLTAGE FEEDBACK (VFB) OP AMP TOPOLOGIES A voltage feedback (VFB) op amp is distinguished from a current feedback (CFB) op amp by circuit topology. The VFB op amp is certainly the most popular in low frequency applications, but the CFB op amp has some advantages at high frequencies. We will discuss high speed CFB in detail in Tutorial MT-057, but first the more traditional VFB architecture. Early IC voltage feedback op amps were made on "all NPN" processes. These processes were optimized for NPN transistors—the "lateral" PNP transistors had relatively poor performance. Some examples of these early VFB op amps which used these poor quality PNPs include the 709, the LM101 and the 741. Lateral PNPs were generally only used as current sources, level shifters, or for other non-critical functions. A simplified diagram of a typical VFB op amp manufactured on such a process is shown in Figure 1 below. CP i = v•gm - + v - gm - + IT v in v out a X1 + VREF R1 R2 fu = fu gm fCL = 2πCP 1+ R2 R1 IT SR = CP Figure 1: Voltage Feedback (VFB) Op Amp Designed on an "All NPN" IC Process Rev.0, 10/08, WK Page 1 of 10 MT-056 The input stage is a differential pair (sometimes called a long-tailed pair) consisting of either a bipolar pair (Q1, Q2) or a FET pair. This "gm" (transconductance) stage converts the small-signal differential input voltage, v, into a current, i, and its transfer function is measured in units of conductance, 1/Ω, (or mhos). The small-signal emitter resistance, re, is approximately equal to the reciprocal of the small-signal gm. The formula for the small-signal gm of a single bipolar transistor is given by the following equation: gm = 1 q (I C ) = q ⎛⎜ I T ⎞⎟ , or = re kT kT ⎝ 2 ⎠ ⎛ 1 ⎞⎛ I T ⎞ gm ≈ ⎜ ⎟⎜ ⎟ , ⎝ 26mV ⎠⎝ 2 ⎠ Eq. 1 Eq. 2 where IT is the differential pair tail current, IC is the collector quiescent bias current (IC = IT/2), q is the electron charge, k is Boltzmann's constant, and T is absolute temperature. At +25°C, VT = kT/q= 26 mV (often called the thermal voltage, VT). As we will see shortly, the amplifier unity gain-bandwidth product, fu, is equal to gm/2πCP, where the capacitance CP is used to set the dominant pole frequency. For this reason, the tail current, IT, is made proportional to absolute temperature (PTAT). This current tracks the variation in re with temperature thereby making gm independent of temperature. It is relatively easy to make CP reasonably constant over temperature. The Q2 collector output of the gm stage drives the emitter of a lateral PNP transistor (Q3). It is important to note that Q3 is not used to amplify the signal, only to level shift, i.e., the signal current variation in the collector of Q2 appears at the collector of Q3. The collector current of Q3 develops a voltage across high impedance node A, and CP sets the dominant pole of the amplifier. Emitter follower Q4 provides a low impedance output. The effective load at the high impedance node A can be represented by a resistance, RT, in parallel with the dominant pole capacitance, CP. The small-signal output voltage, vout, is equal to the small-signal current, i, multiplied by the impedance of the parallel combination of RT and CP. Figure 2 below shows a simple model for the single-stage amplifier and the corresponding Bode plot. The Bode plot is conveniently constructed on a log-log scale. Page 2 of 10 MT-056 i = v • gm + + v gm - vOUT X1 - RT CP vin NOISE GAIN = G = 1+ R1 R2 AO fO fO = fu = 6dB/OCTAVE f 1+ R2 R1 CL = R2 R1 1 2πR TC P gm 2πC P fu 1 + R2 R1 = fu G f u = UNITY GAIN FREQUENCY f 1 f CL = CLOSED LOOP BANDWIDTH Figure 2: Model and Bode Plot for a VFB Op Amp The low frequency breakpoint, fO, is given by: fo = 1 . 2πR T C P Eq. 3 Note that the high frequency response is determined solely by gm and CP: v out = v ⋅ gm . jωC P Eq. 4 The unity gain-bandwidth frequency, fu, occurs where |vout| = |v|. Letting ω = 2πfu and |vout| = |v|, Eq. 4 can be solved for fu, fu = gm . 2πC P Eq. 5 We can use feedback theory to derive the closed-loop relationship between the circuit's signal input voltage, vin, and its output voltage, vout: Page 3 of 10 MT-056 R2 v out R1 . = jωC P ⎛ R2 ⎞ v in 1+ ⎜1 + ⎟ gm ⎝ R1 ⎠ 1+ Eq. 6 At the op amp 3 dB closed-loop bandwidth frequency, fcl, the following is true: 2 πf cl C P ⎛ R2 ⎞ ⎜1 + ⎟ = 1 , and hence gm ⎝ R1 ⎠ ⎞ ⎛ ⎜ gm 1 ⎟ ⎟ , or ⎜ f cl = 2 πC P ⎜ 1 + R 2 ⎟ ⎟ ⎜ R1 ⎠ ⎝ f cl = fu . R2 1+ R1 Eq. 7 Eq. 8 Eq. 9 This demonstrates the fundamental property of VFB op amps: The closed-loop bandwidth multiplied by the closed-loop gain is a constant, i.e., the VFB op amp exhibits a constant gainbandwidth product over most of the usable frequency range. As noted previously, some VFB op amps (called de-compensated) are not stable at unity gain, but designed to be operated at some minimum (higher) amount of closed-loop gain. However, even for these op amps, the gain-bandwidth product is still relatively constant over the region of stability. Now, consider the following typical example: IT = 100 µA, CP = 2 pF. We find that: I / 2 50μA 1 = gm = T = VT 26mV 520Ω fu = gm 1 = = 153MHz . 2πC P 2π(520)( 2 ⋅ 10 −12 ) Eq. 10 Eq. 11 Now, we must consider the large-signal response of the circuit. The slew-rate, SR, is simply the total available charging current, IT/2, divided by the dominant pole capacitance, CP. For the example under consideration, I=C dv dv I = SR , SR = , C dt dt Page 4 of 10 Eq. 12 MT-056 I / 2 50μA SR = T = = 25V / μs . CP 2pF Eq. 13 The full-power bandwidth (FPBW) of the op amp can now be calculated from the formula: FPBW = SR 25V / μs = = 4 MHz, 2πA 2π ⋅ 1V Eq. 14 where A is the peak amplitude of the output signal. If we assume a 2 V peak-to-peak output sinewave (certainly a reasonable assumption for high speed applications), then we obtain a FPBW of only 4 MHz, even though the small-signal unity gain-bandwidth product is 153 MHz! For a 2 V p-p output sinewave, distortion will begin to occur much lower than the actual FPBW frequency. We must increase the SR by a factor of about 40 in order for the FPBW to equal 153 MHz. The only way to do this is to increase the tail current, IT, of the input differential pair by the same factor. This implies a bias current of 4 mA in order to achieve a FPBW of 160 MHz. We are assuming that CP is a fixed value of 2 pF and cannot be lowered by design. These calculations are summarized below in Figure 3. Assume that IT = 100µA, Cp = 2pF I 50μA 1 = gm = c = VT 26mV 520Ω fu = gm = 153MHz 2π Cp Slew Rate = SR = BUT FOR 2V PEAK-PEAK OUTPUT (A = 1V) SR FPBW = = 4MHz 2π A Must increase IT to 4mA to get FPBW = 160MHz!! Reduce gm by adding emitter degeneration resistors Figure 3: VFB Op Amp Bandwidth And Slew Rate Calculations In practice, the FPBW of the op amp should be approximately 5 to 10 times the maximum output frequency in order to achieve acceptable distortion performance (typically 55-80 dBc @ 5 to 20 MHz, but actual system requirements vary widely). Notice, however, that increasing the tail current causes a proportional increase in gm and hence fu. In order to prevent possible instability due to the large increase in fu, gm can be reduced by inserting resistors in series with the emitters of Q1 and Q2 (this technique, called emitter degeneration, also serves to linearize the gm transfer function and thus also lowers distortion). Page 5 of 10 MT-056 This analysis points out that a major inefficiency of conventional bipolar voltage feedback op amps is their inability to achieve high slew rates without proportional increases in quiescent current (assuming that CP is fixed, and has a reasonable minimum value of 2 or 3 pF). This of course is not meant to say that high speed op amps designed using this architecture are deficient, just that there are circuit design techniques available which allow equivalent performance at much lower quiescent currents. This is extremely important in portable battery operated equipment where every milliwatt of power dissipation is critical. VFB OP AMPS DESIGNED ON COMPLEMENTARY BIPOLAR PROCESSES With the advent of complementary bipolar (CB) processes having high quality PNP transistors as well as NPNs, VFB op amp configurations such as the one shown in the simplified diagram in Figure 4 below became popular. +VS D1 Q3 Q4 + Q1 OUTPUT BUFFER Q2 X1 C P - I T -VS Figure 4: VFB op amp using two gain stages Notice that the input differential pair (Q1, Q2) is loaded by a current mirror (Q3 and D1). We show D1 as a diode for simplicity, but it is actually a diode-connected PNP transistor (matched to Q3) with the base and collector connected to each other. This simplification will be used in many of the circuit diagrams to follow in this section. The common emitter transistor, Q4, provides a second voltage gain stage. Since the PNP transistors are fabricated on a complementary bipolar process, they are high quality and matched to the NPNs, and therefore suitable for voltage gain. The dominant pole of the Fig. 4 amplifier is set by CP, and the combination of the gain stage, Q4 and local feedback capacitor CP is often referred to as a Miller Integrator. The unity-gain output buffer is usually a complementary emitter follower. Page 6 of 10 MT-056 A model for this two-stage VFB op amp is shown in Figure 5 below. Notice that the unity gainbandwidth frequency, fu, is still determined by the input stage gm and the dominant pole capacitance, CP. The second gain stage increases the dc open-loop gain, but maximum slew rate is still limited by the input stage tail current as: SR = IT/CP. CP i = v•gm - + v - gm - + IT v in v out a X1 + VREF R1 R2 fu = fu gm fCL = 2πCP 1+ R2 R1 IT SR = CP Figure 5: Model for Two Stage VFB Op Amp A two-stage amplifier topology such as this is widely used throughout the IC industry in VFB op amps, both precision and high speed. Another popular VFB op amp architecture is the folded cascode as shown in Figure 6. An industry-standard video amplifier family (the AD847) is based on this architecture. This circuit also takes advantage of the fast PNPs available on a CB process. The differential signal currents in the collectors of Q1 and Q2 are fed to the emitters of a PNP cascode transistor pair (hence the term folded cascode). The collectors of Q3 and Q4 are loaded with the current mirror, D1 and Q5, and voltage gain is developed at the Q4-Q5 node. This single-stage architecture uses the junction capacitance at the high-impedance node for compensation (CSTRAY). Some variations of the design bring this node to an external pin so that additional external capacitance can be added if desired. Page 7 of 10 MT-056 +VS 2IT 2IT CCOMP IT IT Q4 Q3 + Q2 Q1 VBIAS X1 CSTRAY Q5 2IT AC GROUND D1 -VS Figure 6: AD847-Family Folded Cascode Simplified Circuit With no emitter degeneration resistors in Q1 and Q2, and no additional external compensating capacitance, this circuit is only stable for high closed-loop gains. However, unity-gain compensated versions of this family are available which have the appropriate amount of emitter degeneration. The availability of JFETs on a CB process allows not only low input bias current but also improvements in the slew rate tradeoff, which must be made between gm and IT found in bipolar input stages. Figure 7 shows a simplified diagram of the AD845 16 MHz op amp. JFETs have a much lower gm per mA of tail current than a bipolar transistor. This lower gm of the FET allows the input tail current (hence the slew rate) to be increased, without having to increase CP to maintain stability. +VS D1 Q5 Q6 Q3 Q4 VBIAS Q1 + CP X1 Q2 - -VS Figure 7: AD845 BiFET 16MHz Op Amp Simplified Circuit Page 8 of 10 MT-056 The unusual thing about this seemingly poor performance of the JFET is that it is exactly what is needed for a fast, high SR input stage. For a typical JFET, the value of gm is approximately Is/1V (Is is the source current), rather than Ic/26mV for a bipolar transistor, i.e., the FET gm is about 40 times lower. This allows much higher tail currents (and higher slew rates) for a given gm when JFETs are used as the input stage. Until recently, op amp designers had to make the above tradeoffs between the input gm stage quiescent current and the slew-rate and distortion performance. ADI has patented a circuit core which supplies current-on-demand, to charge and discharge the dominant pole capacitor, CP, while allowing the quiescent current to be small. The additional current is proportional to the fast slewing input signal and adds to the quiescent current. A simplified diagram of the basic core cell is shown in Figure 8 below. +VS Q5 Q7 Q1 Q2 - CP1 + X1 CP2 Q3 Q4 Q8 Q6 -VS Figure 8: "Quad-Core" VFB gm Stage forCurrent-on-Demand The quad-core (gm stage) consists of transistors Q1, Q2, Q3, and Q4 with their emitters connected together as shown. Consider a positive step voltage on the inverting input. This voltage produces a proportional current in Q1 that is mirrored into CP1 by Q5. The current through Q1 also flows through Q4 and CP2. At the dynamic range limit, Q2 and Q3 are correspondingly turned off. Notice that the charging and discharging current for CP1 and CP2 is not limited by the quad core bias current. In practice, however, small current-limiting resistors are required forming an "H" resistor network as shown. Q7 and Q8 form the second gain stage (driven differentially from the collectors of Q5 and Q6), and the output is buffered by a unity-gain complementary emitter follower. Page 9 of 10 MT-056 The quad core configuration is patented (see Reference 1), as well as the circuits that establish the quiescent bias currents (not shown in Fig. 8). The "quad core" is also often referred to as an "H-Bridge" core. A number of VFB op amps using this proprietary configuration have been released and have unsurpassed high frequency low distortion performance, bandwidth, and slew rate at low quiescent current levels. Figure 9 lists a few of the voltage feedback op amps using this architecture for comparison. LISTED IN ORDER OF DECREASING SUPPLY CURRENT BANDWIDTH SLEWRATE PART # ISY / AMP AD8045 (1) 19mA 1000MHz 1350V/µs ADA4899-1 (1) 16.2mA 600MHz 310V/µs AD8099 (1) 16mA 500MHz 1600V/µs AD8074 (3) 10mA 600MHz 1600V/µs AD8057 (1) 7.5mA 325MHz 1150V/µs AD8038 (1) 1.5mA 350MHz 425V/µs Number in ( ) indicates single, dual, triple, or quad Figure 9: Some High Speed VFB Op Amps REFERENCES 1. Hank Zumbahlen, Basic Linear Design, Analog Devices, 2006, ISBN: 0-915550-28-1. Also available as Linear Circuit Design Handbook, Elsevier-Newnes, 2008, ISBN-10: 0750687037, ISBN-13: 9780750687034. Chapter 1. 2. Walter G. Jung, Op Amp Applications, Analog Devices, 2002, ISBN 0-916550-26-5, Also available as Op Amp Applications Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7844-5. Chapter 1. Copyright 2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Tutorials. Page 10 of 10

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