Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 TPS65982 USB Type-C and USB PD Controller, Power Switch, and High Speed Multiplexer 1 Features 3 Description • The TPS65982 is a stand-alone USB Type-C & Power Delivery (PD) controller providing cable plug and orientation detection at the USB Type-C connector. Upon cable detection, the TPS65982 communicates on the CC wire using the USB PD protocol. When cable detection and USB PD negotiation are complete, the TPS65982 enables the appropriate power path and configures alternate mode settings for internal and (optional) external multiplexers. • • • • • USB Power Delivery (PD) Controller – Mode Configuration for Source (Host), Sink (Device), or Source-Sink – Bi-Phase Marked Encoding/Decoding (BMC) – Physical Layer (PHY) Protocol – Policy Engine – Configurable at Boot and Host-Controlled USB Type-C Specification Compliant – Detect USB Cable Plug Attach – Cable Orientation and Role Detection – Assign CC and VCONN Pins – Advertise Default, 1.5 A or 3 A for Type-C Power Port Power Switch – 5-V, 3-A Switch to VBUS for Type-C Power – 5-V to 20-V, 3-A Bidirectional Switch to or from VBUS for USB PD Power – 5-V, 600-mA Switches for VCONN – Over-Current Limiter, Overvoltage Protector – Slew Rate Control – Hard Reset Support Port Data Multiplexer – USB 2.0 HS Data, UART Data, and Low Speed Endpoint – Sideband Use Data for Alternate Modes (DisplayPort and Thunderbolt™) Power Management – Gate Control and Current Sense for External 5-V to 20-V, 5-A Bi-directional Switch (Back-toBack NFETs) – Power Supply from 3.3-V or VBUS Source – 3.3-V LDO Output for Dead Battery Support BGA MicroStar Junior Package – 0.5-mm Pitch – Through-Hole Via Compatible for All Pins 2 Applications • • • • • • • Notebook Computers Tablets and Ultrabooks Docking Systems Charger Adapters USB PD Hosts, Devices, and Dual-Role Ports USB PD-Enabled Bus-Powered Devices DisplayPort, Thunderbolt™ and HDMI The mixed-signal front end on the CC pins advertises default (500 mA), 1.5 A or 3 A for Type-C power sources, detects a plug event and determines the USB Type-C cable orientation, and autonomously negotiates USB PD contracts by adhering to the specified bi-phase marked coding (BMC) and physical layer (PHY) protocol. The port power switch provides up to 3 A downstream at 5 V for legacy and Type-C USB power. An additional bi-directional switch path provides USB PD power up to 3 A at a maximum of 20 V as either a source (host), sink (device), or source-sink. The TPS65982 is also an Upstream-Facing Port (UFP), Downstream-Facing Port (DFP), or Dual-Role Port for data. The port data multiplexer passes data to or from the top or bottom D+/D– signal pair at the port for USB 2.0 HS and has a USB 2.0 Low Speed Endpoint. Additionally, the Sideband-Use (SBU) signal pair is used for auxiliary or Alternate Modes of communication (DisplayPort or Thunderbolt™, for example). The power management circuitry utilizes a 3.3 V inside the system and also uses VBUS to start up and negotiate power for a dead-battery or no-battery condition. Device Information(1) PART NUMBER PACKAGE TPS65982 BODY SIZE (NOM) BGA (96) 6.00 mm x 6.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 5A 5 -20 V External FET Sense and CTRL 5 -20 V VBUS 3A 5V 3A 3.3 V Host Host Interface Type -C Cable Detection and USB PD Controller CC1/2 2 CC/VCONN USB Type-C Connector TPS65982 USB2.0 & Sideband-Use Data High Speed Mux Alternate Mode Mux Ctrl SEL EN POL 1 USB_TP/TN USB_BP /BN 2 SBU1/2 2 2 D+/D+/SBU1 /2 GND SuperSpeed Mux 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.21 SPI Master Characteristics ................................... 22 6.22 Single-Wire Debugger (SWD) Timing Requirements........................................................... 22 6.23 BUSPOWERZ Configuration Requirements ......... 23 6.24 HPD Timing Requirements and Characteristics ... 23 6.25 Thermal Shutdown Characteristics ....................... 23 6.26 Oscillator Requirements and Characteristics........ 23 6.27 Typical Characteristics .......................................... 24 1 1 1 2 3 7 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 8 Power Supply Requirements and Characteristics..... 9 Power Supervisor Characteristics........................... 10 Power Consumption Characteristics....................... 10 Cable Detection Characteristics.............................. 11 USB-PD Baseband Signal Requirements and Characteristics ......................................................... 12 6.10 USB-PD TX Driver Voltage Adjustment Parameter ................................................................ 12 6.11 Port Power Switch Characteristics........................ 13 6.12 Port Data Multiplexer Switching and Timing Characteristics ......................................................... 16 6.13 Port Data Multiplexer Clamp Characteristics ........ 18 6.14 Port Data Multiplexer SBU Detection Requirements........................................................... 18 6.15 Port Data Multiplexer Signal Monitoring Pull-Up and Pull-Down Characteristics ........................................ 18 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics .................................................. 18 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics........................... 19 6.18 Analog-to-Digital Converter (ADC) Characteristics ......................................................... 19 6.19 Input/Output (I/O) Requirements and Characteristics ......................................................... 19 6.20 I2C Slave Requirements and Characteristics........ 21 7 8 Parameter Measurement Information ................ 25 Detailed Description ............................................ 28 8.1 8.2 8.3 8.4 8.5 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming .......................................................... 28 29 29 66 73 Application and Implementation ........................ 78 9.1 Application Information............................................ 78 9.2 Typical Application .................................................. 78 10 Power Supply Recommendations ..................... 88 10.1 3.3 V Power .......................................................... 88 10.2 1.8 V Core Power.................................................. 88 10.3 VDDIO................................................................... 88 11 Layout................................................................... 90 11.1 Layout Guidelines ................................................. 90 11.2 Layout Example .................................................... 93 12 Device and Documentation Support ............... 108 12.1 12.2 12.3 12.4 12.5 12.6 Device Support.................................................... Documentation Support ...................................... Community Resources........................................ Trademarks ......................................................... Electrostatic Discharge Caution .......................... Glossary .............................................................. 108 108 108 108 108 108 13 Mechanical, Packaging, and Orderable Information ......................................................... 108 4 Revision History Changes from Original (March 2015) to Revision A • 2 Page Initial release of Production Datasheet................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 5 Pin Configuration and Functions ZQZ BGA MicroStar Junior (96) Top View 1 2 3 4 5 6 7 8 9 10 11 A GND LDO_1V8D SPI_CLK SPI_MISO I2C_SDA2 PP_HV PP_HV PP_HV HV_GATE2 SENSEN PP_5V0 A B VDDIO GPIO0 SPI_SSZ SPI_MOSI I2C_SCL2 I2C_IRQ2Z PP_HV GND HV_GATE1 SENSEP PP_5V0 B C I2C_IRQ1Z GPIO1 GPIO4 PP_5V0 C D I2C_SDA1 I2C_SCL1 E LDO_BMC UART_TX F I2C_ADDR G DEBUG_CTL2 HRESET GPIO7 GND GPIO2 PP_5V0 D DEBUG_CTL1 GND GND GND GND GPIO5 MRESET E UART_RX SWD_DAT GND GND GND GND BUSPOWERZ RESETZ F LDO_3V3 R_OSC SWD_CLK GND GND GND GND GPIO6 GPIO3 G H VIN_3V3 VOUT_3V3 GND GND GPIO8 SS GND PP_CABLE VBUS H J AUX_P AUX_N VBUS VBUS J K LDO_1V8A DEBUG2 DEBUG4 LSX_P2R USB_RP_N C_USB_TP C_USB_BP C_SBU1 RPD_G1 RPD_G2 VBUS K L GND DEBUG1 DEBUG3 LSX_R2P USB_RP_P C_USB_TN C_USB_BN C_SBU2 C_CC1 C_CC2 NC L 1 2 3 4 5 6 7 8 9 10 11 High Power Low Power Ground GPIOs Application Specific No Connect Pin Functions PIN NAME NO. I/O POR STATE DESCRIPTION HIGH CURRENT POWER PINS PP_5V0 A11, B11, C11, D11 Power NA 5 V supply for VBUS. Bypass with capacitance CPP_5V0 to GND. Tie pin to GND when unused PP_HV A6, A7, A8, B7 Power NA HV supply for VBUS. Bypass with capacitance CPP_HV to GND. Tie pin to GND when unused H10 Power NA 5 V supply for C_CC pins. Bypass with capacitance CPP_CABLE to GND when not tied to PP_5V0. Tie pin to PP_5V0 when unused. H11, J10, J11, K11 Power NA 5 V output from PP_5V0. Input or output from PP_HV up to 20 V. Bypass with capacitance CVBUS to GND. PP_CABLE VBUS Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 3 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN NAME NO. I/O POR STATE DESCRIPTION LOW CURRENT POWER PINS VIN_3V3 H1 Power NA Supply for core circuitry and I/O. Bypass with capacitance CVIN_3V3 to GND. VDDIO B1 Power NA VDD for I/O. Some I/Os are reconfigurable to be powered from VDDIO instead of LDO_3V3. When VDDIO is not used, tie pin to LDO_3V3. When not tied to LDO_3V3 and used as a supply input, bypass with capacitance CVDDIO to GND. VOUT_3V3 H2 Power NA Output of supply switched from VIN_3V3. Bypass with capacitance COUT_3V3 to GND. Float pin when unused. LDO_3V3 G1 Power NA Output of the VBUS to 3.3 V LDO or connected to VIN_3V3 by a switch. Main internal supply rail. Used to power external flash memory. Bypass with capacitance CLDO_3V3 to GND. LDO_1V8A K1 Power NA Output of the 3.3 V or 1.8 V LDO for Core Analog Circuits. Bypass with capacitance CLDO_1V8A to GND. LDO_1V8D A2 Power NA Output of the 3.3 V or 1.8 V LDO for Core Digital Circuits. Bypass with capacitance CLDO_1V8D to GND. LDO_BMC E1 Power NA Output of the USB-PD BMC transceiver output level LDO. Bypass with capacitance CLDO_BMC to GND. C_CC1 L9 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC1 to GND. C_CC2 L10 Analog I/O Hi-Z Output to Type-C CC or VCONN pin. Filter noise with capacitance CC_CC2 to GND. RPD_G1 K9 Analog I/O Hi-Z Tie pin to C_CC1 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise. RPD_G2 K10 Analog I/O Hi-Z Tie pin to C_CC2 when configured to receive power in dead-battery or no-power condition. Tie pin to GND otherwise. C_USB_TP K6 Analog I/O Hi-Z Port side Top USB D+ connection to Port Multiplexer. C_USB_TN L6 Analog I/O Hi-Z Port side Top USB D- connection to Port Multiplexer. C_USB_BP K7 Analog I/O Hi-Z Port side Bottom USB D+ connection to Port Multiplexer. C_USB_BN L7 Analog I/O Hi-Z Port side Bottom USB D- connection to Port Multiplexer. C_SBU1 K8 Analog I/O Hi-Z Port side Sideband Use connection of Port Multiplexer. C_SBU2 L8 Analog I/O Hi-Z Port side Sideband Use connection of Port Multiplexer. TYPE-C PORT PINS PORT MULTIPLEXER PINS SWD_DATA F4 Digital I/O Resistive Pull High SWD serial data. Float pin when unused. SWD_CLK G4 Digital Input Resistive Pull High SWD serial clock. Float pin when unused. UART_RX F2 Digital Input Digital Input UART serial receive data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982 and ground pin through a 100 kΩ resistance. UART_TX E2 Digital Output UART_RX UART serial transmit data. Connect pin to another TPS65982 UART_TX to share firmware. Connect UART_RX to UART_TX when not connected to another TPS65982. USB_RP_P L5 Analog I/O Hi-Z System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1 kΩ and 5 MΩ resistance when unused. USB_RP_N K5 Analog I/O Hi-Z System side USB2.0 high-speed connection to Port Multiplexer. Ground pin with between 1 kΩ and 5 MΩ resistance when unused. LSX_R2P L4 Digital Input Digital Input System side low speed TX from system to port. This pin is configurable to be an input to the digital core or the crossbar multiplexer to the port. Ground pin with between 1 kΩ and 5 MΩ resistance when unused. LSX_P2R K4 Digital Output Hi-Z System side low speed RX to system from port. This pin is configurable to be an output from the digital core or the crossbar multiplexer from the port. Float pin when unused. AUX_P J1 Analog I/O Hi-Z System side DisplayPort connection to Port Multiplexer. Ground pin with between 1 kΩ and 5 MΩ resistance when unused. AUX_N J2 Analog I/O Hi-Z System side DisplayPort connection to Port Multiplexer. Ground pin with between 1 kΩ and 5 MΩ resistance when unused. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Pin Functions (continued) PIN NAME I/O NO. POR STATE DESCRIPTION EXTERNAL HV FET CONTROL/SENSE PINS AND SOFT START SENSEP B10 Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused. SENSEN A10 Analog Input Analog Input Positive sense for external high voltage power path current sense resistance. Short pin to VBUS when unused. HV_GATE1 B9 Analog Output Short to SENSEP External NFET gate control for high voltage power path. Float pin when unused. HV_GATE2 A9 Analog Output Short to VBUS External NFET gate control for high voltage power path. Float pin when unused. SS H7 Analog Output Driven Low Soft Start. Tie pin to capacitance CSS to ground. DIGITAL CORE I/O AND CONTROL PINS R_OSC G2 Analog I/O Hi-Z External resistance setting for oscillator accuracy. Connect R_OSC to GND through resistance RR_OSC. GPIO0 (HD3 AMSEL) B2 Digital I/O Hi-Z General Purpose Digital I/O 0. Alternate mode select signal to external Super Speed multiplexer (tri-state capable with pull-up and pull-down resistors). Ground pin with a 1-MΩ resistor when unused in the application. GPIO1 (CONFIG0) C2 Digital I/O Hi-Z General Purpose Digital I/O 1. Must be tied high or low through a 1 kΩ pull-up or pull-down resistor when used as a configuration input. GPIO2 D10 Digital I/O Hi-Z General Purpose Digital I/O 2. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. GPIO3 (HD3 EN) G11 Digital I/O Hi-Z General Purpose Digital I/O 3. Enable signal to external Super Speed multiplexer. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. GPIO4 (HPD TXRX) C10 Digital I/O Hi-Z General Purpose Digital I/O 4. Configured as Hot Plug Detect (HPD) TX and/or HPD RX when DisplayPort Mode supported. Ground pin with a 1-MΩ resistor when unused in the application. GPIO5 (HPD RX) E10 Digital I/O Hi-Z General Purpose Digital I/O 5. Can be configured as Hot Plug Detect (HPD) RX when DisplayPort Mode supported. Must be tied high or low through a 1 kΩ pull-up or pull-down resistor when used as a configuration input. Ground pin with a 1 MΩ resistor when unused in the application. GPIO6 G10 Digital I/O Hi-Z General Purpose Digital I/O 6. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. GPIO7 D7 Digital I/O Hi-Z General Purpose Digital I/O 7. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. GPIO8 H6 Digital I/O Hi-Z General Purpose Digital I/O 8. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. RESETZ (GPIO9) F11 Digital I/O Push-Pull Output (Low) BUSPOWERZ (GPIO10) F10 Analog Input Input (Hi-Z) General Purpose Digital I/O 10. Sampled by ADC at boot. Tie pin to LDO_3V3 through a 100-kΩ resistor to disable PP_HV and PP_EXT power paths during deadbattery or no-battery boot conditions. Refer to the BUSPOWERZ table for more details. MRESET (GPIO11) E11 Digital I/O Hi-Z General Purpose Digital I/O 11. Forces RESETZ to assert. By default, this pin asserts RESETZ when pulled high. The pin can be programmed to assert RESETZ when pulled low. Ground pin with a 1MΩ resistor when unused in the application. DEBUG4 (GPIO12, CONFIG2) K3 Digital I/O Hi-Z General Purpose Digital I/O 12. Must be tied high or low through a 1-kΩ pull-up or pull-down resistor when used as a configuration input. DEBUG3 (GPIO13, CONFIG1) L3 Digital I/O Hi-Z General Purpose Digital I/O 13. Must be tied high or low through a 1-kΩ pull-up or pull-down resistor when used as a configuration input. DEBUG2 (GPIO14, HD3 POL) K2 Digital I/O Hi-Z General Purpose Digital I/O 14. Polarity signal to external Super Speed multiplexer. Float pin if it is configured as a push-pull output in the application. Ground pin with a 1-MΩ resistor when unused in the application. DEBUG1 (GPIO15) L2 Digital I/O Hi-Z General Purpose Digital I/O 15. Ground pin with a 1-MΩ resistor when unused in the application. DEBUG_CTL1 (GPIO16, I2C ADDR B4) E4 Digital I/O Hi-Z General Purpose Digital I/O 16. At power-up, pin state is sensed to determine bit 4 of the I2C address. General Purpose Digital I/O 9. Active low reset output when VOUT_3V3 is low (driven low on start-up). Float pin when unused. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 5 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/O POR STATE DESCRIPTION D5 Digital I/O Hi-Z General Purpose Digital I/O 17. At power-up, pin state is sensed to determine bit 5 of the I2C address. HRESET D6 Digital I/O Hi-Z Active high hardware reset input. Will re-load settings from external flash memory. Ground pin when HRESET functionality will not be used. I2C_SDA1 D1 Digital I/O Digital Input I2C port 1 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10 kΩ resistance when used or unused. I2C_SCL1 D2 Digital I/O Digital Input I2C port 1 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10 kΩ resistance when used or unused. I2C_IRQ1Z C1 Digital Output Hi-Z I2C port 1 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused. I2C_SDA2 A5 Digital I/O Digital Input I2C port 2 serial data. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10 kΩ resistance when used or unused. I2C_SCL2 B5 Digital I/O Digital Input I2C port 2 serial clock. Open-drain output. Tie pin to LDO_3V3 or VDDIO (depending on configuration) through a 10 kΩ resistance when used or unused. I2C_IRQ2Z B6 Digital Output Hi-Z I2C port 2 interrupt. Active low. Implement externally as an open drain with a pull-up resistance. Float pin when unused. I2C_ADDR F1 Analog I/O Analog Input Sets the I2C address for both I2C ports as well as determine the master and slave devices for memory code sharing. SPI_CLK A3 Digital Output Digital Input SPI serial clock. Ground pin when unused SPI_MOSI B4 Digital Output Digital Input SPI serial master output to slave. Ground pin when unused. SPI_MISO A4 Digital Input Digital Input SPI serial master input from slave. This pin is used during boot sequence to determine if the flash memory is valid. Refer to the Boot Code section for more details. Ground pin when unused. SPI_SSZ B3 Digital Output Digital Input SPI slave select. Ground pin when unused. A1, B8, D8, E5, E6, E7, E8, F5, F6, F7, F8, G5, G6, G7, G8, H4, H5, H8, L1 Ground NA Ground. Connect all balls to ground plane. L11 Blank NA Populated Ball that must remain unconnected. C3, C4, C5, C6, C7, C8, C9, D3, D4, D9, E3, E9, F3, F9, G3, G9, H3, H9, J3, J4, J5, J6, J7, J8, J9 Blank NA Unpopulated Ball for A1 marker and unpopulated inner ring. NAME NO. DEBUG_CTL2 (GPIO17, I2C ADDR B5) GROUND AND NO CONNECT PINS GND NC No Ball 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VI VIO Input voltage range (2) Output voltage range (2) (1) MIN MAX PP_CABLE, PP_5V0 –0.3 6 VIN_3V3 –0.3 3.6 SENSEP, SENSEN (3) –0.3 24 VDDIO, UART_RX –0.3 LDO_3V3 + 0.3 LDO_1V8A, LDO_1V8D, LDO_BMC, SS –0.3 2 LDO_3V3 –0.3 3.45 VOUT_3V3, RESETZ, I2C _IRQ1Z, I2C_IRQ2Z, SPI_MOSI, SPI_CLK, SPI_SSZ, LSX_P2R, SWD_CLK, UART_TX –0.3 LDO_3V3 + 0.3 HV_GATE1, HV_GATE2 –0.3 30 HV_GATE1 (relative to SENSEP), –0.3 6 PP_HV, VBUS (2) –0.3 24 I2C_SDA1, I2C_SCL1, SWD_DATA, SPI_MISO, I2C_SDA2, I2C_SCL2, LSX_R2P, USB_RP_P, USB_RP_N, AUX_N, AUX_P, DEBUG1, DEBUG2, DEBUG3, DEBUG4, DEBUG_CTL1, DEBUG_CTL2, GPIOn, MRESET, BUSPOWERZ, GPIO0-8 –0.3 LDO_3V3 + 0.3 R_OSC, I2C_ADDR UNIT V V HV_GATE2 (relative to VBUS) VIO I/O voltage range (2) –0.3 2 C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Open) –2 6 C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU2, C_SBU1 (Switches Closed) –0.3 6 C_CC1, C_CC2, RPD_G1, RPD_G2 V –0.3 6 TJ Operating junction temperature –10 125 °C Tstg Storage temperature –55 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. The 24 V maximum is based on keeping HV_GATE1/2 at or below 30 V. Fast voltage transitions (< 100 ns) may occur up to 30 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 7 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Input voltage range (1) VI MIN MAX VIN_3V3 2.85 3.45 PP_5V0 4.75 5.5 PP_CABLE 2.95 5.5 PP_HV 4.5 22 VDDIO 1.7 3.45 VBUS 4 22 –2 5.5 0 5.5 UNIT V VIO I/O voltage range (1) TA Ambient operating temperature range –10 85 °C TB Operating board temperature range –10 100 °C TJ Operating junction temperature range –10 125 °C C_USB_PT, C_USB_NT, C_USB_PB, C_USB_NB, C_SBU1, C_SBU2 C_CC1, C_CC2 (1) V All voltage values are with respect to network GND. All GND pins must be connected directly to the GND plane of the board. 6.4 Thermal Information TPS65982 THERMAL METRIC (1) ZQZ (BGA) UNIT 96 BALLS RθJA Junction-to-ambient thermal resistance 42.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.4 °C/W RθJB Junction-to-board thermal resistance 13.0 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 13.0 °C/W (1) 8 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 6.5 Power Supply Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT EXTERNAL VIN_3V3 Input 3.3-V supply 2.85 3.3 3.45 V PP_CABLE Input voltage to power C_CC pins. This input is also available to power core circuitry and the VOUT_3V3 output. 2.95 5 5.5 V VBUS Bi-direction DC bus voltage. Output from the TPS65982 or input to the TPS65982. 4 5 22 V PP_5V0 5V supply input to power VBUS. This supply does not power the TPS65982. 4.75 5 5.5 V 3.45 V 3.45 V 250 mV VDDIO (1) Optional supply for I/O cells. 1.7 VLDO_3V3 DC 3.3V generated internally by either a switch from VIN_3V3, an LDO from PP_CABLE, or an LDO from VBUS 2.7 VDO_LDO3V3 Drop Out Voltage of LDO_3V3 from PP_CABLE INTERNAL 3.3 ILOAD = 50 mA Drop Out Voltage of LDO_3V3 from VBUS 250 500 750 mV VLDO_1V8D DC 1.8V generated for internal digital circuitry. 1.7 1.8 1.9 V VLDO_1V8A DC 1.8V generated for internal analog circuitry. 1.7 1.8 1.9 V VLDO_BMC DC voltage generated on LDO_BMC. Setting for USB-PD. 1.05 1.125 1.2 V ILDO_3V3 DC current supplied by the 3.3V LDOs. This includes internal core power and external load on LDO_3V3. 50 mA ILDO_3V3EX External DC current supplied by LDO_3V3 IOUT_3V3 External DC current supplied by VOUT_3V3 ILDO_1V8D DC current supplied by LDO_1V8D. This is intended for internal loads only but small external loads may be added. ILDO_1V8DEX External DC current supplied by LDO_1V8D. ILDO_1V8A DC current supplied by LDO_1V8A. This is intended for internal loads only but small external loads may be added. ILDO_1V8AEX 10 mA 100 mA 50 mA 5 mA 20 mA External DC current supplied by LDO_1V8A. 5 mA ILDO_BMC DC current supplied by LDO_BMC. This is intended for internal loads only. 5 mA ILDO_BMCEX External DC current supplied by LDO_BMC. 0 mA VFWD_DROP Forward voltage drop across VIN_3V3 to LDO_3V3 switch ILOAD = 50 mA 25 60 90 mV RIN_3V3 Input switch resistance from VIN_3V3 to LDO_3V3 VVIN_3V3 – VLDO_3V3 > 50 mV 0.5 1.1 1.75 Ω ROUT_3V3 Output switch resistance from VIN_3V3 to VOUT_3V3 0.35 0.7 Ω TR_OUT3V3 10-90% rise time on VOUT_3V3 from switch enable. 120 µs (1) CVOUT_3V3 = 1 μF 35 I/O buffers are not fail-safe to LDO_3V3. Therefore, VDDIO may power-up before LDO_3V3. When VDDIO powers up before LDO_3V3, the I/Os shall not be driven high. When VDDIO is low and LDO_3V3 is high, the I/Os may be driven high. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 9 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6.6 Power Supervisor Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT 2.2 2.325 2.45 V 80 150 mV 3.75 3.95 V 80 150 mV 2.5 2.625 2.75 20 50 80 PP_5V0 rising 3.5 3.725 3.95 V PP_5V0 falling 20 80 150 mV 24 V UV_LDO3V3 Under-voltage threshold for LDO_3V3. Locks out 1.8-V LDOs LDO_3V3 rising UVH_LDO3V3 Under-voltage hysteresis for LDO_3V3 LDO_3V3 falling 20 UV_VBUS_LDO Under-voltage threshold for VBUS to enable LDO VBUS rising 3.35 UVH_VBUS_LDO Under-voltage hysteresis for VBUS to enable LDO VBUS falling 20 UV_PCBL Under-voltage threshold for PP_CABLE PP_CABLE rising UVH_PCBL Under-voltage hysteresis for PP_PCABLE PP_CABLE falling UV_5V0 Under-voltage threshold for PP_5V0 UVH_5V0 Under-voltage hysteresis for PP_P5V0 OV_VBUS Over-voltage threshold for VBUS. This value is a 6-bit programmable threshold VBUS rising OVLSB_VBUS Over-voltage threshold step for VBUS. This value is the LSB of the programmable threshold VBUS rising OVH_VBUS Over-voltage hysteresis for VBUS VBUS falling, % of OV_VBUS UV_VBUS Under-voltage threshold for VBUS. This value is a 6-bit programmable threshold VBUS falling UVLSB_VBUS Under-voltage threshold step for VBUS. This value is the LSB of the programmable threshold VBUS falling UVH_VBUS Under-voltage hysteresis for VBUS VBUS rising, % of UV_VBUS 0.9% 1.3% 1.7% Setting 0 2.019 2.125 2.231 Setting 1 2.138 2.25 2.363 Setting 2 2.256 2.375 2.494 Setting 3 2.375 2.5 2.625 Setting 4 2.494 2.625 2.756 Setting 5 2.613 2.75 2.888 Setting 6 2.731 2.875 3.019 Setting 7 2.85 3 3.15 30 50 mV 75 μs 161.3 ms UVR_OUT3V3 Configurable under-voltage threshold for VOUT_3V3 rising. De-asserts RESETZ UVRH_OUT3V3 Under-voltage hysteresis for VOUT_3V3 falling. TUVRASSERT Delay from falling VOUT_3V3 or MRESET assertion to RESETZ asserting low TUVRDELAY Configurable delay from VOUT_3V3 to RESETZ deassertion. 5 328 0.9% 1.3% 2.5 mV 1.7% 18.21 249 OUT_3V3 falling 0 V mV V mV V 6.7 Power Consumption Characteristics (1) Recommended operating conditions; TA = 25°C (Room temperature) unless otherwise noted PARAMETER TEST CONDITION Sleep IVIN_3V3 Idle (2) (3) Active (4) (1) (2) (3) (4) 10 MIN TYP MAX UNIT VIN_3V3 = VDDIO = 3.45 V, VBUS = 0, PPCABLE = 0; 100-kHz Oscillator running 58 µA VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE= 0; 100-kHz Oscillator running, 48-MHz Oscillator running 1.66 mA VIN_3V3 = VDDIO = 3.45 V, VBUS=0, PPCABLE= 0; 100-kHz Oscillator running, 48-MHz Oscillator running 5.64 mA Application code can result in other power consumption measurements by adjusting enabled circuitry and clock rates. Application code also provisions the wake=up mechanisms (for example, I2C activity and GPIO activity). Sleep is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active. Idle is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, and a selectable clock to the digital core of 3 MHz or 4 MHz. Active is defined as Type-C cable detect activated as DFP or UFP, internal power management and supervisory functions active, all core functionality active, and the digital core is clocked at 12 MHz. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 6.8 Cable Detection Characteristics Recommended operating conditions; TA = -10 to 85 °C unless otherwise noted MIN TYP MAX UNIT IH_CC_USB Source Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising Default USB current to a peripheral device PARAMETER TEST CONDITIONS 73.6 80 86.4 μA IH_CC_1P5 Source Current through each C_CC pin when in a disconnected state when Configured as a DFP advertising 1.5 A to a UFP 169 180 191 μA IH_CC_3P0 Source Current through each C_CC pin when in a disconnected state and Configured as a DFP advertising 3.0 A to a UFP. 303 330 356 μA VD_CCH_USB Voltage Threshold for detecting a DFP attach when configured as a UFP and the DFP is advertising Default USB current source capability 0.15 0.2 0.25 V VD_CCH_1P5 Voltage Threshold for detecting a DFP advertising 1.5 A source capability when configured as a UFP 0.61 0.66 0.7 V VD_CCH_3P0 Voltage Threshold for detecting a DFP advertising 3 A source capability when configured as a UFP 1.169 1.23 1.29 V VH_CCD_USB Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising Default USB current source capability. IH_CC = IH_CC_USB 1.473 1.55 1.627 V VH_CCD_1P5 Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 1.5 A source capability IH_CC = IH_CC_1P5 1.473 1.55 1.627 V VH_CCD_3P0 Voltage Threshold for detecting a UFP attach when configured as a DFP and advertising 3.0 A source capability. IH_CC = IH_CC_3P0 VIN_3V3 ≥ 3.135 V 2.423 2.55 2.67 V VH_CCA_USB Voltage Threshold for detecting an active cable attach when configured as a DFP and advertising Default USB current capability. 0.15 0.2 0.25 V VH_CCA_1P5 Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 1.5 A capability. 0.35 0.4 0.45 V VH_CCA_3P0 Voltage Threshold for detecting active cables attach when configured as a DFP and advertising 3 A capability. 0.76 0.8 0.84 V RD_CC Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered. V = 1 V, 1.5 V 4.85 5.1 5.35 kΩ RD_CC_OPEN Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP. LDO_3V3 powered. V = 0 V to LDO_3V3 500 RD_DB Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when configured for dead battery (RPD_Gn tied to C_CCn). LDO_3V3 unpowered V = 1.5 V, 2.0 V RPD_Gn tied to C_CCn 4.08 RD_DB_OPEN Pull-down resistance through each C_CC pin when in a disconnect state and configured as a UFP when not configured for dead battery (RPD_Gn tied to GND). LDO_3V3 unpowered V = 1.5 V, 2.0 V RPD_Gn tied to GND 500 VTH_DB Threshold Voltage of the pull-down FET in series with RD during dead battery I_CC = 80 μA 0.5 0.9 1.2 V R_RPD Resistance between RPD_Gn and the gate of the pull-down FET 25 50 85 MΩ VIN_3V3 ≥ 3.135 V kΩ 5.1 6.12 kΩ Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 kΩ 11 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6.9 USB-PD Baseband Signal Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT COMMON PD_BITRATE PD data bit rate 270 300 330 Kbps UI (1) Unit interval (1/PD_BITRATE) 3.03 3.33 3.7 μs 25 pF CCBLPLUG Capacitance for a cable plug (each plug on a cable may have up to this value) (2) ZCABLE Cable characteristic impedance 32 65 Ω CRECEIVER (3) Receiver capacitance. Capacitance looking into C_CCn pin when in receiver mode. 70 120 pF ZDRIVER TX output impedance. Source output impedance at the Nyquist frequency of USB2.0 low speed (750kHz) while the source is driving the C_CCn line. 33 75 Ω TRISE Rise Time. 10% to 90% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask. 300 ns TFALL Fall Time. 90% to 10% amplitude points, minimum is under an unloaded condition. Maximum set by TX mask. 300 ns VRXTR Rx Receive Rising Input threshold 605 630 655 mV VRXTF Rx Receive Falling Input threshold 450 470 490 mV 20 μs TRANSMITTER RECEIVER NCOUNT Number of transitions for signal detection (number to count to detect non-idle bus). (4) TTRANWIN (4) Time window for detecting non-idle bus. 12 Does not include pull-up or pull-down resistance from cable detect. Transmitter is Hi-Z. ZBMCRX Receiver input impedance TRXFILTER (5) Rx bandwidth limiting filter. Time constant of a single pole filter to limit broadband noise ingression (1) (2) (3) (4) (5) 3 10 MΩ 100 ns UI denotes the time to transmit an un-encoded data bit not the shortest high or low times on the wire after encoding with BMC. A single data bit cell has duration of 1 UI, but a data bit cell with value 1 will contain a centrally place 01 or 10 transition in addition to the transition at the start of the cell. The capacitance of the bulk cable is not included in the CCBLPLUG definition. It is modeled as a transmission line. CRECEIVER includes only the internal capacitance on a C_CCn pin when the pin is configured to be receiving BMC data. External capacitance is needed to meet the required minimum capacitance per the USB-PD Specifications. It is recommended to add capacitance to bring the total pin capacitance to 300 pF for improved TX behavior. BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of NCOUNT transitions occur at the receiver within a time window of TTRANWIN. After waiting TTRANWIN without detecting NCOUNT transitions, the bus is declared idle. Broadband noise ingression is due to coupling in the cable interconnect. 6.10 USB-PD TX Driver Voltage Adjustment Parameter (1) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER MIN NOM MAX UNIT 1.615 1.7 1.785 V TX Transmit Peak Voltage 1.52 1.6 1.68 V TX Transmit Peak Voltage 1.425 1.5 1.575 V VTXP3 TX Transmit Peak Voltage 1.33 1.4 1.47 V VTXP4 TX Transmit Peak Voltage 1.235 1.3 1.365 V VTXP5 TX Transmit Peak Voltage 1.188 1.25 1.312 V VTXP6 TX Transmit Peak Voltage 1.14 1.2 1.26 V VTXP7 TX Transmit Peak Voltage 1.116 1.175 1.233 V VTXP8 TX Transmit Peak Voltage 1.092 1.15 1.208 V VTXP9 TX Transmit Peak Voltage 1.068 1.125 1.181 V VTXP0 TX Transmit Peak Voltage VTXP1 VTXP2 (1) 12 TEST CONDITION VTXP voltage settings are determined by application code and the setting used must meet the needs of the application and adhere to the USB-PD Specifications. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 USB-PD TX Driver Voltage Adjustment Parameter(1) (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN NOM MAX UNIT VTXP10 TX Transmit Peak Voltage 1.045 1.1 1.155 V VTXP11 TX Transmit Peak Voltage 1.021 1.075 1.128 V VTXP12 TX Transmit Peak Voltage 0.998 1.05 1.102 V VTXP13 TX Transmit Peak Voltage 0.974 1.025 1.076 V VTXP14 TX Transmit Peak Voltage 0.95 1 1.05 V VTXP15 TX Transmit Peak Voltage 0.903 0.95 0.997 V 6.11 Port Power Switch Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted TEST CONDITION (1) PARAMETER RPPCC PP_CABLE to C_CCn power switch resistance RPP5V PP_5V0 to VBUS power switch resistance RPPHV PP_HV to VBUS power switch resistance IHVACT Active quiescent current from PP_HV pin, EN_HV = 1 IHVSD Shutdown quiescent current from PP_HV pin, EN_HV = 0 IHVEXTACT Active quiescent current from SENSEP pin, EN_HV = 1 Configured as source Active quiescent current from VBUS pin, EN_HV = 1 Configured as sink IHVEXTSD Shutdown quiescent current from SENSEP pin, EN_HV = 0 IPP5VACT Active quiescent current from PP_5V0 IPP5VSD Shutdown quiescent current from PP_5V0 ILIMHV (2) (1) (2) MIN TYP MAX UNIT 312 mΩ 50 60 mΩ 95 135 mΩ 1 mA 100 μA 1 mA 3.5 mA 40 μA 1 mA 100 μA PP_HV current limit, setting 0 1.007 1.118 1.330 A PP_HV current limit, setting 1 1.258 1.398 1.638 A PP_HV current limit, setting 2 1.51 1.678 1.945 A PP_HV current limit, setting 3 1.761 1.957 2.153 A PP_HV current limit, setting 5 2.013 2.237 2.46 A PP_HV current limit, setting 6 2.265 2.516 2.768 A PP_HV current limit, setting 7 2.516 2.796 3.076 A PP_HV current limit, setting 8 2.768 3.076 3.383 A PP_HV current limit, setting 9 3.02 3.355 3.691 A PP_HV current limit, setting 10 3.271 3.635 3.998 A PP_HV current limit, setting 11 3.523 3.914 4.306 A PP_HV current limit, setting 12 3.775 4.194 4.613 A PP_HV current limit, setting 13 4.026 4.474 4.921 A PP_HV current limit, setting 14 4.278 4.753 5.228 A PP_HV current limit, setting 15 4.529 5.033 5.536 A PP_HV current limit, setting 16 5.033 5.592 6.151 A Maximum capacitance on VBUS when configured as a source must not exceed 12 µF. Settings selected automatically by application code for the current limit needed in the application. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 13 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Port Power Switch Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted TEST CONDITION (1) PARAMETER ILIMHVEXT (3) (2) ILIMPP5V (2) ILIMPPCC MIN TYP MAX UNIT PP_EXT current limit, setting 0 0.986 1.12 1.254 A PP_EXT current limit, setting 1 1.231 1.399 1.567 A PP_EXT current limit, setting 2 1.477 1.678 1.879 A PP_EXT current limit, setting 3 1.761 1.957 2.153 A PP_EXT current limit, setting 4 2.012 2.236 2.46 A PP_EXT current limit, setting 5 2.263 2.515 2.767 A PP_EXT current limit, setting 6 2.514 2.794 3.074 A PP_EXT current limit, setting 7 2.765 3.073 3.381 A PP_EXT current limit, setting 8 3.016 3.352 3.688 A PP_EXT current limit, setting 9 3.267 3.631 3.995 A PP_EXT current limit, setting 10 3.519 3.91 4.301 A PP_EXT current limit, setting 11 3.77 4.189 4.608 A PP_EXT current limit, setting 12 4.021 4.468 4.915 A PP_EXT current limit, setting 13 4.272 4.747 5.222 A PP_EXT current limit, setting 14 4.523 5.026 5.529 A PP_EXT current limit, setting 15 5.025 5.584 6.143 A PP_5V0 current limit, setting 0 1.006 1.118 1.330 A PP_5V0 current limit, setting 1 1.132 1.258 1.484 A PP_5V0 current limit, setting 2 1.258 1.398 1.638 A PP_5V0 current limit, setting 3 1.384 1.538 1.691 A PP_5V0 current limit, setting 4 1.51 1.677 1.845 A PP_5V0 current limit, setting 5 1.636 1.817 1.999 A PP_5V0 current limit, setting 6 1.761 1.957 2.153 A PP_5V0 current limit, setting 7 1.887 2.097 2.307 A PP_5V0 current limit, setting 8 2.013 2.237 2.46 A PP_5V0 current limit, setting 9 2.139 2.376 2.614 A PP_5V0 current limit, setting 10 2.265 2.516 2.768 A PP_5V0 current limit, setting 11 2.39 2.656 2.922 A PP_5V0 current limit, setting 12 2.516 2.796 3.075 A PP_5V0 current limit, setting 13 2.642 2.936 3.229 A PP_5V0 current limit, setting 14 2.768 3.075 3.383 A PP_5V0 current limit, setting 15 3.019 3.355 3.69 A PP_CABLE current limit (highest setting) 0.6 0.75 0.9 A PP_CABLE current limit (lowest setting) 0.35 0.45 0.55 A 3.25 5 6.75 A/V I = 200 mA 4 5 6 A/V I = 500 mA 4.4 5 5.6 A/V I≥1A 4.5 5 5.5 A/V 3.5 5 6.5 A/V I = 200 mA, RSENSE = 10 mΩ 4 5 6 A/V I = 500 mA, RSENSE = 10 mΩ 4.4 5 5.6 A/V I ≥ 1 A, RSENSE = 10 mΩ 4.5 5 5.5 A/V PP_HV current sense accuracy I = 100 mA Reverse current blocking disabled IHV_ACC (4) PP_EXT current sense accuracy (excluding RSENSE accuracy) IHVEXT_ACC (3) (4) 14 I = 100 mA , RSENSE = 10 mΩ Reverse current blocking disabled Specified for a 10-mΩ RSENSE resistor and 10-mΩ RSENSE application code setting. Values will scale with a different RSENSE resistance and application code setting. The current sense in the ADC will not accurately read below the current VREV5V0/RPP5V or VREVHV/RPPHV due to the reverse blocking behavior. When reverse blocking is disabled, the values given for accuracy are valid. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Port Power Switch Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted TEST CONDITION (1) PARAMETER PP_5V0 current sense accuracy MIN TYP MAX UNIT 1.95 3 4.05 A/V I = 200 mA 2.4 3 3.6 A/V I = 500 mA 2.64 3 3.36 A/V 2.7 3 3.3 A/V I = 100 mA - 1 - A/V I = 200 mA - 1 - A/V I = 500 mA - 1 - A/V 4 5 6 μA I = 100 mA Reverse current blocking disabled IPP5V_ACC (4) I≥1A PP_CABLE current sense accuracy IPPCBL_ACC IGATEEXT (5) External Gate Drive Current on HV_GATE1 and HV_GATE2 VGSEXT VGS voltage driving external FETs 4.5 7.5 V PP_HV path turn on time from enable to VBUS = 95% of PP_HV voltage Configured as a source or as a sink with soft start disabled. PP_HV = 20 V, CVBUS = 10 μF, ILOAD = 100 mA 8 ms PP_5V0 path turn on time from enable to VBUS = 95% of PP_5V0 voltage Configured as a source or as a sink with soft start disabled. PP_5V0 = 5 V, CVBUS = 10 μF, ILOAD = 100 mA 2.5 ms TON_CC PP_CABLE path turn on time from enable to C_CCn = 95% of the PP_CABLE voltage PP_CABLE = 5 V, C_CCn = 500 nF, ILOAD = 100 mA 2 ms ISS Soft start charging current 5.5 7 8.5 μA RSS_DIS Soft start discharge resistance 0.6 1 1.4 kΩ VTHSS Soft start complete threshold 1.35 1.5 1.65 V TSSDONE Soft start complete time 31.9 46.2 60.5 ms VREVPHV Reverse current blocking voltage threshold for PP_HV switch 2 6 10 mV VREVPEXT Reverse Current Blocking voltage Threshold for PP_EXT external switches 2 6 10 mV VREV5V0 Reverse current blocking voltage threshold for PP_5V0 switches 2 6 10 mV Voltage threshold above VIN at which the pulldown RHVDISPD on VBUS will disable during a transition from PHV to 5V0 45 200 250 mV VHVDISPD VSAFE0V Voltage that is a safe 0V per USB-PD Specifications 0.8 V TSAFE0V Voltage transition time to VSAFE0V 650 ms VSO_HV Voltage on PP_HV or PP_HVEXT above which the PP_HV or PP_EXT to PP_5V0 transition on VBUS will meet transition requirements SRPOS Maximum slew rate for positive voltage transitions SRNEG Maximum slew rate for negative voltage transitions TSTABLE EN to stable time for both positive and negative voltage transitions VSRCVALID Supply Output Tolerance beyond VSRCNEW during time TSTABLE VSRCNEW Supply Output Tolerance TON_HV TON_5V (5) CSS = 220 nF 0 9.9 V 0.03 –0.03 V/μs V/μs 275 ms –0.5 0.5 V –5 5 % Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit events. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 15 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6.12 Port Data Multiplexer Switching and Timing Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX Vi = 3.3 V, IO = 20 mA 35 55 Vi = 1 V, IO = 20 mA 30 46 UNIT SWD MULTIPLEXER PATH (1) SWD_RON_U On resistance of SWD_DATA/CLK to C_USB_TP/TN/BP/BN SWD_ROND_U On resistance difference between P and N paths of SWD_DATA/CLK to C_USB_ TP/TN/BP/BN SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2 SWD_ROND_S On resistance difference between P and N paths of SWD_DATA/CLK to C_SBU1/2 SWD_TON Switch on time from enable of SWD path Vi = 1 V to 3.3 V, IO = 20 mA –2.5 2.5 Vi = 3.3 V, IO = 20 mA 26 42 Vi = = 1 V, IO = 20 mA 24 37 Vi = 1V to 3.3 V, IO = 20 mA –1.5 1.5 Time from enable bit with charge pump off 500 Time from disable bit at charge pump steady state SWD_BW 3 dB bandwidth of SWD path CL = 10 pF Ω Ω μs 10 Switch off time from disable of SWD path Ω 150 Time from enable bit at charge pump steady state SWD_TOFF Ω 200 ns MHz DEBUG1/2 MULTIPLEXER PATH (1) DB1_RON_U On resistance DEBUG1/2 to C_USB_TP/TN/BP/BN DB1_ROND_U On resistance difference between P and N paths of DEBUG1/2 to C_USB_TP/TN/BP/BN DB1_RON_S On resistance of DEBUG1/2 to C_SBU1/2 DB1_ROND_S On resistance difference between P and N paths of Debug path DEBUG1/2 to C_SBU1/2 DB1_TON Switch on time from enable of DEBUG path Vi = 3.3 V, IO = 20 mA 14 26 Vi = 1 V, IO = 20 mA 10 17 Vi = 1 V to 3.3 V, IO = 20 mA –2.5 2.5 Vi = 3.3 V, IO = 20 mA 9.5 17 Vi = 1 V, IO = 20 mA 6.5 12 Vi = 1 V to 3.3 V, IO = 20 mA –0.5 0.5 Time from enable bit with charge pump off 500 Time from disable bit at charge pump steady state DB1_BW 3dB bandwidth of DEBUG path CL = 10 pF Ω Ω μs 10 Switch off time from disable of DEBUG path Ω 150 Time from enable bit at charge pump steady state DB1_TOFF Ω 200 ns MHz DEBUG3/4 MULTIPLEXER PATH (1) DB3_RON_U On resistance of DEBUG3/4 to C_USB_TP/TN/BP/BN DB3_ROND_U On resistance difference between P and N paths of DEBUG3/4 to C_USB_ TP/TN/BP/BN DB3_RON_S On resistance of DEBUG3/4 to C_SBU1/2 DB3_ROND_S On resistance difference between P and N paths of DEBUG3/4 to C_SBU1/2 DB3_TON Switch on time from enable of DEBUG3/4 path Vi = 3.3 V, IO = 20 mA Vi = 1 V, IO = 20 mA Vi = 1 V to 3.3V, IO = 20 mA 17 –1.5 1.5 9.5 18 Vi = 1 V, IO = 20 mA 6.5 12 Vi = 1 V to 3.3 V, IO = 20 mA –0.15 Time from enable bit with charge pump off 0.15 500 DB3_BW 3dB bandwidth of DEBUG3/4 path CL = 10 pF Ω Ω Ω μs 10 Time from disable bit at charge pump steady state Ω 150 Time from enable bit at charge pump steady state Switch off time from disable of DEBUG3/4 path 16 24 9 Vi = 3.3 V, IO = 20 mA DB3_TOFF (1) 14 200 ns MHz All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum difference between the two switches in a pair. ROND does not add to RON. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Port Data Multiplexer Switching and Timing Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX Vi = 3.3 V, IO = 20 mA 8.5 17 Vi = 1 V, IO = 20 mA 5.5 11 UNIT LSX_R2P/P2R MULTIPLEXER PATH (1) LSX_RON On resistance of LSX_P2R/R2P to C_SBU1/2 LSX_ROND On resistance difference between P and N paths of LSX path LSX_TON Vi = 1 V to 3.3 V, IO = 20 mA –0.3 Time from enable bit with charge pump off Switch on time from enable of LSX path μs 10 500 Switch off time from disable of LSX path Time from disable bit at charge pump steady state LSX_BW 3dB bandwidth of LSX path CL = 10 pF Ω 150 Time from enable bit at charge pump steady state LSX_TOFF AUX MULTIPLEXER PATH 0.3 Ω 200 ns MHz (1) AUX_RON On resistance of AUX_P/N to C_SBU1/2 AUX_ROND On resistance difference between P and N paths of AUX_P/N to C_SBU1/2 AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2 Vi = 3.3 V, IO = 20 mA 3.5 7 Vi = 1 V, IO = 20 mA 2.5 5 Vi = 1 V to 3.3 V, IO = 20 mA –0.25 0.25 Time from enable bit with charge pump off μs 15 500 Switch off time from disable of AUX_P/N to C_SBU1/2 Time from disable bit at charge pump steady state AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path CL = 10 pF Ω 150 Time from enable bit at charge pump steady state AUX_TOFF Ω 200 ns MHz UART MULTIPLEXER PATH (2nd Stage Only) (1) (2) UART_RON On resistance of UART buffers to C_USB_TP/TN/BP/BN or Vi = 3.3 V, IO = 20 mA C_SBU1/2 UART_TON Switch on time from enable of UART buffer C_USB_TP/TN/BP/BN or C_SBU1/2 path 3.1 Time from enable bit with charge pump off 12 150 µs Time from enable bit at charge pump steady state 10 500 UART_TOFF Switch off time from disable of UART buffer path Time from disable bit at charge pump steady state UART_BW 3dB bandwidth of UART buffer path CL = 10 pF Ω 200 ns MHz USB_RP MULTIPLEXER PATH (1) (3) USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN USB_ROND On resistance difference between P and N paths of USB_RP to C_USB_TP/TN/BP/BN USB_TON Switch on time from enable of USB USB_RP path Vi = 3 V, IO = 20 mA Vi = 400 mV, IO = 20 mA Vi = 0.4 V to 3 V, IO = 20 mA –0.15 Time from enable bit with charge pump off 4.5 10 3 7 0.15 Ω Ω 150 µs Time from enable bit at charge pump steady state 15 500 USB_TOFF Switch off time from disable of USB_RP path Time from disable bit at charge pump steady state USB_BW 3dB bandwidth of USB_RP path CL = 10 pF USB_ISO Off Isolation of USB_RP path RL = 50 Ω, VI = 800 mV, f = 240 MHz –19 dB USB_XTLK Channel to Channel crosstalk of USB_RP path RL = 50 Ω, f = 240 MHz –26 dB R_SBU_OPEN Resistance of the open C_SBU1/2 paths Vi = 0 V to LDO_3V3 1 MΩ R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths Vi = 0 V to LDO_3V3 1 MΩ 850 ns MHz C_SBU1/2 OUTPUT (2) (3) The UART switch path connects from the UART buffers to the port pins. See Input/Output (I/O) Requirements and Characteristics for buffer specifications. See Port Data Multiplexer USB Endpoint Requirements and Characteristics for the USB_EP specifications. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 17 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6.13 Port Data Multiplexer Clamp Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP 3.95 MAX UNIT VCLMP_IND Clamp Voltage triggering indicator to Digital Core 3.8 4.1 V ICLMP_IND Clamp Current at VCLMP_IND 10 250 μA TCLMP_PRT (1) Time from clamp current crossing ICLMP_IND to interrupt signal assertion 0 4 μs ICLMP USB_EP and USB_RP Port Clamp Current (1) I ≥ ICLMP_IND rising V = LDO_3V3 V = VCLMP_IND + 500 mV 3.5 250 nA 15 mA The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time may be longer. 6.14 Port Data Multiplexer SBU Detection Requirements Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS VIH_PORT Port switch detect input high voltage LDO_3V3 = 3.3 V VIL_PORT Port switch detect input low voltage LDO_3V3 = 3.3 V MIN TYP MAX 2.0 UNIT v 0.8 V 6.15 Port Data Multiplexer Signal Monitoring Pull-Up and Pull-Down Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPU05 500-Ω pull-up/down resistance LDO_3V3 = 3.3 V 350 500 650 Ω RTPU5 5-kΩ pull-up/down resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ RPU100 100-kΩ pull-up/down resistance LDO_3V3 = 3.3 V 70 100 130 kΩ 6.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Transmitter (1) T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns T_RRM_EP Rise/Fall time matching Low-speed (1.5 Mbps) data rate only –20% 25% V_XOVER_EP Output crossover voltage 1.3 2 RS_EP Source resistance of driver including 2nd Stage Port Data Multiplexer Differential Receiver V Ω 34 (1) VOS_DIFF_EP Input offset VIN_CM_EP Common Mode Range RPU_EP D- Bias Resistance Receiving –100 100 0.8 2.5 mV V 1.425 1.575 kΩ Single Ended Receiver (1) VTH_SE_EP Single ended threshold Signal rising/falling VHYS_SE_EP Single ended threshold hysteresis Signal falling (1) 18 0.8 2 200 V mV The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for VIN_3V3 ≥ 3.135 V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 6.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 7 10 13 μA 14.25 20 24.8 kΩ Data Contact Detect IDP_SRC DCD Source Current RDM_DWN DCD pull-down resistance LDO_3V3 = 3.3 V VLGC_HI Threshold for no connection VC_USB_TP/BP ≥ VLGC_HILDO_3V3 = 3.3 V LDO_3V3 = 3.3 V VLGC_LO Threshold for connection VC_USB_TP/BP ≤ VLGC_LO LDO_3V3 = 3.3 V 2 V 0.8 V Primary and Secondary Detect VDX_SRC Source voltage VDX_RSRC Total series resistance due to Port Data Multiplexer 0.55 VDX_ILIM VDX_SRC current limit IDX_SNK Sink Current 0.6 VDX_SRC = 0.65 V 250 VC_USB_TN/BN ≥ 250 mV 25 75 MIN TYP 0.65 V 65 Ω 400 μA 125 μA 6.18 Analog-to-Digital Converter (ADC) Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MAX UNIT 1.5 1.523 MHz 42.14 43 43.86 μs ADC input sample time 10.5 10.67 10.9 μs ADC conversion time 7.88 8 8.12 μs T_INTA ADC interrupt time 1.31 1.33 1.35 μs LSB Least Significant Bit 1.152 1.17 1.188 mV DNL Differential Non-linearity –0.65 0.65 LSB INL Integral Non-linearity –1.2 1.2 LSB –1.5% 1.5% RES_ADC ADC Resolution F_ADC ADC clock frequency 1.477 T_ENA ADC enable time T_SAMPLEA T_CONVERTA GAIN_ERR 10 Gain Error (divider) Gain Error (no divider) bits –1 1 –10 10 mV –8 8 °C VOS_ERR Buffer Offset Error THERM_ACC Thermal Sense Accuracy THERM_GAIN Thermal slope 3.095 mV/°C THERM_V0 Zero Degree Voltage 0.823 V 6.19 Input/Output (I/O) Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT SPI SPI_VIH High Level Input Voltage LDO_3V3 = 3.3 V SPI_VIL Low Input Voltage LDO_3V3 = 3.3 V SPI_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 SPI_ILKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 SPI Output High Voltage IO = –8 mA, LDO_3V3=3.3 V 2.9 IO = –15 mA, LDO_3V3=3.3 V 2.5 SPI_VOH SPI_VOL SPI Output Low Voltage 2 V 0.8 V 1 μA V V IO = 10 mA 0.4 IO = 20 mA 0.8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 V 19 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Input/Output (I/O) Requirements and Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT SWDIO SWDIO_VIH High Level Input Voltage LDO_3V3 = 3.3 V SWDIO_VIL Low Input Voltage LDO_3V3 = 3.3 V SWDIO_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V 0.2 SWDIO_ILKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 Output High Voltage IO = –8 mA, LDO_3V3 = 3.3 V 2.9 IO = –15 mA, LDO_3V3 = 3.3 V 2.5 SWDIO_VOH SWDIO_VOL Output Low Voltage 2 V 0.8 V 1 μA V V IO = 10 mA 0.4 IO = 20 mA V 0.8 SWDIO_RPU Pull-up Resistance 2.8 4 SWDIO_TOS SWDIO Output skew to falling edge SWDCLK –5 5.2 kΩ 5 SWDIO_TIS Input Setup time required between SWDIO and rising edge of SWCLK 6 ns ns SWDIO_TIH Input Hold time required between SWDIO and rising edge of SWCLK 1 ns SWDCLK SWDCL_VIH High Level Input Voltage LDO_3V3 = 3.3 V SWDCL_VIL Low Input Voltage LDO_3V3 = 3.3 V SWDCL_THI SWDIOCLK HIGH period SWDCL_TLO SWDIOCLK LOW period SWDCL_HYS Input Hysteresis Voltage SWDCL_RPU Pull-up Resistance 2 LDO_3V3 = 3.3 V V 0.8 V 0.05 500 μs 0.05 500 μs 5.2 kΩ 0.2 2.8 V 4 GPIO, MRESET, RESETZ, BUSPOWERZ GPIO_VIH High Level Input Voltage LDO_3V3 = 3.3 V 2 VDDDIO = 1.8 V LDO_3V3 = 3.3 V 0.8 GPIO_VIL Low Input Voltage GPIO_HYS Input Hysteresis Voltage GPIO_ILKG I/O Leakage Current INPU = 0 V to VDD GPIO_RPU Pull-up Resistance pull-up enabled 50 GPIO_RPD Pull-down Resistance pull-down enabled 50 GPIO_DG Digital input path de-glitch GPIO_VOH GPIO Output High Voltage GPIO_VOL GPIO Output Low Voltage V 1.25 VDDIO = 1.8 V 0.63 LDO_3V3 = 3.3 V 0.2 VDDIO = 1.8 V V 0.09 1 μA 100 150 kΩ 100 150 kΩ –1 20 IO = –2 mA, LDO_3V3 = 3.3 V IO = –2 mA, VDDIO = 1.8 V V ns 2.9 V 1.35 IO = 2 mA, LDO_3V3 = 3.3 V 0.4 IO = 2 mA, VDDIO = 1.8 V 0.45 V UART_RX/TX, LSX_P2R/R2P UARTRX_VIH High Level Input Voltage UARTRX_VIL Low Input Voltage UARTRX_HYS Input Hysteresis Voltage UARTTX_VOH GPIO Output High Voltage UARTTX_VOL GPIO Output Low Voltage UARTTX_RO Output impedance, TX channel UARTTX_TRTF Rise and fall time, TX channel UART_FMAX Maximum UART baud rate 20 LDO_3V3 = 3.3 V 2 VDDDIO = 1.8 V V 1.25 LDO_3V3 = 3.3 V 0.8 VDDIO = 1.8 V 0.63 LDO_3V3 = 3.3 V 0.2 VDDIO = 1.8 V IO = –2 mA, VDDIO = 1.8 V V 0.09 IO = –2 mA, LDO_3V3 = 3.3 V 2.9 V 1.35 IO = 2 mA, LDO_3V3 = 3.3 V 0.4 IO = 2 mA, VDDIO = 1.8 V LDO_3V3 = 3.3 V 10%–90%, CL = 20 pF Submit Documentation Feedback 0.45 35 1 V 70 V 115 Ω 40 ns 1.1 Mbps Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Input/Output (I/O) Requirements and Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT I2C_IRQ1Z, I2C_IRQ2Z OD_VOL Low level output voltage IOL = 2 mA OD_LKG Leakage Current Output is Hi-Z, VIN = 0 to LDO_3V3 SBU_VIH High Level Input Voltage LDO_3V3 = 3.3 V SBU_VIL Low Input Voltage LDO_3V3 = 3.3 V SBU_HYS Input Hysteresis Voltage LDO_3V3 = 3.3 V –1 0.4 V 1 μA SBU 2 V 0.8 0.2 V V 6.20 I2C Slave Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT SDA and SCL COMMON CHARACTERISTICS ILEAK Input leakage current Voltage on Pin = LDO_3V3 -3 IOL = 3mA, LDO_3V3 = 3.3 V 3 0.4 μA VOL SDA output low voltage IOL SDA max output low current VIL Input low signal VIH Input high signal VHYS Input Hysteresis TSP I2C pulse width suppressed 50 ns CI Pin Capacitance 10 pF 100 kHz IOL = 3mA, VDDIO = 1.8 V 0.36 VOL = 0.4 V 3 VOL = 0.6 V 6 mA LDO_3V3 = 3.3 V 0.99 VDDIO = 1.8 V 0.54 LDO_3V3 = 3.3 V 2.31 VDDIO = 1.8 V 1.26 LDO_3V3 = 3.3 V 0.17 VDDIO = 1.8 V 0.09 V V V V SDA and SCL STANDARD MODE CHARACTERISTICS FSCL I2C clock frequency 0 THIGH I2C clock high time 4 μs 2 TLOW I C clock low time 4.7 μs TSUDAT I2C serial data setup time 250 ns THDDAT I2C serial data hold time TVDDAT TVDACK 0 2 ns I C Valid data time SCL low to SDA output valid 3.4 μs I2C Valid data time of ACK condition ACK signal from SCL low to SDA (out) low 3.4 μs 2 TOCF I C output fall time TBUF I2C bus free time between stop and start 10 pF to 400 pF bus 4.7 μs TSTS I2C start or repeated Start condition setup time 4.7 μs 2 250 ns TSTH I C Start or repeated Start condition hold time 4 μs TSPS I2C Stop condition setup time 4 μs Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 21 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com I2C Slave Requirements and Characteristics (continued) Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT 400 kHz SDA and SCL FAST MODE CHARACTERISTICS I2C clock frequency FSCL 0 2 THIGH I C clock high time 0.6 μs TLOW I2C clock low time 1.3 μs TSUDAT I2C serial data setup time 100 ns 0 ns THDDAT TVDDAT 2 I C serial data hold time 2 SCL low to SDA output valid 0.9 μs 2 ACK signal from SCL low to SDA (out) low 0.9 μs I C Valid data time TVDACK I C Valid data time of ACK condition TOCF I2C output fall time TBUF I2C bus free time between stop and start 10 pF to 400 pF bus, VDD = 3.3 V 12 250 10 pF to 400 pF bus, VDD = 1.8 V 6.5 250 2 ns 1.3 μs TSTS I Cstart or repeated Start condition setup time 0.6 μs TSTH I2C Start or repeated Start condition hold time 0.6 μs TSPS I2C Stop condition setup time 0.6 μs 6.21 SPI Master Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITION MIN TYP MAX UNIT 11.82 12 12.18 MHz 82.1 83.33 84.6 ns FSPI Frequency of SPI_CLK TPER Period of SPI_CLK (1/F_SPI) TWHI SPI_CLK High Width 30 TWLO SPI_CLK Low Width 30 TDACT SPI_SZZ falling to SPI_CLK rising delay time 30 50 ns TDINACT SPI_CLK falling to SPI_SSZ rising delay time 160 180 ns TDMOSI SPI_CLK falling to SPI_MOSI Valid delay time –5 5 ns TSUMISO SPI_MISO valid to SPI_CLK falling setup time 21 ns THDMSIO SPI_CLK falling to SPI_MISO invalid hold time 0 ns TRSPI SPI_SSZ/CLK/MOSI rise time 10% to 90%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V TFSPI SPI_SSZ/CLK/MOSI fall time 90% to 10%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V ns ns 0.1 8 ns 0.1 8 ns 6.22 Single-Wire Debugger (SWD) Timing Requirements Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER FSWD Frequency of SWD_CLK TPER Period of SWD_CLK (1/FSWD) TWHI TEST CONDITION MIN TYP MAX UNIT 10 MHz 100 ns SWD_CLK High Width 35 ns TWLO SWD_CLK Low Width 35 ns TDOUT SWD_CLK rising to SWD_DATA valid delay time 2 TSUIN SWD_DATA valid to SWD_CLK rising setup time 9 ns THDIN SWD_DATA hold time from SWD_CLK rising 3 ns TRSWD SWD Output rise time 10% to 90%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns TFSWD SWD Output fall time 90% to 10%, CL = 5 pF to 50 pF, LDO_3V3 = 3.3 V 0.1 8 ns 22 Submit Documentation Feedback 25 ns Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 6.23 BUSPOWERZ Configuration Requirements Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN VBPZ_EXT BUSPOWERZ Voltage for receiving VBUS Power through the PP_EXT path VBPZ_HV BUSPOWERZ Voltage for receiving VBUS Power through the PP_HV path 0.8 VBPZ_DIS BUSPOWERZ Voltage for disabling system power from VBUS 2.4 TYP MAX UNIT 0.8 V 2.4 V V 6.24 HPD Timing Requirements and Characteristics Recommended operating conditions; TA = -10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DP SOURCE SIDE (HPD TX) T_IRQ_MIN HPD IRQ minimum assert time T_3MS_MIN HPD Assert 3 ms minimum time 675 750 825 μs 3 3.33 3.67 ms HPD_HDB_SEL = 0 300 375 450 μs HPD_HDB_SEL = 1 100 111 122 ms DP SINK SIDE (HPD RX) T_HPD_HDB HPD high de-bounce time T_HPD_LDB HPD low de-bounce time 300 375 450 μs T_HPD_IRQ HPD IRQ limit time 1.35 1.5 1.65 ms MIN TYP MAX UNIT 145 160 175 °C 135 150 6.25 Thermal Shutdown Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS TSD_MAIN Thermal shutdown temperature of the main thermal shutdown Temperature rising TSDH_MAIN Thermal shutdown hysteresis of the main thermal shutdown Temperature falling TSD_PWR Thermal shutdown temperature of the power path block Temperature rising TSDH_PWR Thermal shutdown hysteresis of the power path block Temperature falling TSD_DG Programmable thermal shutdown detection de-glitch time 20 °C 165 37 °C °C 0.1 ms 6.26 Oscillator Requirements and Characteristics Recommended operating conditions; TA = –10 to 85 °C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FOSC_48M 48-MHz oscillator 47.28 48 48.72 MHz FOSC_100K 100-kHz oscillator 95 100 105 kHz 14.98 5 15 15.01 5 kΩ RR_OSC External oscillator set resistance (0.2%) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 23 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 41 88 40 86 39 84 Resistance (m:) Resistance (m:) 6.27 Typical Characteristics 38 37 36 35 82 80 78 76 74 34 72 33 70 32 -10 0 10 20 30 40 50 60 Temperature (qC) 70 80 90 100 68 -10 0 10 20 D001 Figure 1. PP_5V0 Switch On-Resistance vs. Temperature 30 40 50 60 Temperature (qC) 70 80 90 100 D002 Figure 2. PP_HV Switch On-Resistance vs. Temperature 220 Resistance (m:) 215 210 205 200 195 190 185 -10 0 10 20 30 40 50 60 Temperature (qC) 70 80 90 100 D003 Figure 3. PP_CABLE Switch On-Resistance vs Temperature 24 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 7 Parameter Measurement Information UVR_OUT3V3 - UVRH_OUT3V3 UVR_OUT3V3 VOUT_3V3 MRESET TUVRDELAY TUVRASSERT TUVRDELAY TUVRASSERT RESETZ Figure 4. RESETZ Assertion Timing T_ENA T_SAMPLEA T_CONVERTA T_INTA ADC Clock ADC Enable ADC Sample ADC Interrupt New Valid Output Previous or Invalid Output ADC Output Figure 5. ADC Enable and Conversion Timing Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 25 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Parameter Measurement Information (continued) T_SAMPA T_INTA T_CONVERTA T_SAMPLE T_CONVERTA ADC Clock ADC Sample ADC Interrupt New Valid Output ADC Output New Valid Output Figure 6. ADC Repeated Conversion Timing tf SDA tr tSU;DAT 70 % 30 % 70 % 30 % cont. tHD;DAT tf tVD;DAT tHIGH tr 70 % 30 % SCL 70 % 30 % 70 % 30 % tHD;STA 70 % 30 % cont. tLOW 9th clock 1 / fSCL S 1st clock cycle tBUF SDA tSU;STA tHD;STA tVD;ACK tSP tSU;STO 70 % 30 % SCL Sr P 9th clock S 002aac938 2 Figure 7. I C Slave Interface Timing 26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Parameter Measurement Information (continued) tper SPI_SSZ twhigh twlow tdact tdinact SPI_CLK tdmosi tdmosi SPI_MOSI Valid Data tsumiso SPI_MISO Valid Data thdmiso Figure 8. SPI Master Timing twhigh tper t wlow SWD_CLK t dout SWD_DATA (Output) t dout Valid Data t hdin tsuin SWD_DATA (Input) Valid Data Figure 9. SWD Timing Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 27 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8 Detailed Description 8.1 Overview The TPS65982 is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for a USB Type-C & PD plug or receptacle. The TPS65982 communicates with the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power switches, controls an external high current port power switch, and multiplexes high-speed data to the port for USB2.0 and supported Alternate Mode sideband information. The TPS65982 also controls an attached superspeed multiplexer to simultaneously support USB3.0/3.1 data rates and DisplayPort video. The TPS65982 is divided into six main sections: the USB-PD controller, the cable plug and orientation detection circuitry, the port power switches, the port data multiplexer, the power management circuitry, and the digital core. The USB-PD controller provides the physical layer (PHY) functionality of the USB-PD protocol. The USB-PD data is output through either the C_CC1 pin or the C_CC2 pin, depending on the orientation of the reversible USB Type-C cable. For a high-level block diagram of the USB-PD physical layer, a description of its features and more detailed circuitry, refer to the USB-PD Physical Layer section. The cable plug and orientation detection analog circuitry automatically detects a USB Type-C cable plug insertion and also automatically detects the cable orientation. For a high-level block diagram of cable plug and orientation detection, a description of its features and more detailed circuitry, refer to the Cable Plug and Orientation Detection section. The port power switches provide power to the system port through the VBUS pin and also through the C_CC1 or C_CC2 pins based on the detected plug orientation. For a high-level block diagram of the port power switches, a description of its features and more detailed circuitry, refer to the Port Power Switches section. The port data multiplexer connects various input pairs to the system port through the C_USB_TP, C_USB_TN, C_USB_BP, C_USB_BN, C_SBU1 and C_SBU2 pins. For a high-level block diagram of the port data multiplexer, a description of its features and more detailed circuitry, refer to the USB Type-C Port Data Multiplexer section. The power management circuitry receives and provides power to the TPS65982 internal circuitry and to the VOUT_3V3 and LDO_3V3 outputs. For a high-level block diagram of the power management circuitry, a description of its features and more detailed circuitry, refer to the Power Management section. The digital core provides the engine for receiving, processing, and sending all USB-PD packets as well as handling control of all other TPS65982 functionality. A small portion of the digital core contains non-volatile memory, called boot code, which is capable of initializing the TPS65982 and loading a larger, configurable portion of application code into volatile memory in the digital core. For a high-level block diagram of the digital core, a description of its features and more detailed circuitry, refer to the Digital Core section. The digital core of the TPS65982 also interprets and uses information provided by the analog-to-digital converter ADC (see the ADC section), is configurable to read the status of general purpose inputs and trigger events accordingly, and controls general outputs which are configurable as push-pull or open-drain types with integrated pull-up or pull-down resistors and can operate tied to a 1.8 V or 3.3 V rail. The TPS65982 is an I2C slave to be controlled by a host processor (see the I2C Slave Interface section), an SPI master to write to and read from an external flash memory (see the SPI Master Interface section), and is programmed by a single-wire debugger (SWD) connection (see the Single-Wire Debugger Interface section). The TPS65982 also integrates a thermal shutdown mechanism (see Thermal Shutdown section) and runs off of accurate clocks provided by the integrated oscillators (see the Oscillators section). 28 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 8.2 Functional Block Diagram NMOS PP_EXT SENSEP SENSEN HV_GATE1 HV_GATE2 External FET Control and Sense PP_HV VBUS 3A PP_5V0 600mA PP_CABLE VDDIO VIN_3V3 VOUT_3V3 RESETZ MRESET BUSPOWERZ R_OSC I2C_ADDR GPIO1-9 I2C_SDA/SCL/IRQ1Z I2C_SDA/SCL/IRQ2Z SPI_MOSI/MISO/SSZ/CLK SWD_DATA/CLK DEBUG_CTL1/2 UART_RX/TX LSX_R2P/P2R AUX_P/N USB_RP_P/N DEBUG1/2 DEBUG3/4 3A LDO_3V3 LDO_1V8A LDO_1V8D LDO_BMC Power Management and Supervisors Cable/Device 9 3 3 4 2 2 2 2 2 2 2 2 Detect, Digital Core C_CC1 RPD_G1 C_CC2 RPD_G2 Cable Power, and USB-PD Phy Port Data Multiplexer 2 2 2 C_USB_TP/TN C_USB_BP/BN C_SBU1/2 GND 8.3 Feature Description 8.3.1 USB-PD Physical Layer Figure 10 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 29 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Feature Description (continued) Fast current limit PP_CABLE C_CC1/2 Gate Control and Current Limit C_CC1 Gate Control LDO_3V3 C_CC1 USB-PD Phy Digital Core C_CC2 LDO_3V3 C_CC2 Gate Control Figure 10. USB-PD Physical Layer and Simplified Plug and Orientation Detection Circuitry USB-PD messages are transmitted in a USB Type-C system using a BMC signaling. The BMC signal is output on the same pin (C_CC1 or C_CC2) that is DC biased due to the DFP (or UFP) cable attach mechanism discussed in the Cable Plug and Orientation Detection section. 8.3.1.1 USB-PD Encoding and Signaling Figure 11 illustrates the high-level block diagram of the baseband USB-PD transmitter. Figure 12 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Encoder Data BMC Encoder to PD_TX CRC Figure 11. USB-PD Baseband Transmitter Block Diagram 30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Feature Description (continued) BMC Decoder from PD_RX SOP Detect Data 4b5b Decoder CRC Figure 12. USB-PD Baseband Receiver Block Diagram The USB-PD baseband signal is driven on the C_CCn pins with a tri-state driver. The tri-state driver is slew rate limited to reduce the high frequency components imparted on the cable and to avoid interference with frequencies used for communication. 8.3.1.2 USB-PD Bi-Phase Marked Coding The USBP-PD physical layer implemented in the TPS65982 is compliant to the USB-PD Specifications. The encoding scheme used for the baseband PD signal is a version of Manchester coding called Biphase Mark Coding (BMC). In this code, there is a transition at the start of every bit time and there is a second transition in the middle of the bit cell when a 1 is transmitted. This coding scheme is nearly DC balanced with limited disparity (limited to 1/2 bit over an arbitrary packet, so a very low DC level). Figure 13 illustrates Biphase Mark Coding. 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 Data in BMC Figure 13. Biphase Mark Coding Example The USB PD baseband signal is driven onto the C_CC1 or C_CC2 pins with a tri-state driver. The tri-state driver is slew rate to limit coupling to D+/D- and to other signal lines in the Type-C fully featured cables. When sending the USB-PD preamble, the transmitter will start by transmitting a low level. The receiver at the other end will tolerate the loss of the first edge. The transmitter will terminate the final bit by an edge to ensure the receiver clocks the final bit of EOP. 8.3.1.3 USB-PD Transmit (TX) and Receive (Rx) Masks The USB-PD driver meets the defined USB-PD BMC TX masks. Since a BMC coded “1” contains a signal edge at the beginning and middle of the UI, and the BMC coded “0” contains only an edge at the beginning, the masks are different for each. The USB-PD receiver meets the defined USB-PD BMC Rx masks. The boundaries of the Rx outer mask are specified to accommodate a change in signal amplitude due to the ground offset through the cable. The Rx masks are therefore larger than the boundaries of the TX outer mask. Similarly, the boundaries of the Rx inner mask are smaller than the boundaries of the TX inner mask. Triangular time masks are superimposed on the TX outer masks and defined at the signal transitions to require a minimum edge rate that will have minimal impact on adjacent higher speed lanes. The TX inner mask enforces the maximum limits on the rise and fall times. Refer to the USB-PD Specifications for more details. 8.3.1.4 USB-PD BMC Transmitter The TPS65982 transmits and receives USB-PD data over one of the C_CCn pins. The C_CCn pin is also used to determine the cable orientation (see the Cable Plug and Orientation Detection section) and maintain cable/device attach detection. Thus, a DC bias will exist on the C_CCn. The transmitter driver will overdrive the C_CCn DC bias while transmitting, but will return to a Hi-Z state allowing the DC voltage to return to the C_CCn pin when not transmitting. Figure 14 shows the USB-PD BMC TX/Rx driver block diagram. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 31 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Feature Description (continued) Digitally Adjustable VREF LDO_BB Level Shifter PD_TX Driver C_CC1 Level Shifter PD_RX C_CC2 USB-PD Modem Digitally Adjustable VREF Figure 14. USB-PD BMC TX/Rx Block Diagram Figure 15 shows the transmission of the BMC data on top of the DC bias. Note, The DC bias can be anywhere between the minimum threshold for detecting a UFP attach (VD_CCH_USB) and the maximum threshold for detecting a UFP attach to a DFP (VD_CCH_3P0) defined in the Cable Plug and Orientation Detection section. This means that the DC bias can be below VOH of the transmitter driver or above VOH. VOH DC Bias DC Bias VOL DC Bias VOH DC Bias VOL Figure 15. TX Driver Transmission with DC Bias The transmitter drives a digital signal onto the C_CCn lines. The signal peak VTXP is adjustable by application code and sets the VOH/VOL for the BMC data that is transmitted, and is defined in USB-PD TX Driver Voltage Adjustment Parameter. Keep in mind that the settings in a final system must meet the TX masks defined in the USB-PD Specifications. When driving the line, the transmitter driver has an output impedance of ZDRIVER. ZDRIVER is determined by the driver resistance and the shunt capacitance of the source and is frequency dependent. ZDRIVER impacts the noise ingression in the cable. Figure 16 shows the simplified circuit determining ZDRIVER. It is specified such that noise at the receiver is bounded. ZDRVER is defined by Equation 1. ZDRIVER = 32 RDRIVER 1 + s ´ RDRIVER ´ CDRIVER (1) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Feature Description (continued) RDRIVER ZDRIVER Driver CDRIVER Figure 16. ZDRIVER Circuit 8.3.1.5 USB-PD BMC Receiver The receiver block of the TPS65982 receives a signal that falls within the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. The values for VRXTR and VRXTF are listed in USB-PD Baseband Signal Requirements and Characteristics. Figure 17 shows an example of a multi-drop USB-PD connection. This connection has the typical UFP (device) to DFP (host) connection, but also includes cable USB-PD TX/Rx blocks. Only one system can be transmitting at a time. All other systems are Hi-Z (ZBMCRX). The USB-PD Specification also specifies the capacitance that can exist on the wire as well as a typical DC bias setting circuit for attach detection. DFP System Tx Pullup for Attach Detection UFP System Cable Connector Connector Tx CRECEIVER CRECEIVER CCBLPLUG CCBLPLUG RD for Attach Detection Rx Rx Tx Rx Tx Rx Figure 17. Example USB-PD Multi-Drop Configuration 8.3.2 Cable Plug and Orientation Detection Figure 18 shows the plug and orientation detection block at each C_CC pin (C_CC1 and C_CC2). Each pin has identical detection circuitry. LDO_3V3 IH_CC_0P9 IH_CC_1P5 VREF1 IH_CC_3P0 C_CCn VREF2 RD_CC VREF3 Figure 18. Plug and Orientation Detection Block Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 33 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Feature Description (continued) 8.3.2.1 Configured as a DFP When configured as a DFP, the TPS65982 detects when a cable or a UFP is attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65982 monitors the voltages on these pins to determine what, if anything, is connected. See the USB Type-C Specification for more information. Table 1 shows the high-level detection results. Refer to the USB Type-C Specification for more information. Table 1. Cable Detect States for a DFP C_CC1 C_CC2 Open Open Nothing attached CONNECTION STATE Continue monitoring both C_CC pins for attach. Power is not applied to VBUS or VCONN until a UFP connect is detected. RESULTING ACTION Rd Open UFP attached Monitor C_CC1 for detach. Power is applied to VBUS but not to VCONN (C_CC2). Open Rd UFP attached Monitor C_CC2 for detach. Power is applied to VBUS but not to VCONN (C_CC1). Ra Open Powered Cable/No UFP attached Monitor C_CC2 for a UFP attach and C_CC1 for cable detach. Power is not applied to VBUS or VCONN (C_CC1) until a UFP attach is detected. Open Ra Powered Cable/No UFP attached Monitor C_CC1 for a UFP attach and C_CC2 for cable detach. Power is not applied to VBUS or VCONN (C_CC1) until a UFP attach is detected. Ra Rd Powered Cable/UFP Attached Provide power on VBUS and VCONN (C_CC1) then monitor C_CC2 for a UFP detach. C_CC1 is not monitored for a detach. Rd Ra Powered Cable/UFP attached Provide power on VBUS and VCONN (C_CC2) then monitor C_CC1 for a UFP detach. C_CC2 is not monitored for a detach. Rd Rd Debug Accessory Mode attached Sense either C_CC pin for detach. Ra Ra Audio Adapter Accessory Mode attached Sense either C_CC pin for detach. When the TPS65982 is configured as a DFP, a current IH_CC is driven out each C_CCn pin and each pin is monitored for different states. When a UFP is attached to the pin, a pull-down resistance of Rd to GND will exist. The current IH_CC is then forced across the resistance Rd generating a voltage at the C_CCn pin. When configured as a DFP advertising Default USB current sourcing capability, the TPS65982 applies IH_CC_USB to each C_CCn pin. When a UFP with a pull-down resistance Rd is attached, the voltage on the C_CCn pin will pull below VH_CCD_USB. The TPS65982 can also be configured as a DFP to advertise default (500 mA), 1.5 A and 3 A sourcing capabilities. When the C_CCn pin is connected to an active cable VCONN (power to the active cable), the pull-down resistance will be different (Ra). In this case, the voltage on the C_CCn pin will pull below VH_CCA_USB/1P5/3P0 and the system will recognize the active cable. The VH_CCD_USB/1P5/3P0 thresholds are monitored to detect a disconnection from each of these cases respectively. When a connection has been recognized and the voltage on the C_CCn pin rises above the VH_CCD_USB/1P5/3P0 threshold, the system will register a disconnection. 8.3.2.2 Configured as a UFP When the TPS65982 is configured as a UFP, the TPS65982 presents a pull-down resistance RD_CC on each C_CCn pin and waits for a DFP to attach and pull-up the voltage on the pin. The DFP will pull-up the C_CC pin by applying either a resistance or a current. The UFP detects an attachment by the presence of VBUS. The UFP determines the advertised current from the DFP by the pull-up applied to the C_CCn pin. 8.3.2.3 Dead-Battery or No-Battery Support Type-C USB ports require a sink to present Rd on the CC pin before a USB Type-C source will provide a voltage on VBUS. The TPS65982 is hardware-configurable to present this Rd during a dead-battery or no-battery condition. Additional circuitry provides a mechanism to turn off this Rd when the port is acting as a source. Figure 19 shows the RPD_Gn pin used to configure the behavior of the C_CCn pins, and elaborates on the basic cable plug and orientation detection block shown in Figure 18. RPD_G1 and RPD_G2 configure C_CC1 and C_CC2 respectively. A resistance R_RPD is connected to the gate of the pull-down FET on each C_CCn pin. 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 This resistance must be pin-strapped externally in order to configure the C_CCn pin to behave in one of two ways: present an Rd pull-down resistance or present a Hi-Z when the TPS65982 is unpowered. During normal operation, RD will be RD_CC; however, while dead-battery or no-battery conditions exist, the resistance is untrimmed and will be RD_DB. When RD_DB is presented during dead-battery or no-battery, application code will switch to RD_CC. RPD_Gn C_CCn R_RPD RD_DB RD_DB_EN RD_CC RD_CC_EN Figure 19. C_CCn and RPD_Gn pins When C_CC1 is shorted to RPD_G1 and C_CC2 is shorted to RPD_G2 in an application of the TPS65982, booting from dead-battery or no-battery conditions will be supported. In this case, the gate driver for the pulldown FET is Hi-Z at its output. When an external connection pulls up on C_CCn (the case when connected to a DFP advertising with a pull-up resistance Rp or pull-up current), the connection through R_RPD will pull up on the FET gate turning on the pull-down through RD_DB. In this condition, the C_CCn pin will act as a clamp VTH_DB in series with the resistance RD_DB. When RPD_G1 and RPD_G2 are shorted to GND in an application and not electrically connected to C_C1 and C_CC2, booting from dead-battery or no-battery conditions is not possible. In this case, the TPS65982 will present a Hi-Z on the C_CC1 and C_CC2 pins and a USB Type-C source will never provide a voltage on VBUS. 8.3.3 Port Power Switches Figure 20 shows the TPS65982 port power path including all internal and external paths. The port power path provides to VBUS from PP_5V0, provides power to or from VBUS from or to PP_HV, provides power to or from an external port power node (shown and refered to as PP_EXT) from or to VBUS, and provides power from PP_CABLE to C_CC1 or C_CC2. The PP_CABLE to C_CCn switches shown in Figure 20 are the same as in Figure 10, but are now shown without the analog USB Type-C cable plug and orientation detection circuitry. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 35 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com NMOS 5A RSENSE 10 mΩ ± 1% HV_GATE2 HV_GATE1 SENSEP SENSEN PP_EXT PP_HV Gate Control and Current Limit PP_HV Fast current limit 3A HV Gate Control and Sense PP_5V0 Gate Control and Current Limit PP_5V0 VBUS Fast current limit 3A C_CC1/2 Gate Control and Current Limit C_CC1 Gate Control PP_CABLE C_CC1 Fast current600mA limit C_CC2 Gate Control C_CC2 Figure 20. Port Power Paths 8.3.3.1 5V Power Delivery The TPS65982 provides port power to VBUS from PP_5V0 when a low voltage output is needed. The switch path provides 5 V at up to 3 A to from PP_5V0 to VBUS. Figure 20 shows a simplified circuit for the switch from PP_5V0 to VBUS. 8.3.3.2 5V Power Switch as a Source The PP_5V0 path is unidirectional, sourcing power from PP_5V0 to VBUS only. When the switch is on, the protection circuitry limits reverse current from VBUS to PP_5V0. Figure 21 shows the I-V characteristics of the reverse current protection feature. Figure 21 and the reverse current limit can be approximated using Equation 2. IREV5V0 = VREV5V0/RPP5V 36 (2) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 I 1/RPP5V VREV5V0 V IREV5V0 Figure 21. 5V Switch I-V Curve 8.3.3.3 PP_5V0 Current Sense The current from PP_5V0 to VBUS is sensed through the switch and is available to be read digitally through the ADC. 8.3.3.4 PP_5V0 Current Limit Current (A) 12 10 6 I VBUS VBUS 5 8 4 6 3 4 2 2 1 0 0 -2 Voltage (V) The current through PP_5V0 to VBUS is limited to ILIMPP5V and is controlled automatically by the digital core. When the current exceeds ILIMPP5V, the current-limit circuit activates. Depending on the severity of the overcurrent condition, the transient response will react in one of two ways: Figure 22 and Figure 23 show the approximate response time and clamping characteristics of the circuit for a hard short while Figure 24 shows the shows the approximate response time and clamping characteristics for a soft short with a load of 2 Ω. -1 Time (5 Ps/div) D004 Current (A) 12 10 6 I VBUS VBUS 5 8 4 6 3 4 2 2 1 0 0 -2 Voltage (V) Figure 22. PP_5V0 Current Limit with a Hard Short -1 Time (200 Ps/div) D005 Figure 23. PP_5V0 Current Limit with a Hard Short (Extended Time Base) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 37 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 6 I VBUS VBUS Current (A) 5 5 4 4 3 3 2 2 1 1 0 Voltage (V) 6 0 Time (200 Ps/div) D006 Figure 24. PP_5V0 Current Limit with a Soft Short (2 Ω) 8.3.3.5 Internal HV Power Delivery The TPS65982 has an integrated, bi-directional high-voltage switch that is rated for up to 3 Amps of current. The TPS65982 is capable of sourcing or sinking high-voltage power through an internal switch path designed to support USB-PD power up to 20 V at 3 A of current. VBUS and PP_HV are both rated for up to 22 V as determined by Recommended Operating Conditions, and operate down to 0 V as determined by Absolute Maximum Ratings. In addition, VBUS is tolerant to voltages up to 22 V even when PP_HV is at 0 V. Similarly, PP_HV is tolerant up to 22 V while VBUS is at 0 V. The switch structure is designed to tolerate a constant operating voltage differential at either of these conditions. Figure 20 shows a simplified circuit for the switch from PP_HV to VBUS. 8.3.3.6 Internal HV Power Switch as a Source The TPS65982 provides power from PP_HV to VBUS at the USB Type-C port as an output when operating as a source. When the switch is on as a source, the path behaves resistively until the current reaches the amount calculated by Equation 3 and then blocks reverse current from VBUS to PP_HV. Figure 25 shows the diode behavior of the switch as a source. IREVHV = VREVHV/RPPHV (3) I 1/RPPHV VREVHV V IREVHV Figure 25. Internal HV Switch I-V Curve as a Source 8.3.3.7 Internal HV Power Switch as a Sink The TPS65982 can also receive power from VBUS to PP_HV when operating as a sink. When the switch is on as a sink the path behaves as an ideal diode and blocks reverse current from PP_HV to VBUS. Figure 26 shows the diode behavior of the switch as a sink. 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 I 1/RPPHV VREVHV/RPPHV VBUS-PP_HV VREVHV Figure 26. Internal HV Switch I-V Curve as a Sink 8.3.3.8 Internal HV Power Switch Current Sense The current from PP_HV to VBUS is sensed through the switch and is available to be read digitally through the ADC only when the switch is sourcing power. When sinking power, the readout from the ADC will not reflect the current. 8.3.3.9 Internal HV Power Switch Current Limit The current through PP_HV to VBUS is current limited to ILIMPPHV (only when operating as a source) and is controlled automatically by the digital core. When the current exceeds ILIMPPHV, the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response will react in one of two ways: Figure 27 shows the approximate response time and clamping characteristics of the circuit for a hard short while Figure 28 shows the approximate response time and clamping characteristics for a soft short of 7 Ω. 30 I VBUS VBUS 25 PP_HV Current (A) 25 20 20 15 15 10 10 5 5 0 0 -5 Voltage (V) 30 -5 Time (10 Ps/div) D007 Figure 27. PP_HV Current Limit Response with a Hard Short Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 39 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 25 20 10 Voltage (V) Current (A) 15 5 I VBUS 0 VBUS PP_HV -5 Time (200 Ps/div) D008 Figure 28. PP_HV Current Limit Response with a Soft Short (7 Ω) 8.3.3.10 External HV Power Delivery The TPS65982 is capable of controlling an external high-voltage, common-drain back-to-back NMOS FET switch path to source or sink power up to the maximum limit of the USB PD specification: 20 V at 5 A of current. The TPS65982 provides external control and sense to external NMOS power switches for currents greater than 3 A. This path is bi-directional for either sourcing current to VBUS or sinking current from VBUS. The external NMOS switches are back-to-back to protect the system from large voltage differential across the FETs as well as blocking reverse current flow. Each NFET has a separate gate control. HV_GATE2 is always connected to the VBUS side and HV_GATE1 is always connected to the opposite side, referred to as PP_EXT. Two sense pins, SENSEP and SENSEN, are used to implement reverse current blocking, over-current protection, and current sensing. The external path may be used in conjunction with the internal path. For example, the internal path may be used to source current from PP_HV to VBUS when the TPS65982 is acting as a power source and the external path may be used to sink current from VBUS to PP_EXT in order to charge a battery when the TPS65982 is acting as a sink. The internal and external paths must never be used in parallel to source current at the same time or sink current at the same time. The current limiting function will not function properly in this case and may become unstable. 8.3.3.11 External HV Power Switch as a Source with RSENSE Figure 20 shows the configuration when the TPS65982 is acting as a source for the external switch path. The external FETs must be connected in a common-drain configuration and will not work in a common source configuration. In this mode, current is sourced to VBUS. RSENSE provides an accurate current measurement and is used to initiate the current limiting feature of the external power path. The voltage between SENSEP (PP_EXT) and SENSEN (VBUS) is sensed to block reverse current flow. This measurement is also digitally readable via the ADC. 8.3.3.12 External HV Power Switch as a Sink with RSENSE Figure 29 shows the configuration when the TPS65982 is acting as a sink for the external switch path with RSENSE used to sense current. Acting as a sink, the voltage between SENSEP (VBUS) and SENSEN (PP_EXT) is sensed to provide an accurate current measurement and initiate the current limiting feature of the external power path. This measurement is also digitally readable via the ADC. 40 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 NMOS 5A RSENSE 10 mΩ ± 1% VBUS HV_GATE2 HV_GATE1 SENSEN SENSEP PP_EXT HV Gate Control and Sense Figure 29. External HV Switch as a Sink with RSENSE 8.3.3.13 External HV Power Switch as a Sink without RSENSE Figure 30 shows the configuration when the TPS65982 is acting as a sink for the external switch path without an RSENSE resistor. In this mode, current is sunk from VBUS to an internal system power node, referred to as PP_EXT. This is used for charging a battery or for providing a supply voltage for a bus-powered device. To block reverse current, the VBUS and SENSEP pins monitor the voltage across the NFETs. To ensure that SENSEN does not float, tie SENSEP to SENSEN in this configuration. When configured in this mode, the digital readout from current from the ADC will be approximately zero. NMOS 5A VBUS HV_GATE2 HV_GATE1 SENSEN SENSEP PP_EXT HV Gate Control and Sense Figure 30. External HV Switch as a Sink without RSENSE 8.3.3.14 External Current Sense The current through the external NFETs to VBUS is sensed through the RSENSE resistor and is available to be read digitally through the ADC. When acting as a source, the readout from the ADC will only accurately reflect the current through the external NFETs when the connection of SENSEP and SENSEN adheres to Figure 20. When acting as a sink, the readout from the ADC will only accurately reflect the current through the external NFETs when the connection of SENSEP and SENSEN adheres to Figure 29. 8.3.3.15 External Current Limit The current through the external NFETs to VBUS is current limited when acting as a source or a sink. The current is sensed across the external RSENSE resistance. The current limit is set by a combination of the RSENSE magnitude and configuration settings for the voltage across the resistance. When the voltage across the RSENSE resistance exceeds the automatically set voltage limit, the current-limit circuit is activated. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 41 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.3.16 Soft Start When configured as a sink, the SS pin provides a soft start function for each of the high-voltage power path supplies (P_HV and external PP_EXT path) up to 5.5 V. The SS circuitry is shared for each path and only one path will turn on as a sink at a time. The soft start is enabled by application code or via the host processor. The SS pin is initially discharged through a resistance RSS_DIS. When the switch is turned on, a current ISS is sourced from the pin to a capacitance CSS. This current into the capacitance generates a slow ramping voltage. This voltage is sensed and the power path FETs turn on and the voltage follows this ramp. When the voltage reaches the threshold VTHSS, the power path FET will be near being fully turned on, the output voltage will be fully charged. At time TSSDONE, a signal to the digital core indicates that the soft start function has completed. The ramp rate of the supply is given by Equation 4: ISS Ramp Rate = 9 ´ CSS (4) The maximum ramp voltage for the supply is approximately 16.2 V. For any input voltage higher than this, the ramp will stop at 16.2 V until the firmware disables the soft start. At this point, the voltage will step to the input voltage at a ramp rate defined by approximately 7 μA into the gate capacitance of the switch. The TSSDONE time is independent of the actual final ramp voltage. 8.3.3.17 BUSPOWERZ At power-up, when VIN_3V3 is not present and a dead-battery condition is supported as described in DeadBattery or No-Battery Support, the TPS65982 will appear as a USB Type-C sink (device) causing a connected USB Type-C source (host) to provide 5 V on VBUS. The TPS65982 will power itself from the 5-V VBUS rail (see Power Management) and execute boot code (see Boot Code). The boot code will observe the BUSPOWERZ voltage, which will fall into one of three voltage ranges: VBPZ_DIS, VBPZ_HV, and VBPZ_EXT (defined in BUSPOWERZ Configuration Requirements). These three voltage ranges configure how the TPS65982 routes the 5 V present on VBUS to the system in a dead-battery or no-battery scenario. When the voltage on BUSPOWERZ is in the VBPZ_DIS range (when a 100-kΩ pull-up resistor is tied from BUSPOWERZ to LDO_3V3 as in Figure 31), this indicates that the TPS65982 will not route the 5 V present on VBUS to the entire system. In this case, the TPS65982 will load SPI-connected flash memory and execute this application code. This configuration will disable both the PP_HV and PP_EXT high voltage switches and only use VBUS to power the TPS65982. LDO_3V3 LDO_1V8D BUSPOWERZ ADC Figure 31. BUSPOWERZ Configured to Disable Power from VBUS The BUSPOWERZ pin can alternately configure the TPS65982 to power the entire system through the PP_HV internal load switch when the voltage on BUSPOWERZ is in the VBPZ_HV range (when a 100-kΩ pull-up resistor is tied from BUSPOWERZ to LDO_1V8D as in Figure 32). LDO_3V3 LDO_1V8D BUSPOWERZ ADC Figure 32. BUSPOWERZ Configured with PP_HV as Input Power Path 42 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 The BUSPOWERZ pin can also alternately configure the TPS65982 to power the entire system through the PP_EXT external load switch when the voltage on BUSPOWERZ is in the VBPZ_EXT range (as in Figure 33). LDO_3V3 LDO_1V8D BUSPOWERZ ADC Figure 33. BUSPOWERZ Configured with PP_EXT as Input Power Path 8.3.3.18 Voltage Transitions on VBUS through Port Power Switches Figure 34 shows the waveform for a positive voltage transition. The timing and voltages apply to both a transition from 0 V to PP_5V0 and a transition from PP_5V0 to PP_HV as well as a transition from PP_5V0 to an PP_EXT. A transition from PP_HV to PP_EXT is possible and vice versa, but does not necessarily follow the constraints in Figure 34. When a switch is closed to transition the voltage, a maximum slew-rate of SRPOS occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches VSRCVALID within the final voltage. The voltage may overshoot the new voltage by VSRCVALID. After time TSTABLE from the start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage. VSRCVALID (max) VSRCNEW (max) New Voltage Voltage VSRCNEW (min) VSRCVALID (min) SRPOS Old Voltage TSTABLE Time Figure 34. Positive Voltage Transition on VBUS Figure 35 shows the waveform for a negative voltage transition. The timing and voltages apply to both a transition from PP_HV to PP_5V0 and a transition from PP_5V0 to 0V as well as a transition from PP_EXT to PP_5V0. A transition from PP_HV to PP_EXT is possible and vice versa, but does not necessarily follow the constraints in Figure 35. When a switch is closed to transition the voltage, a maximum slew-rate of SRNEG occurs on the transition. The voltage ramp will remain monotonic until the voltage reaches TOLTRANUN within the final voltage. The voltage may overshoot the new voltage by TOLTRANLN. After time TSTABLE from the start of the transition, the voltage will fall to within VSRCNEW of the new voltage. During the time TSTABLE, the voltage may fall below the new voltage, but will remain within VSRCNEW of this voltage. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 43 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com TSTABLE Old Voltage Voltage SRNEG VSRCVALID (max) VSRCNEW (max) New Voltage VSRCNEW (min) VSRCVALID (min) Time Figure 35. Negative Voltage Transition on VBUS 8.3.3.19 HV Transition to PP_RV0 Pull-Down on VBUS The TPS65982 has an integrated active pull-down on VBUS when transitioning from PP_HV to PP_5V0, shown in Figure 36. When the PP_HV switch is disabled and VBUS > PP_5V0 + VHVDISPD, amplifier turns on a current source and pulls down on VBUS. The amplifier implements active slew rate control by adjusting the pulldown current to prevent the slew rate from exceeding specification. When VBUS falls to within VHVDISPD of PP_5V0, the pull-down is turned off. The load on VBUS will then continue to pull VBUS down until the ideal diode switch structure turns on connecting it to PP_5V0. When switching from PP_HV or PP_EXT to PP_5V0, PP_HV or PP_EXT must be above VSO_HV to follow the switch-over shown in Figure 35. PP_5V0 Gate Control and Current Limit PP_5V0 VBUS Fast current limit VHVDISPD Slew Rate Controlled Pulldown Figure 36. PP_5V0 Slew Rate Control 8.3.3.20 VBUS Transition to VSAVE0V When VBUS transitions to near 0 V (VSAFE0V), the pull-down circuit in Figure 36 is turned on until VBUS reaches VSAFE0V. This transition will occur within time TSAFE0V. 8.3.3.21 C_CC1 and C_CC2 Power Configuration and Power Delivery The C_CC1 and C_CC2 pins are used to deliver power to active circuitry inside a connected cable and output USB-PD data to the cable and connected device. Figure 20 shows the C_CC1, and C_CC2 outputs to the port. Only one of these pins will be used to deliver power at a time depending on the cable orientation. The other pin will be used to transmit USB-PD data through the cable to a connected device. 44 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Figure 37 shows a high-level flow of connecting these pins based on the cable orientation. See the Cable Plug and Orientation Detection section for more detailed information on plug and orientation detection. Firmware Loaded Wait for Plug no Plug Detected? yes Detect Type and Orientation Connect C_CC1 to USB-PD Phy no C_CC2 Powered? C_CC2 Open yes C_CC1 = Data line? yes Connect C_CC2 to PP_CABLE Connect C_CC2 to USB-PD Phy no yes Connect C_CC1 to PP_CABLE no C_CC1 Powered? C_CC1 Open Figure 37. Port C_CC and VCONN Connection Flow Figure 38 and Figure 39 show the two paths from PP_CABLE to the C_CCn pins. When one C_CCn pin is powered from PP_CABLE, the other is connected to the USB-PD BMC modem. The red line shows the power path and the green line shows the data path. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 45 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Fast current limit PP_CABLE C_CC1/2 Gate Control and Current Limit C_CC1 Gate Control LDO_3V3 USB-PD Data USB-PD Phy Digital Core LDO_3V3 C_CC1 CC C_CC2 VCONN Power Active Cable Circuitry Cable Plug C_CC2 Gate Control Figure 38. Port C_CC1 and C_CC2 Normal Orientation Power from PP_CABLE Fast current limit PP_CABLE C_CC1/2 Gate Control and Current Limit C_CC1 Gate Control LDO_3V3 Cable Plug Active Cable Circuitry Digital Core USB-PD Phy LDO_3V3 C_CC1 VCONN C_CC2 CC Power USB-PD Data C_CC2 Gate Control Figure 39. Port C_CC1 and C_CC2 Reverse Orientation Power from PP_CABLE 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 8.3.3.22 PP_CABLE to C_CC1 and C_CC2 Switch Architecture Figure 20 shows the switch architecture for the PP_CABLE switch path to the C_CCc pins. Each path provides a unidirectional current from PP_CABLE to C_CC1 and C_CC2. The switch structure blocks reverse current from C_CC1 or C_CC2 to PP_CABLE. 8.3.3.23 PP_CABLE to C_CC1 and C_CC2 Current Limit The PP_CABLE to C_CC1 and C_CC2 share current limiting through a single FET on the PP_CABLE side of the switch. The current limit ILIMPPCC is adjustable between two levels. When the current exceeds ILIMPPCC, the current-limit circuit activates. Depending on the severity of the over-current condition, the transient response will react in one of two ways: Figure 40 and Figure 41 show the approximate response time and clamping characteristics of the circuit for a hard short while Figure 42 shows the approximate response time and clamping characteristics for a soft short. The switch does not have reverse current blocking when the switch is enabled and current is flowing to either C_CC1 or C_CC2. 10 I CC2 C_CC2 8 PP_CABLE Current (A) 6 5 6 4 4 3 2 2 0 1 -2 0 Voltage (V) 7 -4 Time (10 Ps/div) D009 6 6 5 5 4 4 3 2 3 I CC2 C_CC2 PP_CABLE 2 1 1 0 0 -1 Voltage (V) Current (A) Figure 40. PP_CABLE to C_CCn Current Limit with a Hard Short -1 Time (500 Ps/div) D010 Figure 41. PP_CABLE to C_CCn Current Limit with a Hard Short (Extended Time Base) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 47 TPS65982 www.ti.com 3 6 2.5 5 2 4 1.5 3 1 2 0.5 1 Voltage (V) Current (A) SLVSD02A – MARCH 2015 – REVISED JUNE 2015 I CC2 0 C_CC2 PP_CABLE -1 0 -0.5 Time (50 Ps/div) D011 Figure 42. PP_CABLE to C_CCn Current Limit Response with a Soft Short (2 Ω) 8.3.4 USB Type-C Port Data Multiplexer The USB Type-C receptacle pin configuration is show in Figure 43. Not all signals shown are required for all platforms or devices. The basic functionality of the pins deliver USB 2.0 (D+ and D-) and USB 3.1 (TX and RX pairs) data buses, USB power (VBUS) and ground (GND). Configuration Channel signals (CC1 and CC2), and two Reserved for Future Use (SBU) signal pins. The data bus pins (Top and Bottom D+/D- and the SBU pins) are available to be used in non-USB applications as an Alternate Mode (i.e., DisplayPort, Thunderbolt™, etc.). A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A11 A12 GND TX1+ TX1– VBUS CC1 D+ D– SBU1 VBUS RX2– RX2+ GND GND RX1+ RX1– VBUS SBU2 D– D+ CC2 VBUS TX2– TX2+ GND B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 Figure 43. USB Type-C Receptacle Pin Configuration The TPS65982 USB Type-C interface multiplexers are shown in Table 2. The outputs are determined based on detected cable orientation as well as the identified interface that is connected to the port. There are two USB output ports that may or may not be passing USB data. When an Alternate Mode is connected, these same ports may also pass that data (e.g. DisplayPort, Thunderbolt). Note, the TPS65982 pin to receptacle mapping is shown in Table 2. The high-speed RX and TX pairs are not mapped through the TPS65982 as this would place extra resistance and stubs on the high-speed lines and degrade signal performance. Table 2. TPS65982 to USB Type-C Receptacle Mapping 48 DEVICE PIN Type-C RECEPTACLE PIN VBUS VBUS (A4, A9, B4, B9) C_CC1 CC1 (A5) C_CC2 CC2 (B5) C_USB_TP D+ (A6) C_USB_TN D– (A7) C_USB_BP D+ (B6) C_USB_BN D– (B7) C_SBU1 SBU1 (A8) C_SBU2 SBU2 (B8) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 SWD_DATA SWD_CLK GPIO1 GPIO2 GPIO UART0 1st Stage Digital Cross-Bar Mux UART1 UART0 UART1 CORE_ UART0 CORE_ UART1 2nd Stage SWD CORE_ UART2 Digital Core SWD_CLK/DATA C_USB_TP USB_EP_P/N USB_RP_P/N C_USB_TN DEBUG1/2 DEBUG3/4 UART_TX UART_RX Charger ID LSX_P2R To ADC SBU_INT1 SBU_INT2 LSX_R2P SWD_CLK/DATA USB_RP_P USB_RP USB_RP_N DEBUG1 DEBUG1/2 C_USB_BP USB_RP_P/N USB_EP_P/N DEBUG1/2 DEBUG3/4 C_USB_BN DEBUG2 DEBUG3 DEBUG3/4 DEBUG4 SWD_CLK/DATA SBU_INT1 AUX_P AUX_P/N C_SBU1 SBU_INT2 C_SBU2 AUX_N DEBUG1/2 DEBUG3/4 AUX_P/N Figure 44. Port Data Multiplexers Table 3 shows the typical signal types through the switch path. The UART_RX/TX and LSX_P2R/R2P paths are digitally buffered to allow tri-state control for these paths. All other switches are analog pass switches. The LSX_P2R/R2P pair is also configurable to be analog pass switches as well. These switch paths are not limited to the specified signal type. For the signals that interface with the digital core, the maximum data rate is dictated by the clock rate at which the core is running. Table 3. Typical Signals through Analog Switch Path INPUT PATH SWD_DATA/CLK SIGNAL TYPE SIGNAL FUNCTION Single Ended Data, Clock UART_RX/TX Single Ended TX/Rx UART LSX_P2R/R2P Single Ended TX/Rx UART DEBUG1/2/3/4 Single Ended Debug AUX_P/N Differential DisplayPort and Thunderbolt AUX channel USB_EP_P/N Differential USB 2.0 Low Speed Endpoint USB_RP_P/N Differential USB 2.0 High Speed Data Root Port Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 49 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.4.1 USB Top and Bottom Ports The Top (C_USB_TP and C_USB_TN) and Bottom (C_USB_BP and C_USB_BN) ports that correspond to the Type-C top and bottom USB D+/D– pairs are swapped based on the detected cable orientation. The symmetric pin order shown in Figure 43 from the A-side to the B-side allows the pins to connect to equivalent pins on the opposite side when the cable orientation is reversed. 8.3.4.2 Multiplexer Connection Orientation Table 4 shows the multiplexer connection orientation. For the USB D+/D– pair top and bottom port connections, these connections are fixed. For the SBU port connections, the SBU crossbar multiplexer enables flipping of the signal pair and the connections shown are for the upside-up orientation. The CORE_UARTn connections come from a digital crossbar multiplexer that allows the UART_RX/TX, LSX_P2R/R2P, and GPIO1/2 to be mapped to any of the 1st stage multiplexers. Table 4. Data Multiplexer Connections SYSTEM PIN USB TOP PIN USB BOTTOM PIN USB_RP_P C_USB_TP C_USB_BP USB_RP_N C_USB_TN C_USB_BN SBU MULTIPLEXER PIN USB_EP_P C_USB_TP C_USB_BP USB_EP_N C_USB_TN C_USB_BN SWD_CLK C_USB_TP C_USB_BP SBU1 SWD_DATA C_USB_TN C_USB_BN SBU2 DEBUG1 C_USB_TP C_USB_BP SBU1 DEBUG2 C_USB_TN C_USB_BN SBU2 DEBUG3 C_USB_TP C_USB_BP SBU1 DEBUG4 C_USB_TN C_USB_BN SBU2 AUX_P C_USB_TP C_USB_BP SBU1 AUX_N C_USB_TN C_USB_BN SBU2 LSX_R2P SBU1 LSX_P2R SBU2 CORE_UART0_TX C_USB_TP CORE_UART0_RX C_USB_TN CORE_UART1_TX C_USB_BP CORE_UART1_RX C_USB_BN CORE_UART2_TX SBU1 CORE_UART2_RX SBU2 8.3.4.3 Digital Crossbar Multiplexer The TPS65982 UART paths (UART_RX/TX and LSX_P2R/R2P) and GPIO1/2 all have digital inputs that pass through a cross-bar multiplexer inside the digital core. Each of these pins is configurable as an input or output of the cross-bar multiplexer. The digital cross-bar multiplexer then connects to the port data multiplexers as shown in Figure 44. The connections are configurable via firmware. The default state at power-up is to connect a buffered version of UART_RX to UART_TX providing a bypass through the TPS65982 for daisy chaining during power on reset. 8.3.4.4 SBU Crossbar Multiplexer The SBU Crossbar Multiplexer provides pins (C_SBU1 and C_SBU2) for future USB functionality as well as Alternate Modes. The multiplexer swaps the output pair orientation based on the cable orientation. For more information on Alternate Modes, refer to the USB PD Specification. 50 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 8.3.4.5 Signal Monitoring and Pull-up/Pull-down The TPS65982 has comparators that may be enabled to interrupt the core when a switching event occurs on any of the port inputs. The input parameters for the detection are shown in Port Data Multiplexer Signal Monitoring Pull-Up and Pull-Down Characteristics. These comparators are disconnected by application code when these pins are not digital signals but an analog voltage. The TPS65982 has pull-ups and pull-downs between the first and second stage multiplexers of the port switch for each port output: C_SBU1/2, C_USB_TP/N, C_USB_BP/N. The configurable pull-up and pull-down resistances between each multiplexer are shown in Figure 45. LDO_3V3 LDO_3V3 RP100 RP5 To Digital Core 1st Stage Mux 2nd Stage Mux RPD1 LDO_3V3 RP5 RP100 LDO_3V3 RP100 RP5 To Digital Core RPD1 RP5 RP100 Figure 45. Port Detect and Pull-up/Pull-down 8.3.4.6 Port Multiplexer Clamp Each input to the 2nd stage multiplexer is clamped to prevent voltages on the port from exceeding the safe operating voltage of circuits attached to the system side of the Port Data Multiplexer. Figure 46 shows the simplified clamping circuit. When a path through the 2nd stage multiplexer is closed, the clamp is connected to the one of the port pins (C_USB_TP/N, C_USB_BP/N, C_SBU1/2). When a path through the 2nd stage multiplexer is not closed, then the port pin is not clamped. As the pin voltage rises above the VCLMP_IND voltage, the clamping circuit activates, and sinks current to ground, preventing the voltage from rising further. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 51 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 2nd Stage Mux Input VREF Figure 46. Port Mux Clamp 8.3.4.7 USB2.0 Low-Speed Endpoint The USB low-speed Endpoint is a USB 2.0 low-speed (1.5 Mbps) interface used to support HID class based accesses. The TPS65982 supports control of endpoint EP0. This endpoint enumerates to a USB 2.0 bus to provide USB-Billboard information to a host system as defined in the USB Type-C standard. EP0 is used for advertising the Billboard Class. When a host is connected to a device that provides Alternate Modes which cannot be supported by the host, the Billboard class allows a means for the host to report back to the user without any silent failures. Figure 47 shows the USB Endpoint physical layer. The physical layer consists of the analog transceiver, the Serial Interface Engine, and the Endpoint FIFOs and supports low speed operation. USB_EP LDO_3V3 RPU_EP To Digital Core Digital Core Interrupts and Control 32 EP0 (EP1) TX/RX FIFO RX/TX Status Control Serial Interface Engine EP_TX_DP RS_EP EP_TX_DN RS_EP C_USB_TP USB_RP C_USB_TN 1st Stage Mux 2nd Stage Mux USB_EP EP_RX_RCV C_USB_BP USB_RP C_USB_BN 1st Stage Mux EP_RX_DP 2nd Stage Mux EP_RX_DN Transceiver Figure 47. USB Endpoint Phy 52 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 The transceiver is made up of a fully differential output driver, a differential to single-ended receive buffer and two single-ended receive buffers on the D+/D- independently. The output driver drives the D+/D- of the selected output of the Port Multiplexer. The signals pass through the 2nd Stage Port Data Multiplexer to the port pins. When driving, the signal is driven through a source resistance RS_EP. RS_EP is shown as a single resistor in USB Endpoint Phy but this resistance also includes the resistance of the 2nd Stage Port Data Multiplexer defined in Port Data Multiplexer Requirements and Characteristics. RPU_EP is disconnected during transmit mode of the transceiver. When the endpoint is in receive mode, the resistance RPU_EP is connected to the D- pin of the top or bottom port (C_USB_TN or C_USB_BN) depending on the detected orientation of the cable. The RPU_EP resistance advertises low speed mode only. 8.3.4.8 Battery Charger (BC1.2) Detection Block The battery charger (BC1.2) detection block integrates circuitry to detect when the connected entity on the USB D+/D- pins is a charger. To enable the required detection mechanisms, the block integrates various voltage sources, currents, and resistances to the Port Data Multiplexers. Figure 48 shows the connections of these elements to the Port Data Multiplexers. VLGC_HI IDP_SRC C_USB_TP USB_RP To ADC USB_EP To ADC USB_RP USB_EP VDX_SRC RDM_DWN C_USB_TN C_USB_BP C_USB_BN IDX_SNK Figure 48. BC1.2 Detection Circuitry 8.3.4.9 BC1.2 Data Contact Detect Data Contact Detect follows the definition in the USB BC1.2 specification. The detection scheme sources a current IDP_SRC into the D+ pin of the USB connection. The current is sourced into either the C_USB_TP (top) or C_USB_BP (bottom) D+ pin based on the determined cable/device orientation. A resistance RDM_DWN is connected between the D- pin and GND. Again, this resistance is connected to either the C_USB_TN (top) or C_USB_BN (bottom) D- pin based on the determined cable/device orientation. The middle section of Figure 48, the current source IDP_SRC and the pull-down resistance RDM_DWN, is activated during data contact detection. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 53 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.4.10 BC1.2 Primary and Secondary Detection The Primary and Secondary Detection follow the USB BC1.2 specification. This detection scheme looks for a resistance between D+ and D- lines by forcing a known voltage on the first line, forcing a current sink on the second line and then reading the voltage on the second line using the general purpose ADC integrated in the TPS65982. To provide complete flexibility, 12 independent switches are connected to allow firmware to force voltage, sink current, and read voltage on any of the C_USB_TP, C_USB_TN, C_USB_BP, and C_USB_BN. The left and right sections of Figure 48, the voltage source VDX_SRC and the current source IDX_SNK, are activated during primary and secondary detection. 8.3.5 Power Management The TPS65982 Power Management block receives power and generates voltages to provide power to the TPS65982 internal circuitry. These generated power rails are LDO_3V3, LDO_1V8A, and LDO_1V8D. LDO_3V3 is also a low power output to load flash memory. VOUT_3V3 is a low power output that does not power internal circuitry that is controlled by application code and can be used to power other ICs in some applications. The power supply path is shown in Figure 49. S1 VIN_3V3 VBUS S2 VOUT_3V3 VREF LDO EN VREF LDO_3V3_VB_EN To Digital Core Digitally adjustable trip Point LDO_3V3 VREF LDO_1V8D LDO EN LDO_1V8A LDO_1V8A_EN LDO EN VREF LDO_1V8D_EN Figure 49. Power Supply Path The TPS65982 is powered from either VIN_3V3 or VBUS. The normal power supply input is VIN_3V3. In this mode, current flows from VIN_3V3 to LDO_3V3 to power the core 3.3 V circuitry and the 3.3 V I/Os. A second LDO steps the voltage down from LDO_3V3 to LDO_1V8D and LDO_1V8A to power the 1.8 V core digital circuitry and 1.8 V analog circuits. When VIN_3V3 power is unavailable and power is available on the VBUS, the TPS65982 will be powered from VBUS. In this mode, the voltage on VBUS is stepped down through an LDO to LDO_3V3. Switch S1 in Figure 49 is unidirectional and no current will flow from LDO_3V3 to VIN_3V3 or VOUT_3V3. When VIN_3V3 is unavailable, this is an indicator that there is a dead-battery or no-battery condition. 8.3.5.1 Power-On and Supervisory Functions A power-on-reset (POR) circuit monitors each supply. This POR allows active circuitry to turn on only when a good supply is present. In addition to the POR and supervisory circuits for the internal supplies, a separate programmable voltage supervisor monitors the VOUT_3V3 voltage. 54 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 8.3.5.2 Supply Switch-Over VIN_3V3 takes precedence over VBUS, meaning that when both supply voltages are present the TPS65982 will power from VIN_3V3. Refer to The Figure 49 for a diagram showing the power supply path block. There are two cases in with a power supply switch-over will occur. The first is when VBUS is present first and then VIN_3V3 becomes available. In this case, the supply will automatically switch-over to VIN_3V3 and brown-out prevention is verified by design. The other way a supply switch-over will occur is when both supplies are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65982 occurs prompting a reboot. 8.3.5.3 RESETZ and MRESET The VIN_3V3 voltage is connected to the VOUT_3V3 output by a single FET switch (S2 in Figure 49). The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable. A supervisor circuit monitors the voltage at VOUT_3V3 for an under-voltage condition and sets the external indicator RESETZ. The RESETZ pin is active low (low when an under-voltage condition occurs). The RESETZ output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but is configurable to be active low. Figure 4 shows the RESETZ timing with MRESET set to active high. When VOUT_3V3 is disabled, a resistance of RPDOUT_3V3 pulls down on the pin. 8.3.6 Digital Core Figure 50 shows a simplified block diagram of the digital core. This diagram shows the interface between the digital and analog portions of the TPS65982. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 55 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com MRESET RESETZ GPIO0-8 BUSPOWERZ I2C_ADDR R_OSC OSC I2C Debug Port DEBUG_CTL1 DEBUG_CTL2 I2C_SDA1 I2C to System Control I2C Port 1 I2C_SCL1 CBL_DET Bias CTL and USB-PD I2C_IRQ1Z USB PD Phy I2C_SDA2 I2C to Auxiliary Control I2C Port 2 I2C_SCL2 Digital Core I2C_IRQ2Z SPI_CLK SPI to Flash SPI_MOSI SPI SPI_MISO SPI_SSZ SWD_DATA SWD SWD_CLK ADC Read ADC Temp Sense Signals into ADC Thermal Shutdown UART_TX UART0 UART_RX USB EP LSX_P2R UART1 USB EP Phy LSX_R2P Figure 50. Digital Core Block Diagram 8.3.7 USB-PD BMC Modem Interface The USB-PD BMC modem interface is a fully USB-PD compliant Type-C interface. The modem contains the BMC encoder/decoder, the TX/Rx FIFOs, the packet engine for construction/deconstruction of the USB-PD packet. This module contains programmable SOP values and processes all SOP headers. 8.3.8 System Glue Logic The system glue logic module performs various system interface functions such as control of the system interface for RESETZ, MRESET, and VOUT_3V3. This module supports various hardware timers for digital control of analog circuits. 8.3.9 Power Reset Congrol Module (PRCM) The PRCM implements all clock management, reset control, and sleep mode control. 56 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 8.3.10 Interrupt Monitor The Interrupt Control module handles all interrupt from the external GPIO as well as interrupts from internal analog circuits. 8.3.11 ADC Sense The ADC Sense module is a digital interface to the SAR ADC. The ADC converts various voltages and currents from the analog circuits. The ADC converts up to 11 channels from analog levels to digital signals. The ADC can be programmed to convert a single sampled value. 8.3.12 UART Two digital UARTS are provided for serial communication. The inputs to the UART are selectable by a programmable digital crossbar multiplexer. The UART may act as pass-through between the system and the Type-C port or may filter through the digital core. The UART_RX/TX pins are typically used to daisy chain multiple TPS65982s in series to share application code at startup. 8.3.13 I2C Slave Two I2C interfaces provide interface to the digital core from the system. These interfaces are master/slave configurable and support low-speed and full-speed signaling. See the I2C Slave Interface section for more information. 8.3.14 SPI Master The SPI master provides a serial interface to an external flash memory. The recommended memory is the W25Q80DV 8 Mbit Serial Flash Memory. A memory of at least 2 Mbit is required when the TPS65982 is using the memory in an unshared manner. A memory of at least 8 Mbit is required when the TPS65982 is using the memory in an shared manner. See theSPI Master Interface section for more information. 8.3.15 Single-Wire Debugger Interface The SWD interface provides a mechanism to directly master the digital core. 8.3.16 DisplayPort HPD Timers To enable DisplayPort HPD signaling through PD messaging, two GPIO pins (GPIO4, GPIO5) are used as the HPD input and output. When events occur on this pins during a DisplayPort connection through the Type-C connector (configured in firmware), hardware timers trigger and interrupt the digital core to indicated needed PD messaging. Table 5 shows each I/O function when GPIO4/5 are configured in HPD mode. When HPD is not enabled via firmware, both GPIO4 and GPIO5 remain generic GPIO and may be programmed for other functions. Figure 51 and Figure 52. Table 5. HPD GPIO Configuration HPD (Binary) Configuration GPIO4 GPIO5 00 HPD TX Generic GPIO 01 HPD RX Generic GPIO 10 HPD TX HPD RX 11 HPD TX/RX (bidirectional) Generic GPIO Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 57 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Enter DP Alternate Mode Firmware enables HPD RX S0: HPD Low Wait State HPD GPIO is low HPD GPIO is High Start HPD Timer HPD GPIO goes low before Timer reaches High_Debounce S1: HPD High Debounce State Timer passes High_Debounce Generate HPD_High interrupt, Stop HPD Timer S2: HPD High Wait State HPD GPIO is high HPD GPIO is low Start HPD Timer Generate HPD_LOW Interrupt, Stop HPD Timer HPD GPIO goes high before Timer reaches Low_Debounce S3: HPD Low Debounce State Timer passes Low_Debounce Timer Passes IRQ_Limit S4: HPD IRQ Detect State Generate HPD_IRQ Interrupt HPD GPIO goes high before Timer reaches IRQ_Limit Figure 51. HPD RX Flow 58 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 DP Confiuration Enabled Firmware enables HPD TX Drive HPD GPIO Low S0: HPD Low Wait State Receive any Receive HPD_HIGH Event other HPD Event Start HPD Timer S1: HPD First High State Timer Passes 2ms_Minimum Drive HPD GPIO High Timer Passes Stop HPD Timer 2ms_Minimum S2: HPD High Idle State S6: HPD High Hold State Reset HPD Timer, Drive HPD High Timer Passes IRQ_MIN Receive Receive HPD_IRQ HPD_LOW Event Event Start HPD Timer, Drive HPD Low Start HPD Timer, Drive HPD Low S3: HPD IRQ State S4: HPD Low State Receive HPD_High Event Timer passes 2ms_Minimum Receive HPD_HIGH Event S5: HPD Low Idle State Receive any other HPD Event Figure 52. HPD TX Flow Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 59 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.17 ADC The TPS65982 ADC is shown in Figure 53. The ADC is a 10-bit successive approximation ADC. The input to the ADC is an analog input multiplexer that supports multiple inputs from various voltages and currents in the device. The output from the ADC is available to be read and used by application firmware. Each supply voltage into the TPS65982 is available to be converted including the port power path inputs and outputs. All GPIO, the C_CCn pins, the charger detection voltages are also available for conversion. To read the port power path current sourced to VBUS, the high-voltage and low-voltage power paths are sensed and converted to voltages to be read by the ADC. For the external FET path, the difference in the SENSEP and SENSEN voltages is converted to detect the current (I_PP_EXT) that is sourced through this path. GPIO0 GPIO0-9 C_CC1 C_CC2 BC_ID VBUS PP_HV PP_5V0 PP_CABLE VIN_3V3 VOUT_3V3 LDO_3V3 LDO_1V8A LDO_1V8D SENSEP SENSEP-SENSEN (I_PP_EXT) I2C_ADDR Buffers Voltage Dividers 10 bits Input SAR ADC Mux Thermal Sense IPP_HV IPP_5V0 IPP_CABLE I-to-V Figure 53. SAR ADC 8.3.17.1 ADC Divider Ratios The ADC voltage inputs are each divided down to the full-scale input of 1.2 V. The ADC current sensing elements are not divided. Table 6 shows the divider ratios for each ADC input. The table also shows which inputs are auto-sequenced in the round robin automatic readout mode. The C_CC1 and C_CC2 pin voltages each have two conversions values. The divide-by-5 (CCn_BY5) conversion is intended for use when the C_CCn pin is configured as VCONN output and the divide-by-2 (CCn_BY2) conversion is intended for use when C_CCn pin is configured as the CC data pin. Table 6. ADC Divider Ratios CHANNEL # 60 SIGNAL TYPE AUTO-SEQUENCED DIVIDER RATIO BUFFERED Temperature Yes N/A No VBUS Voltage Yes 25 No SENSEP Voltage Yes 25 No 3 IPP_EXT Current Yes N/A No 4 PP_HV Voltage Yes 25 No 5 IPP_HV Current Yes N/A No 6 PP_5V0 Voltage Yes 5 No 7 IPP_5V0 Current Yes N/A No 8 CC1_BY5 Voltage Yes 5 Yes 0 Thermal Sense 1 2 9 IPP_CABLE Current Yes N/A No 10 CC2_BY5 Voltage Yes 5 Yes 11 GPIO5 Voltage No 1 No 12 CC1_BY2 Voltage No 2 Yes 13 CC2_BY2 Voltage No 2 Yes Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Table 6. ADC Divider Ratios (continued) CHANNEL # TYPE AUTO-SEQUENCED DIVIDER RATIO BUFFERED 14 PP_CABLE SIGNAL Voltage No 5 No 15 VIN_3V3 Voltage No 3 No 16 VOUT_3V3 Voltage No 3 No 17 BC_ID_SBU Voltage No 3 Yes 18 LDO_1V8A Voltage No 2 No 19 LDO_1V8D Voltage No 2 No 20 V3P3 Voltage No 3 No 21 I2C_ADDR Voltage No 3 Yes 22 GPIO0 Voltage No 3 Yes 23 GPIO1 Voltage No 3 Yes 24 GPIO2 Voltage No 3 Yes 25 GPIO3 Voltage No 3 Yes 26 GPIO4 Voltage No 3 Yes 27 GPIO5 Voltage No 3 Yes 28 GPIO6 Voltage No 3 Yes 29 GPIO7 Voltage No 3 Yes 30 GPIO8 Voltage No 3 Yes 31 BUSPOWERZ Voltage No 3 Yes 8.3.17.2 ADC Operating Modes The ADC is configured into one of three modes: single channel readout, round robin automatic readout and one time automatic readout. 8.3.17.3 Single Channel Readout In Single Channel Readout mode, the ADC reads a single channel only. Once the channel is selected by firmware, a conversion takes place followed by an interrupt back to the digital core. Figure 5 shows the timing diagram for a conversion starting with an ADC enable. When the ADC is disabled and then enabled, there is an enable time T_ADC_EN (programmable) before sampling occurs. Sampling of the input signal then occurs for time T_SAMPLE (programmable) and the conversion process takes time T_CONVERT (12 clock cycles). After time T_CONVERT, the output data is available for read and an Interrupt is sent to the digital core for time T_INTA (2 clock cycles). In Single Channel Readout mode, the ADC can be configured to continuously convert that channel. Figure 6 shows the ADC repeated conversion process. In this case, once the interrupt time has passed after a conversion, a new sample and conversion occurs. 8.3.17.4 Round Robin Automatic Readout When this mode is enabled, the ADC state machine will read from channel 0 to channel 11 and place the converted data into registers. The host interface can request to read from the registers at any time. During Round Robin Automatic Readout, the channel averaging must be set to 1 sample. When the TPS65982 is running a Round Robin Readout, it will take approximately 696 μs (11 channels × 63.33 μs conversion) to fully convert all channels. Since the conversion is continuous, when a channel is converted, it will overwrite the previous result. Therefore, when all channels are read, any given value may be 649 μs out of sync with any other value. 8.3.17.5 One Time Automatic Readout The One Time Automatic Readout mode is identical to the Round Robin Automatic Readout except the conversion process halts after the final channel is converted. Once all 11 channels are converted, an interrupt occurs to the digital core. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 61 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.18 I/O Buffers Table 7 lists the I/O buffer types and descriptions. Table 8 lists the pin to I/O buffer mapping for cross-referencing a pin’s particular I/O structure. The following sections show a simplified version of the architecture of each I/O buffer type. Table 7. I/O Buffer Type Description BUFFER TYPE DESCRIPTION IOBUF_GPIOHSSWD General Purpose High-Speed I/O IOBUF_GPIOHSSPI General Purpose High-Speed I/O IOBUF_GPIOLS General Purpose Low-Speed I/O IOBUF_GPIOLSI2C General Purpose Low-Speed I/O with I2C deglitch time IOBUF_I2C I2C Compliant Clock/Data Buffers IOBUF_OD Open-Drain Output IOBUF_UTX Push-Pull output buffer for UART IOBUF_URX Input buffer for UART IOBUF_PORT Input buffer between 1st/2nd stage Port Data Mux Table 8. Pin to I/O Buffer Mapping I/O GROUP/PIN BUFFER TYPE SUPPLY CONNECTION (DEFAULT FIRST) DEBUG1/2/3/4 IOBUF_GPIOLS LDO_3V3, VDDIO DEBUG_CTL1/2 IOBUF_GPIOLSI2C LDO_3V3, VDDIO BUSPOWERZ IOBUF_GPIOLS LDO_3V3, VDDIO GPIO0-8 IOBUF_GPIOLS LDO_3V3, VDDIO I2C_IRQ1/2Z IOBUF_OD LDO_3V3, VDDIO I2C_SDA1/2/SCL/1/2 IOBUF_I2C LDO_3V3, VDDIO LSX_P2R IOBUF_UTX LDO_3V3, VDDIO LSX_R2P IOBUF_URX LDO_3V3, VDDIO MRESET IOBUF_GPIOLS LDO_3V3, VDDIO RESETZ IOBUF_GPIOLS LDO_3V3, VDDIO UART_RX IOBUF_URX LDO_3V3, VDDIO UART_TX IOBUF_UTX LDO_3V3, VDDIO PORT_INT IOBUF_PORT LDO_3V3 SPI_MOSI/MISO/CLK/SSZ IOBUF_GPIOHSSPI LDO_3V3 SWD_CLK/DATA IOBUF_GPIOHSSWD LDO_3V3 8.3.18.1 IOBUF_GPIOLS and IOBUF_GPIOLSI2C Figure 54 shows the GPIO I/O buffer for all GPIOn pins listed GPIO0-GPIO17 in . GPIOn pins can be mapped to USB Type-C, USB PD, and application-specific events to control other ICs, interrupt a host processor, or receive input from another IC. This buffer is configurable to be a push-pull output, a weak push-pull, or open drain output. When configured as an input, the signal can be a de-glitched digital input or an analog input to the ADC. The push-pull output is a simple CMOS output with independent pull-down control allowing open-drain connections. The weak push-pull is also a CMOS output, but with GPIO_RPU resistance in series with the drain. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. For simplicity, the connection to VDDIO is not shown in Figure 54, but the connection to VDDIO is fail-safe and a diode will not be present from GPIOn to VDDIO in this configuration. The pull-up and pull-down output drivers are independently controlled from the input and are enabled or disabled via application code in the digital core. 62 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 LDO_3V3 GPIO_OD_EN GPIO_OE GPIO_DO GPIO_PU_EN GPIO_RPU GPIO_RPD GPIO_PD_EN 20 ns Deglitch GPIO GPIO_DI GPIO_AI_EN To ADC Figure 54. IOBUF_GPIOLS (General GPIO) I/O Figure 55 shows the IOBUF_GPIOLSI2C that is identical to IOBUF_GPIOLS with an extended de-glitch time. LDO_3V3 GPIO_OD_EN GPIO_OE GPIO_DO GPIO_PU_EN GPIO_RPU GPIO_RPD GPIO_PD_EN 50 ns Deglitch DEBUG_CTL1/2 GPIO_DI GPIO_AI_EN To ADC Figure 55. IOBUF_GPIOLSI2C (General GPIO) I/O with I2C Deglitch 8.3.18.2 IOBUF_OD The open-drain output driver is shown in Figure 56 and is the same push-pull CMOS output driver as the GPIO buffer. The output has independent pull-down control allowing open-drain connections. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 63 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com OD OD_DO Figure 56. IOBUF_OD Output Buffer 8.3.18.3 IOBUF_UTX The push-pull output driver is shown in Figure 57. The output buffer has a UARTTX_RO source resistance. The supply voltage to the system side buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 57. The supply voltage to the port side buffers remains LDO_3V3. UARTTX_RO UART_TX CMOS Output UART_TXout Figure 57. IOBUF_UTX Output Buffer 8.3.18.4 IOBUF_URX The input buffer is shown in Figure 58. The supply voltage to the system side buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 58. The supply voltage to the port side buffers remains LDO_3V3. UART_RX UART_RXin Figure 58. IOBUF_URX Input 8.3.18.5 IOBUF_PORT The input buffer is shown in Figure 59. This input buffer is connected to the intermediate nodes between the 1st stage switch and the 2nd stage switch for each port output (C_SBU1/2, C_USB_TP/N, C_USB_BN/P). The input buffer is enabled via firmware when monitoring digital signals and disabled when an analog signal is desired. See theFigure 45 section for more detail on the pull-up and pull-down resistors of the intermediate node. PORT_intx PORT_DETx EN Figure 59. IOBUF_PORT Input Buffer 8.3.18.6 IOBUF_I2C The I2C I/O driver is shown in Figure 60. This I/O consists of an open-drain output and an input comparator with de-glitching. The supply voltage to this buffer is configurable to be LDO_3V3 by default or VDDIO. This is not shown in Figure 60. Parameters for the I2C clock and data I/Os are found in I2C Slave Requirements and Characteristics. 64 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 50 ns Deglitch I2C_DI I2C_IRQnZ I2C_DO Figure 60. IOBUF_I2C I/O 8.3.18.7 IOBUF_GPIOHSPI Figure 61 shows the I/O buffers for the SPI interface. SPIin SPI_x CMOS Output SPIout SPI_OE Figure 61. IOBUF_GPIOHSSPI 8.3.18.8 IOBUF_GPIOHSSWD Figure 62 shows the I/O buffers for the SWD interface. The CLK input path is a comparator with a pull-up SWD_RPU on the pin. The data I/O consists of an identical input structure as the CLK input but with a tri-state CMOS output driver. LDO_3V3 SWD_RPU SWD_CLK SWDCLKin LDO_3V3 SWD_RPU SWD_DATA SWDIOin CMOS Output SWDIOout SWD_OE Figure 62. IOBUF_GPIOHSSWD Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 65 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.3.19 Thermal Shutdown The TPS65982 has both a central thermal shutdown to the chip and a local thermal shutdown for the power path block. The central thermal shutdown monitors the temperature of the center of the die and disables all functions except for supervisory circuitry and halts digital core when die temperature goes above a rising temperature of TSD_MAIN. The temperature shutdown has a hysteresis of TSDH_MAIN and when the temperature falls back below this value, the device resumes normal operation. The power path block has its own local thermal shutdown circuit to detect an over temperature condition due to over current and quickly turn off the power switches. The power path thermal shutdown values are TSD_PWR and TSDH_PWR. The output of the thermal shutdown circuit is de-glitched by TSD_DG before triggering. The thermal shutdown circuits interrupt to the digital core. 8.3.20 Oscillators The TPS65982 has two independent oscillators for generating internal clock domains. A 48-MHz oscillator generates clocks for the core during normal operation and clocks for the USB 2.0 endpoint physical layer. An external resistance is placed on the R_OSC pin to set the oscillator accuracy. A 100-kHz oscillator generates clocks for various timers and clocking the core during low-power states. 8.4 Device Functional Modes 8.4.1 Boot Code The TPS65982 has a Power-on-Reset (POR) circuit that monitors LDO_3V3 and issues an internal reset signal. The digital core, memory banks, and peripherals receive clock and RESET interrupt is issued to the digital core and the boot code starts executing. Figure 63 provides the TPS65982 boot code sequence. The TPS65982 boot code is loaded from OTP on POR, and begins initializing TPS65982 settings. This initialization includes enabling and resetting internal registers, loading trim values, waiting for the trim values to settle, and configuring the device I2C addresses. The unique I2C address is based on the customer programmable OTP, DEBUG_CTLX pins, and resistor configuration on the I2C_ADDR pin. Once initial device configuration is complete the boot code determines if the TPS65982 is booting under dead battery condition (VIN_3V3 invalid, VBUS valid). If the boot code determines the TPS65982 is booting under dead battery condition, the BUSPOWERZ pin is sampled to determine the appropriate path for routing VBUS power to the system. 66 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Device Functional Modes (continued) VIN_3V3 or VBUS Application Initialize Configure I2C Dead Battery Check SPI_MISO High Load Appcode SPI_MISO Low Load from SPI Download from Flash UART Figure 63. Flow Diagram for Boot Code Sequence 8.4.2 Initialization During initialization the TPS65982 enables device internal hardware and loads default configurations. The 48MHz clock is enabled and the TPS65982 persistence counters begin monitoring VBUS and VIN_3V3. These counters ensure the supply powering the TPS65982 is stable before continuing the initialization process. The initialization concludes by enabling the thermal monitoring blocks and thermal shutdown protection, along with the ADC, CRC, GPIO and NVIC blocks. 8.4.3 I2C Configuration The TPS65982 features dual I2C busses with configurable addresses. The I2C addresses are determined according to the flow depicted in Figure 64. The address is configured by reading device GPIO states at boot (refer to the I2C Pin Address Setting section for details). Once the I2C addresses are established the TPS65982 enables a limited host interface to allow for communication with the device during the boot process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 67 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Device Functional Modes (continued) Initialization Complete Read state of DEBUG_CTL1 DEBUG_CTL2 I2C_ADDR Configure I2C Address Initialize Host Interface Figure 64. I2C Address Configuration 8.4.4 Dead-Battery Condition After I2C configuration concludes the TPS65982 checks VIN_3V3 to determine the cause of device boot. If the device is booting from a source other than VIN_3V3, the dead battery flow is followed to allow for the rest of the system to receive power. The state of the BUSPOWERZ pin is read to determine power path configuration for dead battery operation. After the power path is configured, the TPS65982 will continue through the boot process. Figure 65 depicts the full dead battery process. 68 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Device Functional Modes (continued) I2C Initiated Yes VIN_3V3 Valid No >2.4 V Check BUSPOWERZ ≤2.4 V VBUS Present No Yes Configure for VBUS Power Check > 0.8 V BUSPOWERZ ≤0.8 V Enable PP_HV as Enable PP_EXT as SINK SINK Load App Code Figure 65. Dead-Battery Condition Flow Diagram 8.4.5 Application Code The TPS65982 application code is stored in an external flash memory. The flash memory used for storing the TPS65982 application code may be shared with other devices in the system. The flash memory organization shown in Figure 66 supports the sharing of the flash as well as the TPS65982 using the flash without sharing. The flash is divided into two separate regions, the Low Region and the High Region. The size of this region is flexible and only depends on the size of the flash memory used. The two regions are used to allow updating the application code in the memory without over-writing the previous code. This ensures that the new updated code is valid before switching to the new code. For example, if a power loss occurred while writing new code, the original code is still in place and used at the next boot. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 69 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Device Functional Modes (continued) 0x000000 Region Pointer (RPTR) 0x000004 Low Header 4 kΩ 0x000FFC App Code Offset (AOFF) 0x001000 Region Pointer (RPTR) 0x001004 High Header 4 kΩ 0x001FFC App Code Offset (AOFF) 0x002000 Configuration ID RPTR+AOFF RPTR+AOFF+4 Configuration Status RPTR+AOFF+8 Configuration Size (CSIZE) RPTR+AOFF+12 Bin Size RPTR+AOFF+16 Bin CRC RPTR+AOFF+20 Configuration Data RPTR+AOFF+CSIZE Application Code 64 kΩ Figure 66. Flash Memory Organization There are two 4 kB header blocks starting at address 0x000000h. The Low Header 4 kB block is at address 0x000000h and the High Header 4 kB block is at 0x001000h. Each header contains a Region Pointer (RPTR) that holds the address of the physical location in memory where the low region application code resides. Each also contains an Application Code Offset (AOFF) that contains the physical offset inside the region where the TPS65982 application code resides. The TPS65982 firmware physical location in memory is RPTR + POFF. The first sections of the TPS65982 application code contain device configuration settings. This configuration determines the devices default behavior after power-up and can be customized using the TPS65982 Configuration Tool. These pointers may be valid or invalid. The Flash Read flow handles reading and determining whether a region is valid and contains good application code. 8.4.6 Flash Memory Read The TPS65982 first attempts to load application code from the low region of the attached flash memory. If any part of the read process yields invalid data, the TPS65982 will abort the low region read and attempt to read from the high region. If both regions contain invalid data the device carries out the Invalid Memory flow. Figure 67 shows the flash memory read flow. 70 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Device Functional Modes (continued) Enter Flash Read Read Low Header Read High Header Region Pointer Region Pointer and Application and Application Code Offset Code Offset Invalid Config Read Config Read Config Area Area Invalid Config Valid Config Invalid App Code Read App Code and Check CRC Read App Code and Check CRC Valid App Code Valid App Code Invalid App Code Reset Core and Run App Code Memory Invalid Figure 67. Flash Read Flow 8.4.7 Invalid Flash Memory If the flash memory read fails due to invalid data, the TPS65982 carries out the memory invalid flow and presents the SWD interface on the USB Type-C SBU pins. Memory Invalid Flow depicts the invalid memory process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 71 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Device Functional Modes (continued) Memory Invalid Enable VOUT_3V3 Release RESETZ VBUS Invalid Check VBUS VBUS Good Present Rp/Rp Rd/Rd Not Attached Check for Rd/Rd Rd/Rd Attached Present SWD Monitor VBUS Figure 68. Memory Invalid Flow 8.4.8 UART Download the secondary TPS65982 downloads the needed application code from the primary TPS65982 via UART. Figure 69 depicts the UART download process. Currently the TPS65982 firmware only supports 2 device (1 primary + 1 secondary) systems. 72 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Device Functional Modes (continued) SPI_MISO Low App Code Loaded Send “Request Data” Packet Receive “Request Data” Packet Receive “Send Data” Packet & Save Data Block map complete Yes No No Receive “Send CRC” packet Send “Send Data” packet Saved Data valid Send “Send CRC” Packet Yes Boot Fail Run App Code Secondary Primary Figure 69. UART Download Process 8.5 Programming 8.5.1 SPI Master Interface The TPS65982 loads flash memory during the Boot Code sequence. The SPI master electrical characteristics are defined in SPI Master Characteristics and timing characteristics are defined in Figure 8. The TPS65982 is designed to power the flash from LDO_3V3 in order to support dead-battery or no-battery conditions, and therefore pull-up resistors used for the flash memory must be tied to LDO_3V3. The flash memory IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 1 Mbyte (equivalent to 8 Mbit) to hold the standard application code outlined in Application Code. The SPI master of the TPS65982 supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as chip select (SPI_SSZ pin) becomes active. The chip select polarity is active-low. The clock phase is defined such that data (on the SPI_MISO and SPI_MOSI pins) is shifted out on the falling edge of the clock (SPI_CLK pin) and data is sampled on the rising edge of the clock. The clock polarity for chip select is defined such that when data is not being transferred the SPI_CLK pin is held (or idling) low. The minimum erasable sector size of the flash must be 4 kB. The W25Q80 flash memory IC is recommended. Refer to TPS65982 I2C Host Interface Specification for instructions for interacting with the attached flash memory over SPI using the host interface of the TPS65982. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 73 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Programming (continued) 8.5.2 I2C Slave Interface The TPS65982 has three I2C interface ports. I2C Port 1 is comprised of the I2C_SDA1, I2C_SCL1, and I2C_IRQ1Z pins. I2C Port 2 is comprised of the I2C_SDA2, I2C_SCL2, and I2C_IRQ2Z pins. These interfaces provide general status information about the TPS65982, as well as the ability to control the TPS65982 behavior, as well as providing information about connections detected at the USB-C receptacle and supporting communications to/from a connected device and/or cable supporting BMC USB-PD. The third port is comprised of the DEBUG_CTL1 and DEBUG_CTL2 pins. This third port is a firmware emulated I2C master. The pins are generic GPIO and do not contain any dedicated hardware for I2C such as detecting starts, stops, acks, or other protocol normally associated with I2C. This third port is always a master and has no interrupt. This port is intended to master another device that has simple control based on mode and multiplexer orientation. DEBUG_CTL1 is the serial clock and DEBUG_CTL2 is serial data. The first two ports can be a master or a slave, but the default behavior is to be a slave. Port 1 and Port 2 are interchangeable. Each port operates the same way and has the same access in and out of the core. An interrupt mask is set for each that determines what events are interrupted on that given port. 8.5.2.1 I2C Interface Description The TPS65982 support Standard and Fast mode I2C interface. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor. Data transfer may be initiated only when the bus is not busy. A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high. Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. Figure 70 shows the start and stop conditions of the transfer. Figure 71 shows the SDA and SCL signals for transferring a bit. Figure 72 shows a data transfer sequence with the ACK or NACK at the last clock pulse. SDA SCL S P Start Condition Stop Condition Figure 70. I2C Definition of Start and Stop Conditions 74 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Programming (continued) SDA SCL Data Line Change 2 Figure 71. I C Bit Transfer Data Output by Transmitter Nack Data Output by Receiver SCL From Master Ack 1 2 8 9 S Clock Pulse for Acknowledgement Start Condition Figure 72. I2C Acknowledgment 8.5.2.2 I2C Clock Stretching The TPS65982 features clock stretching for the I2C protocol. The TPS65982 slave I2C port may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master communicating with the slave must not finish the transmission of the current bit and must wait until the clock line actually goes high. When the slave is clock stretching, the clock line will remain low. The master must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs for standard 100 kbps I2C) before pulling the clock low again. Any clock pulse may be stretched but typically it is the interval before or after the acknowledgment bit. 8.5.2.3 I2C Address Setting The boot code sets the hardware configurable unique I2C address of the TPS65982 before the port is enabled to respond to I2C transactions. The unique I2C address is determined by a combination of the digital level on the DEBUG_CTL1/DEBUG_CTL2 pins (two bits) and the analog level set by the analog I2C_ADDR strap pin (three bits) as shown in Table 9. Table 9. I2C Default Unique Address Default I2C Unique Address Bit 7 Bit 6 Bit 5 Bit 4 0 1 DEBUG_CTL2 DEBUG_CTL1 Bit 3 Bit 2 Bit 1 I2C_ADDR_DECODE[2:0] Bit 0 R/W 2 Note 1: Any bit is maskable for each port independently providing firmware override of the I C address. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 75 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 8.5.2.4 Unique Address Interface The Unique Address Interface allows for complex interaction between an I2C master and a single TPS65982. The I2C Slave sub-address is used to receive or respond to Host Interface protocol commands. Figure 73 and Figure 74 show the write and read protocol for the I2C slave interface, and a key is included in Figure 75 to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated here in part. 1 7 1 1 8 1 8 1 8 1 S Unique Address Wr A Register Number A Byte Count = N A Data Byte 1 A 8 1 8 1 Data Byte 2 A Data Byte N A P Figure 73. I2C Unique Address Write Register Protocol 1 7 1 1 8 1 1 7 1 1 8 1 S Unique Address Wr A Register Number A Sr Unique Address Rd A Byte Count = N A 8 1 8 1 8 1 Data Byte 1 A Data Byte 2 A Data Byte N A P 1 2 Figure 74. I C Unique Address Read Register Protocol 1 7 1 1 8 1 1 S Slave Address Wr A Data Byte A P x x S Start Condition SR Repeated Start Condition Rd Read (bit value of 1) Wr Write (bit value of 0) x Field is required to have the value x A Acknowledge (this bit position may be 0 for an ACK or 1 for a NACK) P Stop Condition Master-to-Slave Slave-to-Master Continuation of protocol Figure 75. I2C Read/Write Protocol Key 8.5.2.5 I2C Pin Address Setting To enable the setting of multiple I2C addresses using a single TPS65982 pin, a resistance is placed externally on the I2C_ADDR pin. The internal ADC then decodes the address from this resistance value. Figure 76 shows the decoding. DEBUG_CTL1/2 are checked at the same time for the DC condition on this pin (high or low) for setting other bits of the address described previously. Note, DEBUG_CTL1/2 are GPIO and the address decoding is done by firmware in the digital core. 76 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 5 µA I2C_ADDR ADC R_I2C To Address Decoder DEBUG_CTL1 Tristate DEBUG_CTL2 Debug Data To Address Decoder Figure 76. I2C Address Decode Table 10 lists the external resistance needed to set bits [3:1] of the I2C Unique Address. For the master TPS65982, the pin is grounded. Table 10. I2C Address Resistance EXTERNAL RESISTANCE (1%) I2C UNIQUE ADDRESS [3:1] Master 0 0 0x00 Slave 1 93.1k 0x01 Slave 2 156k 0x02 Slave 3 220k 0x03 Slave 4 280k 0x04 Slave 5 340k 0x05 Slave 6 402k 0x06 Slave 7 Open 0x0F The TPS65982 DEVICE Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 77 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The typical applications of the TPS65982 include chargers, notebooks, tablets, ultrabooks, docking systems, dongles, and any other product supporting USB Type-C and/or USB-PD as a power source, power sink, data DFP, data UFP, or dual-role port (DRP). The typical applications outlined in the following sections detail a FullyFeatured USB Type-C & PD Charger Application and a Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort. 9.2 Typical Application 9.2.1 Fully-Featured USB Type-C & PD Charger Application The TPS65982 controls three separate power paths making it a flexible option for Type C PD charger applications. In addition, the TPS65982supports VCONN power for “e-marked” cables which are required for applications which require greater than 3 A of current on VBUS. Figure 77 below shows the high level block diagram of a Type C PD charger that is capable of supporting 5 V at 3 A, 12 V at 3 A, and 20 V at 5 A. The 5 V and 12 V outputs are supported by the TPS65982 internal FETs and the 20 V output uses the external FET path controlled by the TPS65982 NFET drive. This Type-C PD charger uses a receptacle for flexibility on cable choice. CC1/2 CC1/2 USB2.0 TPS65982 (Charger Application) SENSEP VBUS SENSEN VBUS HV_GATE1 Type C Receptacle HV_GATE2 Supply 20 V, 5 A PP_HV Supply 12 V, 3 A PP_5V0 Supply 5 V, 3.5 A PP_CABLE USB2.0 SBU1/2 VIN_3V3 Supply 3.3 V, 50 mA SSTX/RX Figure 77. Type-C and PD Charger Application 9.2.1.1 Design Requirements For a USB Type-C and PD Charger application, Table 11 shows the input voltage requirements and expected current capabilities. Table 11. Charging Application Design Parameters 78 DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT PP_5V0 Input Voltage and Current Capabilities 5 V, 3 A Sourcing to VBUS Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Typical Application (continued) Table 11. Charging Application Design Parameters (continued) DESIGN PARAMETER EXAMPLE VALUE DIRECTION OF CURRENT PP_CABLE Input Voltage and Current Capabilities 5 V, 500 mA Sourcing to VCONN PP_HV Input Voltage and Current Capabilities 12 V, 3 A Sourcing to VBUS EXT FET Path Input Voltage and Current Capabilities 20 V, 5 A Sourcing to VBUS VIN_3V3 Voltage and Current Requirements 2.85 - 3.45 V, 50 mA Internal TPS65982 Circuitry 9.2.1.1.1 External FET Path Components (PP_EXT & RSENSE) The external FET path allows for the maximum PD power profile (20 V at 5 A) and design considerations must be taken into account for choosing the appropriate components to optimize performance. Although a Type C PD charger will be providing power there could be a condition where a non-compliant device can be connected to the charger and force voltage back into the charger. To protect against this the external FET path detects reverse current in both directions of the current path. The TPS65982 uses “two back to back” NFETs to protect both sides of the system. Another design consideration is to rate the external NFETs above the Type C & PD specification maximum which is 20 V. In this specific design example, 30-V NFETs are used that have an average RDS,ON of 5 mΩ to reduce losses. The TPS65928 supports either a 10 mΩ or a 5 mΩ sense resistor on the external FET path. This RSENSE resistor is used for current limiting and is used for the reverse current protection of the power path. A 5 mΩ sense resistor is used in the design to minimize losses and I-R voltage drop. Recommended NFET Capabilities summarizes the recommended parameters for the external NFET used. The total voltage drop seen across RSENSE and the external NFET could be determined by Equation 5 below. It is important to consider the drop in the entire system and regulate accordingly to ensure that the output voltage is within its specification. Equation 6 will calculate the power lost through the external FET path. Table 12. Recommended NFET Capabilities Voltage Rating Current Rating RDS,ON 30 V (minimum) 10 A (peak current) < 10 mΩ Voltage Drop = DC Current (Rsense + NFET1 RDS,ON + NFET2 RDS,ON Power Loss = Voltage Drop X DC Current (5) (6) 9.2.1.2 Detailed Design Procedure 9.2.1.2.1 TPS65982 External Flash The external flash contains the TPS65982 application firmware and must be sized to 256kB minimum when the flash is not shared with another IC, but a recommended minimum of 1MB is needed when the flash memory of the TPS65982 is shared with another IC. This size will allow for pointers and two copies of the firmware image to reside on the flash along with the needed headers. The flash used is the W25Q80 which is a 3.3 V flash and is powered from the LDO_3V3 output from the TPS65982. 9.2.1.2.2 I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors I2C_ADDR, DEBUG_CTL1/2 pins must be tied to GND through a 0 Ω resistor tied to GND directly if needed to reduce solution size. Pull-ups on the I2C_CLK, I2C_SDA, and I2C_IRQ are used for de-bugging purposes. In most simple charger designs, I2C communication may not be needed. A 3.83 kΩ pull-up resistor from SWD_DATA to LDO_3V3 and a 100 kΩ pull-down resistor from SWD_CLK to GND must also be used for debugging purposes. 9.2.1.2.3 Oscillator (R_OSC) Resistor A 15-kΩ 0.1% resistor is needed for key PD BMC communication timing and the USB2.0 endpoint. A 1% 15-kΩ resistor is not recommended to be used because the internal oscillators will not be controlled well enough by this loose resistor tolerance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 79 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 9.2.1.2.4 VBUS Capacitor & Ferrite Bead A 1uF ceramic capacitor is placed close to the TPS65982 VBUS pins. A 6 A ferrite bead is used in this design along with four high frequency noise 10 nF capacitors placed close to the Type-C connector to minimize noise. 9.2.1.2.5 Soft Start (SS) Capacitor The recommended 0.22 µF is placed on the TPS65982 SS pin. 9.2.1.2.6 USB Top (C_USB_T), USB Bottom (C_USB_B), & Sideband-Use (SBU) Connections Although the charger is configured to be only a power source, SBU1/2, USB Top & Bottom must be routed to the Type C connector. This allows for de-bugging or for any specific alternate modes for power to be configured if needed. ESD protection is used in the design on all of these nets as good design practice. 9.2.1.2.7 Port Power Switch (PP_EXT, PP_HV, PP_5V0, and PP_CABLE) Capacitors The design assumes that a DC/DC converter is connected to the paths where there is significant output capacitance on the DC/DCs to provide the additional capacitance for load steps. It is recommended to for the DC/DC converters for to be capable of supporting current spikes which can occur with certain PD configurations. The PP_EXT path is capable of supporting up to 5 A which will require additional capacitance to support system loading by the device connected to the charger. A ceramic 10 µF (X7R/X5R) capacitor is used in this design. This capacitor must at least have a 25 V rating and it is recommended to have 30 V or greater rated capacitor. The PP_HV path is capable of supporting up to 3 A which will require additional capacitance to support system loading by the device connected to the charger. A ceramic 10 µF (X7R/X5R) capacitor coupled with a 0.1 µF high frequency capacitor is placed close to the TPS65982. The PP_5V0 and PP_CABLE supplies are connected together therefore a ceramic 22-µF (X7R/X5R) capacitor coupled with a 0.1-µF high-frequency capacitor is placed close to the TPS65982. The PP_5V0 path can support 3 A and the PP_CABLE path supports 600 mA for active Type C PD cables. The design assumes that a DC/DC converter is connected to the paths where there is significant output capacitance on the DC/DCs to provide the additional capacitance. It is recommended to for the DC/DC converters to be capable of supporting current spikes which can occur with certain PD configurations. 9.2.1.2.8 Cable Connection (CCn) Capacitors and RPD_Gn Connections This charger application is designed to only be a source of power and does not support “Dead Battery.” RPD_G1 and RPD_G2 must be tied to GND and not connected to the CC1 and CC2 respectively. For CC1 and CC2 lines, they require a 220 pF capacitor to GND. 9.2.1.2.9 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VOUT_3V3, VIN_3V3, & VDDIO For all capacitances it is important to factor in DC voltage de-rating of ceramic capacitors. Generally the effective capacitance is halved with voltage applied. VIN_3V3 is connected to VDDIO which ensures that the I/Os of the TPS65982’s will be configured to 3.3 V. A 1 µF capacitor is used and is shared between VDDIO and VIN_3V3. LDO_1V8D, LDO_1V8A, and LDO_BMC each have their own 1 µF capacitor. In this design LDO_3V3 powers the TPS65982’s external flash and various pull ups. A 10 µF capacitor was chosen to support these additional connections. VOUT_3V3 is not used in this design and capacitor is not needed. 80 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 9.2.1.3 Application Curves 1000 PP_EXT Power Loss (mW) 900 800 700 600 500 400 300 200 100 0 3 3.2 3.4 3.6 3.8 4 4.2 DC Current (A) 4.4 4.6 4.8 5 D012 Figure 78. PP_EXT Power Loss 9.2.2 Dual-Port Notebook Application Supporting USB PD Charging and DisplayPort The TPS65982 features support for DisplayPort over Type-C alternate mode and manages sinking and sourcing of power in Power Delivery. The block diagram, shown in Figure 79, depicts a two port system that is capable of charging from either Type C port over PD, DisplayPort Alternate Mode, and delivering Battery Power to a buspowered device. With the DisplayPort support, the TPS65982 controls an external SuperSpeed multiplexer, HD3SS460, to route the appropriate super-speed signals to the Type-C connector. The HD3SS460 is controlled through GPIOs configured by the TPS65982 application code and the HD3SS460 is designed to meet the timing requirements defined by the DisplayPort over Type-C specification. A system controller is also necessary to handle some of the dynamic aspects of Power Delivery such as reducing power capabilities when system battery power is low. Audio accessory device is supported by the design as well. Although USB_RP_P and USB_RP_N are not shown in the block diagram, they must be connected to the system-side IC that will receive and send USB2.0 high-speed data through the integrated multiplexer of the TPS65982. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 81 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com DC Barrel Jack CC1/2 SENSEP CC1/2 SENSEN VBUS HV_GATE2 VBUS HV_GATE1 PFET Control Type C Receptacle PP_HV Battery Voltage Supply 5 V, 3.5 A Supply 3.3 V, 50 mA AUX_N/P VIN EN POL AMSEL GPIO_3 I2C GPIO_0 SSTX/RX USB2.0 DEBUG_2 SBU1/2 PP_5V0 TPS65982 PP_CABLE USB2.0 (Notebook Application) SBU1/2 VIN_3V3 DC Barrel Jack Sense BAT BQ Battery Battery Voltage + Charger I2C HD3SS460 (SS MUX) CC1/2 CC1/2 DP Source USB3 Source SENSEP VBUS SENSEN VBUS HV_GATE2 Type C Receptacle HV_GATE1 ML0 – ML3 SSTX/RX USB3 SSTX/RX PP_HV System Battery Voltage Controller Supply 5 V, 3.5 A Supply 3.3 V, 50 mA AUX_N/P EN POL AMSEL GPIO_3 I2C GPIO_0 SSTX/RX DEBUG_2 SBU1/2 PP_5V0 TPS65982 PP_CABLE USB2.0 (Notebook Application) SBU1/2 VIN_3V3 USB2.0 I2C Master HD3SS460 (SS MUX) ML0 – ML3 SSTX/RX USB3 SSTX/RX DP Source USB3 Source Figure 79. Dual-Port Notebook Application 9.2.2.1 Design Requirements For a dual-port notebook application, Table 13 Design Parameters shows the input voltage requirements and expected current capabilities. 82 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Table 13. Dual-Port Notebook Application Design Parameters DESIGN PARAMETERS EXAMPLE VALUE DIRECTION OF CURRENT PP_5V0 Input Voltage and Current Capabilities 5 V, 3 A Sourcing to VBUS PP_CABLE Input Voltage and Current Capabilities 5 V, 500 mA Sourcing to VCONN PP_HV Input Voltage and Current Capabilities 10-13 V, 3 A Sourcing to VBUS (directly from Battery) EXT FET Path Voltage and Current Capabilities 20 V, 3 A Sourcing to VBUS or Sinking from VBUS VIN_3V3 Voltage and Current Requirements 2.85-3.45 V, 50 mA Internal TPS65982 Circuitry 9.2.2.1.1 Source Power Delivery Profiles for Type-C Ports Table 14 shows the summary of the source PD profiles that are supported for this specific design. PDO 1 & 2 will always be present in the system and will be able to be negotiated without any other system interaction. When DC barrel Jack voltage is sensed PDO 3 will become available for power delivery negotiation. The external sense resistor, RSENSE, is configured to only measure the current being sourced by the system. When operating as a sink of power the input current cannot be measured in this configuration. Table 14. Source USB PD Profiles PDO1 PDO2 PDO3 POD TYPE Fixed Supply Battery Power Fixed Supply 20 V Voltage 5V 10 V - 13 V Current/Power 3A 30 W 3A Externally Dependent No No Yes 9.2.2.1.2 Sink Power Delivery Profile for Type-C Ports The two Type-C ports used in this design support Power Delivery and enable charging over a Type-C connection. Table 15 shows the sink profile supported by both of the ports. The TPS65982’s reverse current blocking will allow both of the Type-C ports to negotiate a power contract, but it is good system practice for the System Controller to change the sink profile when a power contract is established. When the DC barrel jack is connected the TPS65982 will re-negotiate the a PD contract to no longer charge of Type C and have the DC Barrel Jack take precedence when connected. Table 15. Sink USB PD Profile RDO RDO Type Fixed Supply Voltage 20 V Current 3A Externally Dependent Yes 9.2.2.2 Detailed Design Procedure The same passive components used in the Fully-Featured USB Type-C & PD Charger Application are also applicable in this design to support all of the features of the TPS65982. Additional design information is provided below to explain the connections between the TPS65982 and the system controller and the TPS65982 and the HD3SS460 SuperSpeed multiplexer. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 83 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 9.2.2.2.1 TPS65982 & System Controller Interaction The TPS65982 features two I2C slave ports that can be used simultaneously, where the system controller has the ability to write to either of the I2C slave ports. Each I2C port has an I2C interrupt that will inform the system controller that a change has happened in the system. This allows the system controller to dynamically budget power and reconfigures a port’s capabilities dependent on current state of the system. For example, if a battery power contract is established and the system is running low on battery power the system controller could notify the TPS65982 to re-negotiate a power contract. The system controller is also used for updating the TPS6982 firmware over I2C, where the Operating System will be able to load the Firmware update to the system controller and then the system controller would be able to update firmware update though I2C. 9.2.2.2.2 HD3SS460 Control & DisplayPort Configuration The two Type-C ports in this design support DisplayPort simultaneously on both ports. When a system is not capable of supporting video on both ports the system controller will disable DisplayPort on the second Type-C port through I2C. Table 16 below shows the DisplayPort configurations supported in the system. Table 17 shows the summary of the TPS65982 GPIO signals control for the HD3SS460. Although the HD3SS460 is able to multiplex the required AUX_N/P signals to the SBU_1/2 pins, they are connected through the TPS65982 for additional support of custom alternate mode configurations. Table 16. Supported DisplayPort Configurations DisplayPort Role Display Port Pin Assignment DisplayPort Lanes Configuration 1 DFP_D Pin Assignment C 4 Lane Configuration 2 DFP_D Pin Assignment D 2 Lane & USB 3.1 Configuration 3 DFP_D Pin Assignment E 4 Lane (Dongle Support) Table 17. TPS65982 and HD3SS460 GPIO Control TPS65982 GPIO HD3SS460 Control Pin Description GPIO_0 AMSEL Alternate Mode Selection (DP/USB3) GPIO_3 EN Super Speed Mux Enable DEBUG2 POL Type-C Cable 9.2.2.2.3 9.3.2.3 DC Barrel Jack & Type-C PD Charging The system is design to either charge over Type-C or from the DC barrel jack. The TPS65982 detects that the DC barrel jack is connected to GPIOn. In the simplest form, a voltage divider could be set to the GPIO I/O level when the DC Barrel jack voltage is present, as shown in Figure 80. A comparator circuit is recommend and used in this design for design robustness, as shown in Figure 81. 20 V DC Barrel Jack 100 k 1.81 V Barrel Jack Detect/ PFET Enable 10 k Figure 80. DC Barrel Jack Voltage Divider 84 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 DC Barrel Jack Voltage 1.8 V + 100 kΩ Barrel Jack Detect/ PFET Enable 10 kΩ Figure 81. Barrel Jack Detect Comparator This detect signal is used to determine if the barrel jack is present to support the 20 V PD power contracts and to hand-off charging from barrel jack to Type-C or Type-C to barrel jack. When the DC barrel jack is detected the TPS6982 at each Type-C port will not request 20 V for charging and the system will be able to support a 20 V source power contract to another device. When the DC Barrel Jack is disconnected the TPS65982 will exit any 20 V source power contract and re-negotiate a power contract. When the DC Barrel Jack is connected the TPS65982 will send updated source capabilities and re-negotiate a power contract if needed. The PFET enable will be controlled by the DC barrel jack detect comparator depicted in Figure 81. This will allow the system to power up from dead battery through the barrel jack as well as the Type-C ports. Figure 83 shows the flow between changing from DC barrel jack charging and USB-PD charging. The example uses back-to-back PFETs for disabling and enabling the power path for the DC Barrel Jack. It is important to use PFETs that are rated above the specified parameters to ensure robustness of the system. The DC Barrel Jack voltage in this design is assumed to be 20 V at 5 A, so the PFETs are recommended to be rated at a minimum of 30 V and 10 A of current. The TPS65982 in this design also provides the GPIO control for the PFET gate drive that passes the DC Barrel Jack Voltage to the system. Figure 83 shows the flow between changing from DC Barrel Jack charging and Type-C PD charging. 9.2.2.2.4 Primary TPS65982 Flash Master and Secondary Port A single flash can be used for two TPS65982’s in a system where the primary TPS65982 is connected to the flash and the seoncdary TPS65982 is connected to the primary through UART. UART data is used to pass the firmware from the primary TPS6982 to the secondary TPS65982 in the system. Figure 82 shows a simplified block diagram of how a primary and secondary TPS65982 are connected using a single flash. The primary TPS65982 must have its I2C_ADDR pin tied to GND with a 0Ω to denote it as the primary TPS65982. TPS65982 (Primary) UART TPS65982 (Secondary) SPI SPI Flash Figure 82. Primary and Secondary TPS65982 Sharing a Single Flash Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 85 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 9.2.2.2.5 TPS65982 Dead Battery Support Primary and Secondary Port The TP65982 supports dead battery functionality to be able to power up from the Type-C port. This design supports dead battery using the PP_EXT path, where RPD_G1/2 and CC1/2 are connected respectively, and BUSPOWERZ is connected to GND to path 5 V VBUS into the system through the PP_EXT path. The TPS65982 will soft-start the PP_EXT (or PP_HV) path in order to comply with USB2.0 inrush current requirements. In order to enable PD functionality the TPS65982 must boot the application firmware from the flash. For the primary TPS65982, once VBUS is detected at 5 V it will automatically start to load the application firmware from the flash. The TPS65982 will then be able communicate over PD and establish a power contract at the required 20 V. Figure 84 shows the boot up sequence of the primary TPS65982. When the TPS65982 that is not connected to the flash is connected in dead battery it will pass the 5 V from VBUS in to the battery charger where the battery would be able to generate the needed System 3.3 V rail to both of the TPS65982s. Once the primary TPS65982 has a valid 3.3 V supply (VBUS = 0 V on Primary TPS65982) it will load the application firmware from the flash and pass it to the secondary TPS65982 that is connected. Once the secondary TPS65982 has loaded the application firmware over UART it will be able to negotiate a 20 V power contract. Figure 85 shows the dead battery sequence of the secondary TPS65982. 9.2.2.2.6 De-bugging Methods The TPS65982 has methods of de-bugging a Type-C and PD system. In addition to the resistances recommended in I2C (I2C), Debug Control (DEBUG_CTL), and Single-Wire De-bugger (SWD) Resistors , additional series resistors are used for de-bugging. The two I2C channels allow a designer to check the system state through the Host Interface Specification. By attaching 0-Ω series resistors between the I2C master and the TPS65982 and additionally adding 0-Ω series resistors between the TPS65982 and test points, a multi-master scenario can be avoided. This allows breaking the connection between the I2C channels and the system to allow I2C access to the TPS65982 from an external tool. A header is used to allow for connections without soldering; however, SMT test pads can be used to provide a place to solder “blue-wires” for testing. Exposing the SWD_DAT and SWD_CLK pins will allow for more advanced de-bugging if needed. A header or SMT test point is also used for the SWD_DATA and SWD_CLK pins. 9.2.2.3 Application Curves Barrel Jack Charging Barrel Jack Inserted Barrel Jack Charging Barrel Jack Removed 20 V PD Power Contract Type-C Cable Connected Barrel Jack Inserted 20 V DC Barrel Jack Attached DC Barrel Jack Detect/PFET Enable 5V Type-C Charging Enter 20 V Type-C PD Contract Exit 20 V Type-C PD Contract 0V VBUS PD Charging Figure 83. DC Barrel Jack & Type-C PD Charging Hand-Off Application FW Load Active TPS65982 Code Load Application Boot Flash FW Load Start PD Comm. Enabled Figure 84. Primary TPS65982 Dead Battery Sequence 86 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Type-C Cable Connected 20 V PD Power Contract 20 V 20 V 5V Secondary VBUS 0V 5V Secondary PP_EXT 0V 3.3 V BQ Charger 3.3 V Auxiliary (VIN_3V 3) 0V Primary Application FW Load SPI LOAD Secondary Application FW Load UART LOAD Application Boot Primary Active TPS65982 Code Boot Secondary Active TPS65982 Code Application Secondary TPS65982 Loads App. FW (UART) Primary Secondary PD TPS65982 Loads Communication App. FW (SPI) Enabled Figure 85. Secondary TPS65982 Dead Battery Sequence Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 87 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 10 Power Supply Recommendations 10.1 3.3 V Power 10.1.1 1VIN_3V3 Input Switch The VIN_3V3 input is the main supply to the TPS65982. The VIN_3V3 switch (S1 in Figure 49) is a unidirectional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3 to VIN_3V3. This switch is on when 3.3 V is available. See Table 18 for the recommended external capacitance on the VIN_3V3 pin. 10.1.2 VOUT_3V3 Output Switch The VOUT_3V3 output switch (S2 in Figure 49) enables a low-current auxiliary supply to an external element. This switch is controlled by and is off by default. The VOUT_3V3 output has a supervisory circuit that drives the RESETZ output as a POR signal to external elements. RESETZ is also asserted by the MRESET pin or a host controller. See RESETZ and MRESET for more details on RESETZ. See Table 18 for the recommended external capacitance on the VOUT_3V3 pin. 10.1.3 VBUS 3.3 V LDO The 3.3 V LDO from VBUS steps down voltage from VBUS to LDO_3V3. This allows the TPS65982 to be powered from VBUS when VIN_3V3 is not available. This LDO steps down any recommended voltage on the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65982 will operate without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin may increase temperature enough to trigger thermal shutdown. The VBUS 3.3 V LDO blocks reverse current from LDO_3V3 back to VBUS allowing VBUS to be unpowered when LDO_3V3 is driven from another source. See Table 18 for the recommended external capacitance on the VBUS and LDO_3V3 pins. 10.2 1.8 V Core Power Internal circuitry is powered from 1.8 V. There are two LDOs that step the voltage down from LDO_3V3 to 1.8 V. One LDO powers the internal digital circuits. The other LDO powers internal low voltage analog circuits. 10.2.1 1.8 V Digital LDO The 1.8 V Digital LDO provides power to all internal low voltage digital circuits. This includes the digital core, memory, and other digital circuits. See Table 18 for the recommended external capacitance on the LDO_1V8D pin. 10.2.2 1.8 V Analog LDO The 1.8 V Analog LDO provides power to all internal low voltage analog circuits. See Table 18 for the recommended external capacitance on the LDO_1V8A pin. 10.3 VDDIO The VDDIO pin provides a secondary input allowing some I/Os to be powered by a source other than LDO_3V3. The default state is power from LDO_3V3. The memory stored in the flash will configure the I/O’s to use LDO_3V3 or VDDIO as a source and application code will automatically scale the input and output voltage thresholds of the I/O buffer accordingly. See I/O Buffers for more information on the I/O buffer circuitry. See Table 18 for the recommended external capacitance on the VDDIO pin. 10.3.1 Recommended Supply Load Capacitance Table 18 lists the recommended board capacitances for the various supplies. The typical capacitance is the nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum capacitance allowing for tolerances and voltage de-rating ensuring proper operation. 88 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 VDDIO (continued) Table 18. Recommended Supply Load Capacitance CAPACITANCE PARAMETER DESCRIPTION VOLTAGE RATING MIN (ABS MIN) TYP (TYP PLACED) MAX (ABS MAX) CVIN_3V3 Capacitance on VIN_3V3 6.3 V 5 µF 10 μF CLDO_3V3 Capacitance on LDO_3V3 6.3 V 5 µF 10 µF 25 µF CVOUT_3V3 Capacitance on VOUT_3V3 6.3 V 0.1 μF 1 μF 2.5 μF CLDO_1V8D Capacitance on LDO_1V8D 4V 500 nF 2.2 µF 12 µF CLDO_1V8A Capacitance on LDO_1V8A 4V 500 nF 2.2 µF 12 µF CLDO_BMC Capacitance on LDO_BMC 4V 1 µF 2.2 µF 4 µF CVDDIO Capacitance on VDDIO. When shorted to LDO_3V3, the CLDO_3V3 capacitance may be shared. 6.3 V 0.1 µF 1 µF CVBUS Capacitance on VBUS 1 25 V 0.5 µF 1 µF CPP_5V0 Capacitance on PP_5V0 10 V 2.5 µF 4.7 µF CPP_HV Capacitance on PP_HV (Source to VBUS) 25 V 2.5 µF 4.7 µF Capacitance on PP_HV (Sink from VBUS) 25 V CPP_CABLE Capacitance on PP_CABLE. When shorted to PP_5V0, the CPP_5V0 capacitance may be shared. 10 V 2.5 µF 4.7 µF CPP_HVEXT Capacitance on external high voltage source to VBUS 25 V 2.5 µF 4.7 µF Capacitance on external high voltage sink from VBUS 25 V 47 µF Capacitance on soft start pin 6.3 V 220 nF CSS 47 µF 12 µF 120 µF 120 µF 10.3.2 Schottky for Current Surge Protection To prevent the possibility of large ground currents into the TPS65982 during sudden disconnects due to inductive effects in a cable, it is recommended that a Schottky be placed from VBUS to GND as shown in Figure 86. The NSR20F30NXT5G is recommended. PP_HV Fast current limit HV_GATE2 PP_HV Gate Control and Current Limit HV_GATE1 SENSEN SENSEP PP_EXT HV Gate Control and Sense PP_5V0 Gate Control and Current Limit PP_5V0 VBUS Fast current limit AGND Figure 86. Schottky on VBUS for Current Surge Protection Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 89 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 11 Layout 11.1 Layout Guidelines Proper routing and placement will maintain signal integrity for high-speed signals and improve the thermal dissipation from the TPS65982 power path. The combination of power and high-speed data signals are easily routed if the following guidelines are followed. It is a best practice to consult with a printed circuit board (PCB) manufacturer to verify manufacturing capabilities. 11.1.1 TPS65982 Recommended Footprints 11.1.1.1 Standard TPS65982 Footprint (Circular Pads) Figure 87 shows the TPS65982 footprint using a 0.25mm pad diameter. This footprint is applicable to boards that will be using an HDI PCB process that uses smaller vias to fan-out into the inner layers of the PCB. This footprint requires via fill and tenting and is recommended for size-constrained applications. The circular footprint allows for easy fan-out into other layers of the PCB and better thermal dissipation into the GND planes. Figure 88 shows the recommended via sizing for use under the balls. The size is 5mil hole and 10mil diameter. This via size will allow for approximately 1.5A current rating at 3 mΩ of DC resistance with 1.6nH of inductance. It is recommended to verify these numbers with board manufacturing processes used in fabrication of the PCB. This footprint is available for download on the TPS65982 product folder on the TPS65982 product folder. 90 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Guidelines (continued) Figure 87. Top View Standard TPS65982 Footprint (Circular Pads) Figure 88. Under Ball Recommended Via Size Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 91 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Guidelines (continued) 11.1.2 11.1.2 Alternate TPS65982 Footprint (Oval Pads) Figure 89 shows the TPS65982 footprint using oval-shaped pads in specific locations. This allows the PCB designer to route the inner perimeter balls through the top layer. The balls around the perimeter have their pads in an oval shape with the exception of the corner balls. Figure 90 shows the sizing for the oval pads, 0.25 mm by 0.17 mm. All of the other non-oval shaped pads will have a 0.25 mm diameter. This footprint is recommended for MDI (Medium Density) PCB designs that are generally less expensive to build. The void under the TPS65982 allows for vias to route the inner signals and connect to the GND and power planes. Figure 91 shows the recommended minimum via size (8mil hole and 16 mil diameter). The recommended 8mil vias will be rated for approximately 1.8 A of DC current and 1.5 mΩ of resistance with 1.3 nH of inductance. Some board manufactures may offer 6mil hole and 12 mil diameter vias with a mechanical drill. This footprint is available for download on the TPS65982 product folder. Figure 89. Top View Alternate TPS65982 Footprint (Oval Pads) 92 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Guidelines (continued) Figure 90. Oval Pad Sizing Figure 91. Recommended Minimum Via Sizing 11.2 Layout Example 11.2.1 Top TPS65982 Placement and Bottom Component Placement & Layout When the TPS65982 is placed on top and its components on bottom the solution size will be at its smallest. For systems that do not use the optional external FET path the solution size will average less than 64 mm2 (8 mm × 8 mm). Systems that implement the optional external FET path will average a solution size of less than 100 mm2 (10 mm × 10 mm). These averages will vary with component selection (NFETs, Passives, etc.). Selection of the oval pad TPS65982 footprint or standard TPS65982 footprint will allow for similar results. 11.2.2 Oval Pad Footprint Layout & Placement The oval pad footprint layout is generally more difficult to route than the standard footprint due to the top layer fan-out and void via placement needed; however, when the footprint with oval pads is used, “Via on Pads,” laserdrilled vias, and HDI board processes are not required. Therefore, a footprint with oval pads is ideal for costoptimized applications and will be used for the following the layout example. This layout example follows the charger application example (see Typical Application) and includes all necessary passive components needed for this application. This design uses both the internal and optional external FET paths for sourcing and sinking power respectively. Follow the differential impedances for High Speed signals defined by their specifications (DisplayPort - AUXN/P & USB2.0). All I/O will be fanned out to provide an example for routing out all pins, not all designs will utilize all of the I/O on the TPS65982. 11.2.3 Component Placement Placement of components on the top and bottom layers is used for this example to minimize solution size. The TPS65982 is placed on the top layer of the board and the majority of its components are placed on the bottom layer. When placing the components on the bottom layer, it is recommended that they are placed directly under the TPS65982 in a manner where the pads of the components are not directly under the void on the top layer. Figure 92 and Figure 93 show the placement in 2-D. Figure 94 and Figure 95 show the placement in 3-D. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 93 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Example (continued) Figure 92. Example Layout (Top View in 2-D) 94 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Example (continued) Figure 93. Example Layout (Bottom View in 2-D) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 95 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Example (continued) Figure 94. Example Layout (Top View in 3-D) 96 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Example (continued) Figure 95. Example Layout (Bottom View in 3-D) 11.2.4 Designs Rules and Guidance When starting to route nets it is best to start with 4 mil clearance spacing. The designer may have to adjust the 4mil clearance to 3.5 mil when fanning out the top layer routes. With the routing of the top layer having a tight clearance, it is recommended to have the layout grid snapped to 1 mil. For certain routes on the layout done in this guide, the grid snap was set to 0.1 mil. For component spacing this design used 20 mil clearance between components. The silk screen around certain passive components may be deleted to allow for closer placement of components. 11.2.5 Routing PP_HV, PP_EXT, PP_5V0, & VBUS On the top layer, create pours for PP_HV, PP_5V0 and VBUS to extend area to place 8 mil hole and 16 mil diameter vias to connect to the bottom layer. A minimum of 4 vias is needed to connect between the top and bottom layer. For the bottom layer, place pours that will connect the PP_HV, PP_5V0, and VBUS capacitors to their respective vias. The external FETS must also be connected through pours and place vias for the external FET gates. For 5 A systems, special consideration must be taken for ensuring enough copper is used in order to handle the higher current. For 0.5 oz copper top or bottom pours with 0.5-oz plating will require approximately a 120-mil pour width for 5-A support. When routing the 5 A through a 0.5 oz internal layer, more than 200 mil will be required to carry the current. Figure 96 and Figure 97 show the pours used in this example. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 97 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Example (continued) Figure 96. Top Polygonal Pours 98 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Example (continued) Figure 97. Bottom Polygonal Pours 11.2.6 Routing Top and Bottom Passive Components The next step is to route the connections to the passive components on the top and bottom layers. For the top layer only CC1 and CC2 capacitors will be placed on top. Routing the CC1 and CC2 lines with a 8 mil trace will facilitate the needed current for supporting powered Type C cables through VCONN. For more information on VCONN please refer to the Type C specification. Figure 98 shows how to route to the CC1 and CC2 to their respective capacitors. For capacitor GND pin use a 10 mil trace if possible. This particular system support Dead Battery, which has RPD_G1/2 connected to CC1/2. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 99 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Example (continued) Figure 98. CC1 and CC2 Capacitor Routing The top layer pads will have to be connected the bottom placed component through Vias (8 mil hole and 16 mil diameter recommended). For the VIN_3V3, VDDIO, LDO_3V3, LDO_1V8A, LDO1V8D, LDO_BMC, and VOUT_3V3 use 6mil traces to route. For PP_CABLE route using an 8 mil trace and for all other routes 4 mil traces may be used. To allow for additional space for routing, stagger the component vias to leave room for routing other signal nets. Figure 99 and Figure 100 show the top and bottom routing. Table 19 provides a summary of the trace widths. 100 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Layout Example (continued) Figure 99. Top Layer Component Routing Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 101 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Layout Example (continued) Figure 100. Bottom Layer Component Routing Table 19. Routing Trace Widths 102 ROUTE WIDTH (mil) CC1, CC2, PP_CABLE 8 LDO_3V3, LDO_1V8A, LDO_1V8D, LDO_BMC, VIN_3V3, VOUT_3V3, VDDIO, HV_GATE1, HV_GATE2 6 Component GND 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 11.2.7 Void Via Placement The void under the TPS65982 is used to via out I/O and for thermal relief vias. A minimum of 6 vias must be used for thermal dissipation to the GND planes. The thermal relief vias must be placed on the right side of the device by the power path. Figure 101 shows the recommended placement of the vias. Note the areas under the void where vias are not placed. This is done in order to allow the external FET gate drive and sense pins to route under the TPS65982 through an inner layer. Figure 102 shows the top layer GND pour to connect the vias and GND balls together. Figure 101. Void Via Placement Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 103 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Figure 102. Top Layer GND Pour 11.2.8 Top Layer Routing Once the components are routed, the rest of the area can be used to route all of the additional I/O. After all nets have been routed place a polygonal pour under to connect the TPS65982 GND pins to the GND vias. Refer to Figure 103 for the final top routing and GND pour. 104 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Figure 103. Final Routing and GND Pour (Top Layer) 11.2.9 Inner Signal Layer Routing The inner signal layer is used to route the I/O from the internal balls of the TPS65982 and the external FET control and sensing. Figure 104 shows how to route the internal layer. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 105 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com Figure 104. Final Routing (Inner Signal Layer) 11.2.10 Bottom Layer Routing The bottom layer has most of the components placed and routed already. Place a polygon pour to connect all of the GND nets and vias on the bottom layer, refer to Figure 105. 106 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 TPS65982 www.ti.com SLVSD02A – MARCH 2015 – REVISED JUNE 2015 Figure 105. Final Routing (Bottom Layer) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 107 TPS65982 SLVSD02A – MARCH 2015 – REVISED JUNE 2015 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support TPS65982 Tools & Software - http://www.ti.com/product/TPS65982/toolssoftware 12.2 Documentation Support 12.2.1 Related Documentation • USB Power Delivery Specification Revision 2.0, V1.1 (May 7th, 2015) • USB Type-C Specification Release 1.1 (April 3rd, 2015) • USB Battery Charging Specification Revision 1.2 (December 7th, 2010) • TPS65982 I2C Host Interface Specification • W25Q80 Datasheet - http://www.elinux.org/images/f/f5/Winbond-w25q32.pdf • NSR20F30NXT5G Datasheet - http://www.onsemi.com/pub_link/Collateral/NSR20F30-D.PDF 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. Thunderbolt is a trademark of Intel. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 108 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: TPS65982 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) TPS65982ABZQZR ACTIVE Package Type Package Pins Package Drawing Qty BGA MICROSTAR JUNIOR ZQZ 96 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -10 to 85 TPS65982 AB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65982ABZQZR BGA MI CROSTA R JUNI OR ZQZ 96 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 TPS65982ABZQZR BGA MI CROSTA R JUNI OR ZQZ 96 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65982ABZQZR BGA MICROSTAR JUNIOR ZQZ 96 2500 336.6 336.6 31.8 TPS65982ABZQZR BGA MICROSTAR JUNIOR ZQZ 96 2500 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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