Product Folder Sample & Buy Technical Documents Support & Community Tools & Software LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 AC-DC Quasi-Resonant Current Mode PWM Controller FEATURES APPLICATIONS • • • • • 1 • • • • • • • • • • Critical Conduction Mode Peak Current Mode Control Mode Skip Cycle Mode for Low Standby Power Hiccup Mode for Continuous Overload Protection Cycle-by-Cycle Over-Current Protection Maintains Accuracy over the Universal AC Line Line Current Feed Forward OVP Protection by Sensing the Aux Winding Integrated 0.7 A Peak Gate Driver Direct Opto-Coupler Interface Leading Edge Blanking of Current Sense Signal Maximum Frequency Clamp 130 kHz Programmable Soft Start Thermal Shutdown 8-Pin MSOP Package • • • Universal Input AC-DC Notebook Adapters 10 W to 65 W High Efficiency Housekeeping and Auxiliary Power Battery Chargers Consumer Electronics (DVD Players, Set-Top Boxes, DTV, Gaming, Printers, etc) DESCRIPTION The LM5023 is a Quasi-Resonant Pulse Width Modulated (PWM) controller which contains all of the features needed to implement a highly efficient offline power supply. The LM5023 uses the transformer auxiliary winding for demagnetization detection to ensure Critical Conduction Mode (CCM) operation. The LM5023 features a hiccup mode for over current protection with an auto restart to reduce the stress on the power components during an overload. A skip cycle mode which reduces power consumption at light loads for energy conservation applications (ENERGY STAR®, CEPCP, etc.). The LM5023 also uses the transformer auxiliary winding for output overvoltage (OVP) protection, if an OVP fault is detected the LM5023 latches off the controller. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com SIMPLIFIED SCHEMATIC Vout +19V 90-264 VAC High Voltage Start-up Depletion Mode FET QR OUT VCC CS LM5023 Output voltage regulation VSD SS COMP GND 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 PIN FUNCTIONS NAME NO. TYPE DESCRIPTION COMP 4 I Control input for the Pulse Width Modulator and Skip cycle comparators. COMP pull-up is provided by an internal 42 K resistor which may be used to bias an opto-coupler transistor. CS 5 I Current sense input for current mode control and over-current protection. Current limiting is accomplished using a dedicated current sense comparator. If the CS comparator input exceeds 0.5 V, the OUT pin switches low for cycle-by-cycle current limit. CS is held low for 90 ns after OUT switches high to blank the leading edge current spike. GND 6 G Ground connection return for internal circuits. OUT 7 O High current output to the external MOSFET gate input with source/sink current capability of 0.3 A and 0.7 A respectively. QR 1 I The auxiliary FLYBACK winding of the power transformer is monitored to detect the Quasi-Resonant operation. The peak auxiliary voltage is sensed to detect an output overvoltage (OVP) fault and shuts down the controller. SS 3 O An external capacitor and an internal 22 µA current source sets the softstart ramp. VSD 2 O Connect this pin to the Gate of the external start-up circuit FET; it will disable the start-up FET after VCC is valid. VCC 8 P VCC provides bias to controller and gate drive sections of the LM5023. An external capacitor must be connected from this pin to ground. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VALUE MIN MAX – 4 UNIT IQR Negative Injection Current When the QR Pin is Being Driven Below Ground VSD Maximum Voltage IVSD VSD Clamp Continuous Current Voltage Range SS, COMP, QR Voltage Range CS OUT Gate-Drive Voltage at DRV IOUT IOUT VCC Bias Supply Voltage –0.3 16 V TJ Operating Junction Temperature Range –40 +125 ºC TSTG Storage Temperature –55 +150 ºC ESD Human Body Model (HBM) JESD22-A114 2 kV Charged-Device Model (CDM) JESD22-C101 1 kV (1) (2) mA –0.3 45 V – 500 µA –0.3 7 V –0.3 1.25 V –0.3 Selflimiting V Peak OUT Current, Source – 0.3 A Peak OUT Current Sink – 0.7 A Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 3 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com THERMAL CHARACTERISTICS UNIT θJA (1) MSOP-8 Junction to Ambient 107 °C/W The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS MIN MAX VCC Bias Supply Voltage 8 14 UNIT V IVSD Current Sense 2 10 µA IQR QR Pin Current 1 4 mA TJ Junction Temperature –40 125 ºC ELECTRICAL CHARACTERISTICS Minimum and Maximum apply over the junction temperature range of –40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW = 100 kHz 50% Duty Cycle, No Load on OUT. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BIAS SUPPLY INPUT VCCON Controller enable threshold 12 12.8 13.5 V VCCOFF Minimum operating voltage 7.0 7.5 8.0 V VRST Internal logic reset (fault latch) 4.5 5.0 5.5 V ICCST ICC current while in standby mode COMP = 0.5V, CS = 0 V, no switching 340 420 µA ICCOP Operating supply current COMP = 2.25 V, OUT switching 800 µA SHUTDOWN CONTROL (VSD pin) IVSD OFF Off state leakage current 0.1 µA VVSD ON1 ON state pull-down voltage at 10 uA After VCCON (IVSD = 10 uA) 0.65 V VVSD_ON2 ON state pull-down voltage at 100 uA After VCCON (IVSD = 100 uA) 0.84 V SKIP CYCLE MODE COMPARATOR VSKIP Skip cycle mode enable threshold VSK-HYS Skip cycle mode hysteresis CS Rising 70 120 170 12 mV mV QR DETECT VOVP Overvoltage comparator threshold 2.85 3 3.17 V TOVP Sample delay for OVP 870 1050 1270 ns VDEM VDEM demagnetization threshold FMAX Maximum frequency 114 130 148 kHz TRST TRESTART 9.4 12 15.7 µs 0.35 V PWM COMPARATORS TPPWM COMP to OUT delay DMIN Minimum duty cycle GCOMP COMP to PWM comparator gain VCOMP-O COMP open circuit voltage VCOMP-H COMP at maximum VCS ICOMP COMP short circuit current RCOMP R pull-up COMP set to 2 V CS stepped 0 to 0.4 V, time to OUT transition low, CLOAD = 0 20 COMP = 0 V ns 0 % 5.8 V 0.33 I(COMP)=20µa 4.3 COMP = 0 V 4.9 2.25 V 132 µA 41 45 49 kΩ 450 500 550 mV CURRENT LIMIT VCS 4 Cycle-by-cycle sense voltage threshold Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and Maximum apply over the junction temperature range of –40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25°C, and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW = 100 kHz 50% Duty Cycle, No Load on OUT. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TLEB Leading edge blanking time TPCS Current limit to OUT delay RLEB CS blanking sinking impedance GCM Current mirror gain IQR = 2 ma 100 A/A CFF Current feed forward IQR = 2 ma 140 mV CS step from 0 to 0.6 V time to onset of OUT transition low, CLOAD = 0 130 ns 22 ns 15 Ω 35 HICCUP MODE TOL_10 Over load detection timer IVSD= 10 uA 12 ms TOL_100 Over load detection timer IVSD= 100 uA 1.2 ms OUTPUT GATE DRIVER VOH OUT high saturated IOUT = 50 mA, VCC-OUT 0.3 1.1 V VOL OUT low saturated IOUT = 100 mA 0.3 1 V IPH Peak OUT source current OUT = VCC/2 0.3 IPL Peak OUT sink current OUT = VCC/2 0.7 A tr Rise time CLOAD = 1 nF 25 ns tf Fall time CLOAD = 1 nF 15 ns A SOFT-START ISS Soft-start 17 22 30 µA THERMAL TSD Thermal shutdown temp 165 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 ºC 5 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM IVSD VSD VCC RVSD OLDT S OLDTS 4 Counter VCC VCCON 12.5V Rising SET S R SET CLR Q Q Q VCCMIN 7.5V Falling R CLR Q EN - R SET Q + VRST 5.0V THERMAL SHUTDOWN S CLR Q OVP + D SET tdlay Q - VOVP 3V CLR Q MAX Frequency clamp TRESTART QR - IQR Demag + EN VDEMAG 0.35V IQR/100 OUT Auto Zero Comp S SET Q + R OLDT VCS 6.6K Q GND 0.5V CS CLR OLDTS standby S Over Load Detection Timer LEB OLDTS PWM 5V COMP 4 x 60 x 10 9 sec IVSD R + 42k 2R R SLEEP MODE standby + VSKIP 5V 22uA + SS EN 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS 7.6 14 7.55 13.5 7.5 VCCOFF (V) VCCON(V) 13 12.5 12 7.45 7.4 7.35 7.3 11.5 7.25 7.2 11 -50 -25 0 25 50 75 100 TEMPERATURE (C) -50 125 -25 0 25 50 75 100 TEMPERATURE (C) C001 Figure 1. VCCON vs. Temperature 125 C002 Figure 2. VCCOFF vs. Temperature 5.1 400 390 5.05 380 370 ICCST(µA) VRST(V) 5 4.95 4.9 360 350 340 330 320 4.85 310 4.8 300 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 -50 0 25 50 75 100 TEMPERATURE (C) Figure 3. VRST vs. Temperature 125 C004 Figure 4. ICCST vs. Temperature 800 132 790 131 780 130 FMAX(kHz) ICCOP(µA) -25 C003 770 760 129 128 750 127 740 730 126 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 -50 C005 Figure 5. ICCOP vs. Temperature -25 0 25 50 75 100 TEMPERATURE (C) 125 C006 Figure 6. FMAX vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 7 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 550 CS THRESHOLD (mV) 540 530 520 510 500 490 480 470 460 450 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 C007 Figure 7. CS Threshold vs. Temperature 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 FUNCTIONAL DESCRIPTION The LM5023 is a Quasi-Resonant controller which contains all of the features needed to implement a highly efficient off-line power supply. The LM5023 uses the transformer auxiliary winding for demagnetization detection to ensure Quasi-Resonant operation (Valley-Switching) to minimize switching losses. For application that need to meet the ENERGY STAR® low standby power requirements, the LM5023 features an extremely low lq current (346 µA) and skip cycle mode which reduces power consumption at light loads. The LM5023 uses a feedback signal from the output to provide a very accurate output voltage regulation <1%. To reduce overheating and stress during a sustained overload conditions the LM5023 offers a hiccup mode for over current protection and provides a current limit restart timer to disable the outputs and forcing a delayed restart (hiccup mode). For offline start-up, an external Depletion Mode N Channel MOSFET can be used. This method is recommended for applications where a very low standby power (<50 mW) is required. For application where a low standby power is not as critical an enhancement mode, N Channel MOSFET can be used. If an OVP is detected on the auxiliary winding (QR pin), the IC permanently latches off, requiring recycling of power to restart Additional features include line-current-feed forward, pulse-by-pulse current limit, and a maximum frequency clamp of 130 kHz. START-UP Referring to Figure 8, when the AC rectified line voltage is applied to the bulk energy storage capacitor; the N Channel Depletion Mode MOSFET is turned on and supplies the charging current to the VCC capacitor. When the voltage on the VCC pin reaches 12.5 V typical, the PWM controller, soft-start circuit and gate driver are enabled. When the LM5023 is enabled and the OUT drive signal starts switching the Flyback MOSFET, energy is being stored and then transferred from the transformer primary to the secondary windings. A bias winding, shown in Figure 8, delivers energy to the VCC capacitor to sustain the voltage on the VCC pin. The voltage supplied from the auxiliary winding should be within the range of 10 V to 14 V (where 16 V is the absolute maximum rating). After reaching the VCCON threshold the LM5023 VSD open Drain output, which is pulled up to VCC during startup, goes low. This applies a negative Gate to Source voltage on the Depletion Mode MOSFET turning it off. This disables the high voltage start-up circuit. The high voltage start-up circuit can be implemented in either of two ways; the first is shown in Figure 8, which uses an N Channel Depletion Mode FET, the second is shown in Figure 9, which uses an N Channel Enhancement Mode FET. The circuit using the Depletion Mode FET will have the lowest standby power. The standby power consumption of the FET is the voltage across the start-up FET multiplied by the Drain to Source Cutoff current with Gate negatively biased, this is typically 0.1 µA. Standby Power of the Start-up FET calculation: • Vin = 230Vac • VCC = 10V • • • Vdc max = 230Vac · 2 = 325Vdc IDOFF = 0.1mA, IDOFF is the Depletion MODE FETs leakage current Pd = IDOFF · Vdc max = 0.1uA · 325Vdc = 32.5mW Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 9 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com 90-264 VAC High Voltage Start-up Depletion Mode FET QR OUT VCC RVSD CVCC CS LM5023 VSD GND Figure 8. Start-Up With a Depletion Mode FET An alternative start-up circuit employs an Enhancement Mode FET with resistors connected from the rectified dc bus to the Gate of the FET, Figure 9. After the input AC power is applied the Enhancement Mode FET supplies the charging current to the VCC capacitor CVCC. After reaching the VCCON threshold the LM5023 VSD open Drain output, which is pulled up to VCC during start-up, goes low. This grounds the Gate of the start-up MOSFET turning it off. The start-up resistors are always in the circuit, therefore the standby power consumed will be higher than if a Depletion Mode FET were used. • Vin = 230 Vac • VCC = 10 V • • • 10 Vdc max = 230Vac · 2 = 325Vdc Rstart - up = 10MW P Re sistors = Vdc 2 3252 = = 10.56mW Rstart - up 10MW Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 RSTART-UP 90-264 VAC High Voltage Start-up Enhancement Mode FET QR OUT VCC CVCC CS LM5023 VSD GND Figure 9. Start-Up With an Enhancement Mode FET Quasi Resonant Operation A Quasi-Resonant controlled Flyback converter operates by storing energy in the transformers primary during the MOSFETs on-time. During the on-time (TON) VIN is applied across the primary of the transformer. The primary current starts out at zero and ramps towards a peak value (IPEAK). When the peak primary current reaches the feedback compensation error voltage the PWM comparator resets the output drive, turning off the MOSFET. Due to the phasing of the transformer, the output diode is reversed biased during the MOSFET on-time. During the MOSFETs off time the output diode is forward biased and the stored energy in the transformer primary inductor is transferred to the output. The voltage seen on the secondary inductor is VOUT plus the output diodes forward voltage drop, VF. The current in the output inductor linearly decreases from IPEAK • Ns/Np to zero, refer to Figure 11. When the current in the secondary reaches zero, the transformer is demagnetized, and there is an open circuit on the secondary, and with the primary MOSFET also turned off, there is an open on the primary. A resonant circuit is formed between the transformers primary inductance and the MOSFET output capacitance. The resonant frequency is calculated by: Freq = 2gp LpgCOSS During the resonant period the Drain voltage of the MOSFET will ring down towards ground, refer to Figure 10. When the Drain voltage is at its minimum the Flyback MOSFET is turned back on. The point where the voltage is at its minimum is calculated by: td = p · Lp · COSS Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 11 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com Transformer is demagnetized Figure 10. The Flyback Drain Voltage Waveform Transformer demagnetization is detected by sensing the transformers auxiliary winding. When the transformer is demagnetized the auxiliary winding voltage follows the Drain of the MOSFET and changes from Vout•Naux/Ns to -Vin•Naux/Np. Internal to the LM5203 QR pin is a comparator with a 0.35 V reference. As the auxiliary winding voltage falls below 0.35 V, the voltage is sensed and the comparator sets the PWM Flip-Flop turning on the Flyback MOSFET. Figure 11 shows the QR Converter typical waveforms; the auxiliary winding voltage, primary, and secondary current waveforms. It is possible to adjustable the delay on the auxiliary winding with a resistor and external capacitor to ensures that the MOSFET switches when its Drain voltage is at its minimum, refer to the schematic in Figure 13 and the section on Valley Switching for details. The benefits of QR operation are reduced EMI, and turn-on switching losses. 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 Vaux 0V Vout x Naux Ns 0.35V The Auxillary Winding voltage Vaux Vin x Naux Np TOVP The peak Primary Current The peak Secondary Current ton toff td Tp Figure 11. QR Converter Typical Waveforms Quasi Resonant Operating Frequency When the primary side Flyback MOSFET turns on, the current ramps up until the peak primary current exceeds the feedback compensation error voltage. When this occurs the PWM comparator resets the output drive, turning off the MOSFET. The current ramps up with a slope of: Vin di = Lp dt The tON time of the switch is calculated by: ton = Lp · Ipk Vin When the primary side Flyback MOSFET is turned off, the energy stored in the primary inductance is transfer to the secondary inductance, the off time to transfer all of the energy is: toff = Ipk · n · Lp Vo + Vf Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 13 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com The total switching period is: Tp = ton + toff + tdly The resonant circuit created by the transformer primary inductance and the MOSFETs output capacitance is the tdly time, refer to Figure 11. tdly = p · Lp · COSS 2 Pout = 1 · Lp · Ipk 2 · Freq · h 2 Combining equations: Freq := 1 2 é é ù ù ê ê ng(Vo + Vf + Vin ú ú êLpg2gPout g ê hg é Ving éng Vo + Vf ù ù ú ú + tdly )û û û ú ë ( êë ë ë û From inspection of the equations, it can be seen that the QR Flyback converter does not operate at a fixed frequency. The frequency varies with the output load, input line voltage, or a combination of the two. In order to keep LM5023 frequency below the EMI starting limit of 150 kHz per CISPR--22, the LM5023 has an internal timer which prevents the output drive from restarting within 7.69 μs of the previous driver output (OUT) high to low transition. This timer clamps the maximum switching frequency from exceeding 130 kHz (typical). PWM Comparator The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The COMP pin voltage is reduced by a fixed 0.75 V offset and then attenuated by a 3:1 resistor divider. The PWM comparator input offset voltage is designed such that less than 0.75 V at the COMP pin will result in a zero duty cycle at the controller output. Soft-Start The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses and current surges. At power on, after the VCC reaches the VCCON threshold an internal 22 μA current source charges an external capacitor connected to the SS pin. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses. Gate Driver The LM5023 driver (OUT) was designed to drive the gate of an N Channel MOSFET and is capable of sourcing a peak current of 0.4 A and sinking 0.7 A. Skip Cycle Operation During light load conditions, the efficiency of the switching power supply typically drops as the losses associated with switching and operating bias currents of the converter become a significant percentage of the power delivered to the load. The largest component of the power loss is the switching loss associated with the gate driver and external MOSFET gate charge. Each PWM cycle consumes a finite amount of energy as the MOSFET is turned on and then turned off. These switching losses are proportional to the frequency of operation. To improve the light load efficiency the LM5023 enters a Skip Cycle mode during light load conditions. As the output load is decreased, the COMP pin voltage is reduced by the voltage feedback loop to reduce the Flyback converters peak primary current. Referring to the Block Diagram , the PWM comparator input tracks the COMP pin voltage through a 0.75 V level shift circuit and a 3:1 resistor divider. As the COMP pin voltage falls, the input to the PWM comparator falls proportionately. When the PWM comparator input falls to 125 mV, the Skip Cycle comparator detects the light load condition and disables output pulses from the controller. The LM5023 also reduces all internal bias currents, while in skip mode, to further reduce quiescent power. The controller continues to skip switching cycles until the power supply output falls and the COMP pin voltage increases to demand more output current. The number of cycles skipped will depend on the load and the response time of the frequency 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 voltage loop compensation network. Eventually the COMP voltage will increase when the voltage loop requires more current to sustain the regulated output voltage. When the PWM comparator input exceeds 135 mV (10 mV hysteresis), normal fixed frequency switching resumes. Typical light load operation power supply designs will produce a short burst of output pulses followed by a long skip cycle interval (no drive pulses). The result is a large reduction in the average input power. Current Limit/Current Sense The LM5023 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal current sense comparator with a threshold of 500 mV. If the CS pin voltage plus the current limit feed forward signal voltage exceeds 500 mV, the MOSFET drive signal (OUT) will be terminated. An RC filter, located near the LM5023 CS pin is recommended to attenuate the noise coupled from the power FET’s gate to source switching. The CS pin capacitance is discharged at the end of each PWM cycle by an internal switch. The discharge switch remains on for an additional 90 ns for Leading Edge Blanking (LEB). LEB prevents the LM5023 current sense comparator from being falsely triggered due to the noise generated by the switch currents initial spike. The LM5023 current sense comparator is very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense resistor, which should also be located close to the IC. If a current sense resistor located in the power FET’s source is used for current sense, a low inductance resistor is required. In this case, all of the noise sensitive low current grounds should be connected in common near the IC and then a single connection should be made. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 15 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com APPLICATION INFORMATION Line Current Limit Feed Forward In a peak current mode controlled when the power supply is in an overload, the peak current (measured across the current sense resistor VCS) is compared to a voltage reference for overload protection. If the peak current exceeds the reference the LM5023 controller will turn off the primary side Flyback MOSFET on a cycle-by-cycle basIs. However, the primary switch can’t be turned off instantly, as there are several unavoidable delays. The first delay is caused by the LEB circuit which provides leading-edge blanking. The second delay is caused by the propagation delay between the detecting point of VCS and the actual turn off of the power MOSFET. The total delay time (tprop) refer to Figure 12, includes the current limit comparator, the logic, the gate driver, and the power MOSFET turning off. The propagation delay causes the peak primary current to overshoot, the overshoot increase the maximum peak current beyond the calculated value. The peak current overshoot increase as the AC line voltage increase because of the increase in the slope of the primary current: Vin di = Lp tprop This increase in the peak input current overshoot causes a wide variation of overpower limit in a Flyback converter. In Figure 4, it can be seen that the overpower limit increases with the input line voltage, because of Ipkmax increase: Ipk max = Pout · 2 Vin + · tprop Lp · Freq · h Lp 1 · Ipk max 2 · Lp · Freq 2 Pin Pout = h Pin = 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 Vin Lp 'I HL High Line 'I Ipk/Rsense LL Low Line tpropHL Gate Drive tpropLL Figure 12. Line Current Feed Forward To improve the overpower limit accuracy over the full Universal Input Line; the LM5023 integrates Line Current Limit Feed Forward. Line Current Limit Feed Forward improve the overpower limit by summing a current proportional to the input rectified line into the current sense resistor RSENSE), refer to Figure 13. The current proportional to the input line biases up the current sense pin, this turns off the Flyback MOSFET earlier at high input line. This feature compensates for the propagation delays creating a overpower protection that is nearly constant over the Universal Input Line. To implement Line Current Limit Feed Forward, the first step is to calculate the QR switching frequency at low line and then at high line when the power supply is operating in current limit. For our example: • Lp = 400 µH • RSENSE = 0.15 Ω • Vdcmin = 127 V • Vdcmax = 325 V • Tprop = 160 ns • VCS = 0.5 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 17 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 • • • www.ti.com naux = 10.9 n = ns/np = .167 tdly = 580 ns Freq _ LL = Freq _ LL = Freq _ HL = Freq _ HL = 1 éæ 1 ö ù 1 æ VCS ö ç Rsense ÷ · Lp · êç Vdc min ÷ + (Vout + Vf ) · n ú + tdly è ø ø ëè û 1 éæ 1 ö ù 1 æ 0.5V ö ç 0.15W ÷ · 400mH · êç 127V ÷ + (19V + 0.7V) · 6 ú + 580ns è ø ø ëè û = 49.6kHz 1 éæ ù 1 ö 1 æ VCS ö ç Rsense ÷ · Lp · êç Vdc max ÷ + (Vout + Vf ) · 6 ú + tdly è ø ø ëè û 1 éæ 1 ö ù 1 æ 0.5V ö ç 0.15W ÷ · 400mH · êç 325V ÷ + (19V + 0.7V) · 6 ú + 580ns è ø ø ëè û = 62.3kHz The next step is to calculate the uncompensated output power at the minimum and maximum input line voltage while in current limit. 2 1 æ VCS ö Pout _ LL = · Lp · ç ÷ · Freq _ LL · h 2 è Rsense ø 2 1 æ 0.5 ö Pout _ LL = · 400mH · ç ÷ · 49.6kHz · 0.86 = 94.9W 2 è 0.15 ø 2 1 æ VCS ö Pout _ HL = gLpgç ÷ gFreq _ HLgh 2 è Rsense ø 2 1 æ 0.5 ö Pout _ HL = g400mHgç ÷ g62.3kHzg0.86 = 119.1W 2 è 0.15 ø Step three is to calculate the peak current at high line so it does not deliver more power than while it is operating at low line (94.9 W). One thing that complicates the Line Current Limit Feed Forward calculation is that with Quasi Resonant operation the switching frequency changes with line and load. We have one equation and two unknowns, the peak primary current and the QR frequency. This requires use of the quadratic equation: ax 2 + Bx + C = 0 The positive root is: X (B + = B2 + 4DT 4 Freq _ Comp = 18 ) 4 é êæ 2 êç 4 · tdly + 2 · Lp · Pout _ LL · (Vout + Vf + n · Vdc max) 2 2 êç h · Vdc max · (Vout + Vf ) êè ëê ö ÷+ ÷ ø Submit Documentation Feedback 2 · Lp · Vout + Vf + n · Vdc max· Vdc max· (Vout + Vf ) Pout _ LL ù ú h · Lp ú ú ú ûú 2 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 Freq _ Comp = 4 é êæ 2 êç 4 · 580ns + 2 · 400mH · 94.9 · (19 + 0.7 + 0.167 · 325V) 2 2 êç 0.86 · 325V · (19V + 0.7V ) êè ëê ö ÷+ ÷ ø 2 · 400mH · (19V + 0.7V + 0.167 · 325V) · 325V · (19V + 0.7V) ù 94.9W ú 0.86 · 400mH ú ú ú ûú 2 = 76.8kHz Step four is to calculate the peak current. IL max_ LL = 2 · Pout _ LL h · Lp · Freq _ Comp IL max_ LL = 2 · 94.9W = 2.679Apk 0.86 · 400mH · 76.8kHz é ù æ Vdc max ö VCS _ CL = Rsense · êIL max_ CL - ç ÷ · tprop ú Lp è ø ë û é ù æ 325V ö VCS _ CL = 0.15W · ê2.679Apk - ç ÷ · 160ns ú = 0.382V è 400mH ø ë û For the power supply to go into pulse-by-pulse current limit the voltage across the current sense resistor must be 0.5 V, so: VCS _ OFFSET := VCS - VCS _ CL VCS_OFFSET is the required voltage offset that must be injected across the current sense resistor, RSENSE. VCS _ OFFSET := VCS - VCS _ CL = 0.5V - 0.382V = 0.118V After calculating the required offset voltage, use the following equations to calculate the required current feed forward: While the main Flyback switch is on, Q1, the voltage on the Auxiliary winding will be negative and proportional to the rectified line. - Vaux = IQR = Vdc Naux - Vaux ROFFSET IQR should be chosen in the range of 1 ma to 4 ma. The demagnetization circuit impedance should be calculated to limit the maximum current flowing through Pin 1 to less than 4 mA. ROFFSET = 6.6 kΩ + REXTERNAL (the 6.6 kΩ resistance is internal to the LM5023). Where: Naux is the number of turns on the Flyback primary (Np) divided by the number of turns on the transformer Auxiliary (Naux) winding. The current mirror in the QR pin input has a gain of 100; this will offset the voltage on the current sense pin by: VCSOFFSET = IQR · (6.6kW + REXTERNAL ) 100 Set IQR= 1.75 mA Vdc max 325V R1 = naux = = 17.0kW 10.9 IQR 1.75mA Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 19 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 ROFFSET = www.ti.com VOFFSET 0.118V · 100 = · 100 = 6742W IQR 1.75mA ROFFSET = RINTERNAL + REXTERNAL REXTERNAL = ROFFSET - 6.6kW = 6742W - 6.6kW = 142W No external resistor is required based on the applications describe above, so a 499 Ω resistor and 100 pF capacitor are installed in the CS pin input as a noise filter. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 VCC+VD 0V -Vdc/naux Vaux Np Naux Ns R1 R2 RCFF=R1//R2 Cd Vaux IQR VCC QR OUT 1k CS Q1 REXTERNAL IQR/100 Rsense VCSOFFSET LM5023 GND Figure 13. Current Feed Forward Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 21 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com Overvoltage Protection Output overvoltage protection is implemented with the LM5023 by monitoring the QR pin during the time when the main Flyback MOSFET is off and the energy stored in the transformer primary is being transferred to the secondary. There is a delay prior to sampling the QR pin during the MOSFETs off time, TOVP. There are two reasons for the delay, the first is to blank the voltage spike which is a result of the transformers leakage inductance. The second is to improve the accuracy of the output voltage sensing, referring to the transformer auxiliary winding voltage shown in Figure 11. It is clear there is a down slope in the voltage which represents the decreasing VF of the output rectifier and resistance voltage drop (IS x RS) as the secondary current decreases to zero, so by delaying the sampling of the QR voltage a more accurate representation of the output voltage is achieved. Connected to the QR pin is a comparator with a 3.0 V reference. The transformers auxiliary voltage is proportional to Vout by the transformers turns ratio: Vaux=(VO+VF)·Naux/Ns (1) To set the OVP, a voltage divider is connected to the transformers auxiliary winding, refer to Figure 12. In the section titled Line Current Limit Feed Forward, we developed equations to improve the power limit. Resistor R1 was calculated for Line Current Limit Feed Forward; to implement OVP we now need to calculate R2. VOVP = Vaux _ OVP · R2 = 3.0V · R2 R1 + R2 R1 Vaux _ OVP - 3V When an OVP fault has been detected, the LM5023 OUT driver is latched-off. VCC will discharge to VCCMIN and the VSD pin will be asserted high, allowing the Depletion Mode FET to turn-on and charge up the VCC capacitor to VCCON. The VSD pin will be toggled on-off-on to maintain VCC to the controller. The only way to clear the fault is to removed the input power and allow the controllers VCC voltage to drop below VRST, 5.0 V. Valley Switching For QR operation the Flyback MOSFET is turned on with the minimum Drain voltage. The delay on the auxiliary winding can be adjusted with an external resistor and capacitor to improve valley switching. The delay-time, tdly, must equal half of the natural oscillation period: tdly = p · Lp · COSS 2 By substituting tdly = RFF · Cd We can calculate the RC time constant to achieve the minimum Drain voltage when the LM5023 turns on the Flyback MOSFET. éæ p ö ù êç 2 ÷g Lpused gCoss ú è ø û Cd := ë RFF The LM5023 QR pin’s capacitance is approximately 20 pF, so CdUSED = Cd -20 pF RFF := (R1gR2 ) (R1 + R2 ) R1 and R2 were previously calculated to set the Line Current Limit Feed Forward and Overvoltage protection. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 Hiccup Mode Hiccup Mode is a method to prevent the power supply from over-heating during and extended overload condition. In an overload fault, the current limit comparator turns off the driver output on pulse-by-pulse basis. This starts the Over Load Detection Timer, after the Over Load Detection Timer (OLDT) times out, the current limit comparator is rechecked, if the power supply is still in an overload condition, the OUT drive is Latched-off and VCC is allowed to drop to VCCOFF (7.5 V). When VCC reaches VCCOFF, the VSD open drain output is disabled allowing the Depletion Mode start-up FET to turn-on, charging up the VCC capacitor to VCCON (12.5 V). When VCC reaches VCCON, the VSD output goes low turning-off the Depletion Mode FET. The VCC capacitor is discharged from VCCON to VCCOFF at a rate proportional to the VCC capacitor and the ICCST current (346 µA typical). The charging and discharging of the VCC capacitor is repeated four times (refer to Figure 14) so the total Hiccup time is: tHICCUP = tCHARGE · 4 + tDISCHARGE · 4 After allowing VCC to charge and discharge four times, the LM5023 goes through an auto restart sequence, enabling the LM5023 soft-start and driver output. It is important to set the Over Load Detection Timer long enough so that under low input line and full load conditions that the power supply will have enough time to startup. The Over Load Detection Timer can be set with the resister in series with the VSD pin ®VSD), refer to Figure 8. IVSD = VCC 10V = = 10mA RVSD 1MW OVER _ Load _ Detection _ Timer = 2 · 60nA 2 · 60nA = = 12m sec IVSD 10mA Normally it is recommended that RVSD>1 MΩ, if a lower value is used then the standby power will be higher. Assuming: If the Depletion VCC Capacitor is 10 uF. tCHARGE = Mode FET charges the VCC capacitor with 2 mA, (VCCON - VCCOFF ) · CVCC = 12.5V -7.5V · 10nF = 25ms tDISCHARGE = ICHARGE 2mA (VCCON - VCCOFF ) · CVCC = 12.5V -7.5V · 10mF = 145ms ICCST 346 mA tHICCUP = 25ms · 4 + 145ms · 4 = 680ms Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 23 LM5023 SNVS961C – APRIL 2013 – REVISED AUGUST 2013 www.ti.com The Depeletion FET charging current into the VCC cap 2mA The current comsumption of the LM5023 while the OCP Flag is set ICCST=346uA VCCON 12.5V VCCAUX 10V VCCOFF 7.5V OLDTS OUT VSD SS 25ms 145ms Hicup Mode Figure 14. Hiccup Mode Timing 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 LM5023 www.ti.com SNVS961C – APRIL 2013 – REVISED AUGUST 2013 EVALUATION BOARD SCHEMATIC Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM5023 25 PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM5023MM-2/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SK9B LM5023MMX-2/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SK9B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5023MM-2/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5023MMX-2/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5023MM-2/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5023MMX-2/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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