TI TPS2544RTER

TPS2544
www.ti.com
SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
USB Charging Port Controller and Power Switch
Check for Samples: TPS2544
FEATURES
APPLICATIONS
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
D+/D– CDP/DCP Modes per USB Battery
Charging Specification 1.2
D+/D– Shorted Mode per Chinese
Telecommunication Industry Standard YD/T
1591-2009
Support non-BC1.2 charging modes by
automatic selection
– D+/D– Divider Modes 2.0V/2.7V and 2.7/2.0V
– D+/D- 1.2V Mode
Supports Sleep-Mode Charging and
Mouse/Keyboard Wake Up
Automatic SDP/CDP Switching for devices that
do not connect to CDP ports
Compatible with USB 2.0 and 3.0 Power Switch
requirements
Integrated 73-mΩ (typ) High-Side MOSFET
Adjustable Current-Limit up to 3.0 A (typ)
Operating Range: 4.5V to 5.5V
Max device current
– 2µA when device disabled
– 270µA when device enabled
Drop-In and BOM Compatible with TPS2543
and TPS2546
Available in 16-Pin QFN (3x3) Package
8KV ESD rating on DM/DP pins
UL Listed and CB File No. E169910
USB Ports (Host and Hubs)
Notebook and Desktop PCs
Universal Wall Charging Adapters
DESCRIPTION
The TPS2544 is a USB charging port controller and
power switch with an integrated USB 2.0 high-speed
data line (D+/D–) switch. TPS2544 provides the
electrical signatures on D+/D– to support charging
schemes listed under device feature section. TI tests
charging of popular mobile phones, tablets and media
devices with the TPS2544 to ensure compatibility with
both BC1.2 compliant and non-compliant devices. In
addition to charging popular devices, TPS2544 also
supports system wake up (from S3) with a
mouse/keyboard; both low speed and full speed are
supported.
The TPS2544 73-mΩ power-distribution switch is
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered.
Two programmable current thresholds provide
flexibility for setting current limits.
IN
ILIM_LO
FAULT
16
GND
ILIM_HI
TPS2544 RTE PACKAGE AND TYPICAL APPLICATION DIAGRAM
15
14
13
1
To Portable Device à
Power Bus
DM_OUT
2
11
DM_IN
DP_OUT
3
10
DP_IN
Power Switch EN
ILIM_SEL
4
9
NC
Mode Select I/O
8
EN
CLT1
CLT2
CLT3
Thermal Pad
7
IN
OUT
CUSB
ILIM_LO
ILIM_HI
TPS2544
OUT
Fault Signal
6
0.1 uF
RFAULT
(10 kW)
12
5
4.5V – 5.5V
ILIM Select
FAULT
ILIM_SEL
EN
CTL1
CTL2
CTL3
RILIM_HI
VBUS
DD+
GND
RILIM_LO
GND
DM_IN
DP_IN
DM_OUT
DP_OUT
USB
Connector
To Host Controller à
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS2544
SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
TA
PACKAGE
DEVICE
TOP-SIDE MARKING
–40°C to 85°C
QFN16
TPS2544
2544
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range, voltages are referenced to GND (unless otherwise noted)
LIMIT
IN, EN, ILIM_LO, ILIM_HI, FAULT, ILIM_SEL, CTL1,
CTL2, CTL3, OUT
Voltage range
IN to OUT
UNIT
–0.3 to 7
V
–7 to 7
DP_IN, DM_IN, DP_OUT, DM_OUT
–0.3 to (IN + 0.3) or 5.7
Input clamp current
DP_IN, DM_IN, DP_OUT, DM_OUT
±20
mA
Continuous current in SDP or CDP
mode
DP_IN to DP_OUT or DM_IN to DM_OUT
±100
mA
Continuous current in BC1.2 DCP
mode
DP_IN to DM_IN
±50
mA
Continuous output current
OUT
Continuous output sink current
FAULT
Continuous output source current
ILIM_LO, ILIM_HI
ESD rating
Internally limited
mA
Internally limited
mA
HBM
2
HBM wrt GND and each other, DP_IN, DM_IN, OUT
8
CDM
Operating junction temperature, TJ
(1)
25
kV
500
V
–40 to Internally limited
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS2546
RTE (16 PIN)
θJA
Junction-to-ambient thermal resistance
53.4
θJCtop
Junction-to-case (top) thermal resistance
51.4
θJB
Junction-to-board thermal resistance
17.2
ψJT
Junction-to-top characterization parameter
3.7
ψJB
Junction-to-board characterization parameter
20.7
θJCbot
Junction-to-case (bottom) thermal resistance
3.9
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
RECOMMENDED OPERATING CONDITIONS
voltages are referenced to GND (unless otherwise noted)
MIN
VIN
Input voltage, IN
NOM
MAX
UNIT
4.5
5.5
V
Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL
0
5.5
V
Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT
0
VIN
V
VIH
High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
1.8
V
VIL
Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
0.8
V
Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to
DM_OUT
±30
mA
±15
mA
Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN
IOUT
Continuous output current, OUT
0
2.5
A
Continuous output sink current, FAULT
0
10
mA
RILIM_XX
Current-limit set resistors
16.9
750
kΩ
TJ
Operating virtual junction temperature
–40
125
°C
ELECTRICAL CHARACTERISTICS
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with
respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SWITCH
RDS(on)
On resistance
(1)
tr
OUT voltage rise time
tf
OUT voltage fall time
ton
OUT voltage turn-on time
toff
OUT voltage turn-off time
IREV
Reverse leakage current
TJ = 25°C, IOUT = 2 A
73
84
–40°C ≤ TJ ≤ 85°C, IOUT = 2 A
73
105
–40°C ≤ TJ ≤ 125°C, IOUT = 2 A
73
120
0.7
1.0
1.60
0.2
0.35
0.5
2.7
4
1.7
3
VIN = 5 V, CL = 1 µF, RL = 100 Ω (see Figure 20 and
Figure 21)
VIN = 5V, CL = 1 µF, RL = 100 Ω (see Figure 20 and
Figure 22)
VOUT = 5.5 V, VIN = VEN = 0 V, –40 ≤ TJ ≤ 85°C,
Measure IOUT
mΩ
ms
ms
2
µA
DISCHARGE
RDCHG
OUT discharge resistance
VOUT = 4 V, VEN = 0 V
400
500
630
Ω
tDCHG
OUT discharge hold time
Time VOUT < 0.7 V (see Figure 23)
1.30
2.0
2.9
s
(1)
Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with
respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic threshold
voltage
1
1.35
1.70
Input pin falling logic threshold
voltage
0.85
1.15
1.45
Hysteresis (2)
Input current
200
Pin voltage = 0 V or 5.5 V
–0.5
VILIM_SEL = 0 V, RILIM_LO = 210 kΩ
205
V
mV
0.5
µA
ILIMSEL CURRENT LIMIT
OUT short circuit current limit (3)
IOS
Response time to OUT shortcircuit (2)
tIOS
240
275
625
680
VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ
575
VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ
2120
2275 2430
VILIM_SEL = VIN, RILIM_HI= 20 kΩ
2340
2510 2685
VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ
2770
2970 3170
VIN = 5.0 V, R = 0.1Ω, lead length = 2 inches (see
Figure 24)
1.5
mA
µs
SUPPLY CURRENT
IIN_OFF
IIN_ON
Disabled IN supply current
Enabled IN supply current
VEN = 0 V, VOUT = 0 V, –40 ≤ TJ ≤ 85°C
0.1
2
VCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = 0 V
165
220
VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0 V
175
230
VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN
185
240
VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN
195
250
VCTL1 = 0V, VCTL2 = VCTL3 = VIN
215
270
4.1
4.3
µA
µA
UNDERVOLTAGE LOCKOUT
VUVLO
IN rising UVLO threshold voltage
3.9
Hysteresis (2)
100
V
mV
FAULT
Output low voltage
I FAULT = 1 mA
Off-state leakage
V FAULT = 5.5 V
Over current FAULT rising and
falling deglitch
5
8.2
100
mV
1
µA
12
ms
THERMAL SHUTDOWN
Thermal shutdown threshold
155
Thermal shutdown threshold in
current-limit
135
Hysteresis
(2)
(3)
4
(2)
°C
20
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
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ELECTRICAL CHARACTERISTICS, HIGH-BANDWIDTH SWITCH
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = VCTL2 = VCTL3 = VIN. R FAULT =
10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with
respect to GND.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
HIGH-BANDWIDTH ANALOG SWITCH
DP/DM switch on resistance
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA
2
4
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA
3
6
Switch resistance mismatch between
DP / DM channels
VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA
0.05
0.15
VDP/DM_OUT = 2.4 V, IDP/DM_IN = –15 mA
0.05
0.15
DP/DM switch off-state capacitance (1)
VEN = 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk,
f = 1 MHz
3
3.6
6.2
DP/DM switch on-state capacitance
(2)
Ω
Ω
pF
VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz
5.4
OIRR
Off-state isolation (3)
VEN = 0 V, f = 250 MHz
33
dB
XTALK
On-state cross channel isolation (3)
f = 250 MHz
52
dB
Off state leakage current
VEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V,
measure IDP/DM_OUT
0.1
BW
Bandwidth (–3dB) (3)
RL = 50 Ω
tpd
Propagation delay (3)
tSK
Skew between opposite transitions of the
same port (tPHL – tPLH)
(1)
(2)
(3)
1.5
pF
µA
2.6
GHz
0.25
ns
0.1
0.2
ns
The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
The resistance in series with the parasitic capacitance to GND is typically 150 Ω
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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ELECTRICAL CHARACTERISTICS, CHARGING CONTROLLER
Unless otherwise noted: –40 ≤ TJ ≤ 125°C, 4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, VILIM_SEL = VIN, VCTL1 = 0 V, VCTL2 = VCTL3 = VIN. R
FAULT = 10 kΩ, RILIM_HI = 20 kΩ, RILIM_LO = 80.6 kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are
with respect to GND.
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
125
200
Ω
1.19
1.25
1.31
V
60
75
94
kΩ
DP_IN Divider1 output voltage
1.9
2.0
2.1
V
DM_IN Divider1 output voltage
2.57
2.7
2.84
V
8
10.5
12.5
kΩ
8
10.5
12.5
kΩ
DP_IN Divider2 output voltage
2.57
2.7
2.84
V
DM_IN Divider2 output voltage
SHORTED MODE (BC1.2 DCP)
MIN
VCTL1 = VIN, VCTL2 = VCTL3 = 0V
DP_IN / DM_IN shorting resistance
1.2V Mode
DP_IN /DM_IN output voltage
DP_IN /DM_IN output impedance
DIVIDER1 MODE
DP_IN output impedance
DM_IN output impedance
DIVIDER2 MODE
IOUT = 1A
1.9
2.0
2.1
V
DP_IN output impedance
8
10.5
12.5
kΩ
DM_IN output impedance
8
10.5
12.5
kΩ
0.5
0.6
0.7
V
0.4
V
CHARGING DOWNSTREAM PORT
VCTL1 = VCTL2 = VCTL3 = VIN
VDP_IN = 0.6 V,
–250 µA < IDM_IN < 0 µA
VDM_SRC
DM_IN CDP output voltage
VDAT_REF
DP_IN rising lower window threshold for
VDM_SRC activation
0.25
Hysteresis (1)
VLGC_SRC
50
DP_IN rising upper window threshold for
VDM_SRC de-activation
0.8
hysteresis (1)
IDP_SINK
(1)
6
DP_IN sink current
mV
1
100
VDP_IN = 0.6 V
40
70
V
mV
100
µA
These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS
POWER SWITCH ON RESISTANCE
vs
TEMPERATURE
REVERSE LEAKAGE CURRENT
vs
TEMPERATURE
0.3
100
0.25
Reverse Leakage Current (µA)
On Resistance (mΩ)
90
80
70
60
0.2
0.15
0.1
0.05
50
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
0
−40 −25 −10
110 125
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G001
G002
Figure 1.
Figure 2.
OUT DISCHARGE RESISTANCE
vs
TEMPERATURE
OUT SHORT CIRCUIT CURRENT LIMIT
vs
TEMPERATURE
580
3000
OUT Short Circuit Current Limit (mA)
OUT Discharge Resistance (Ω)
560
3500
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
540
520
500
480
460
−40 −25 −10
2500
2000
1500
RILIM_LO = 210 kΩ
RILIM_LO = 80.6 kΩ
RILIM_HI = 20 kΩ
RILIM_HI = 16.9 kΩ
1000
500
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G003
Figure 3.
G004
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
DISABLED IN SUPPLY CURRENT
vs
TEMPERATURE
ENABLED IN SUPPLY CURRENT - SDP
vs
TEMPERATURE
1.2
190
VIN = 5.5 V
180
Enabled IN Supply Current (µA)
Disabled IN Supply Current (µA)
1
0.8
0.6
0.4
0.2
0
−40
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
170
160
150
Device configured for SDP
VILIMSEL = 0 V
140
−20
0
20
40
60
Junction Temperature (°C)
80
130
−40 −25 −10
100
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G005
G006
Figure 5.
Figure 6.
ENABLED IN SUPPLY CURRENT - CDP
vs
TEMPERATURE
ENABLED IN SUPPLY CURRENT - DCP AUTO
vs
TEMPERATURE
220
230
Enabled IN Supply Current (µA)
Enabled IN Supply Current (µA)
210
240
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
200
190
180
170
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
220
210
200
190
Device configured for CDP
160
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
Device configured for DCP AUTO
110 125
180
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
G007
Figure 7.
8
95
110 125
G008
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
FAULT OUTPUT LOW VOLTAGE
vs
SINKING CURRENT
DATA TRANSMISSION CHARACTERISTICS
vs
FREQUENCY
0
700
TJ = −40°C
TJ = 25°C
TJ = 125°C
600
500
Transmission Gain - dB
Output Low Voltage (mV)
-5
400
300
200
-10
-15
-20
100
VIN = 4.5 V
0
0
1
2
3
4
5
6
7
Sinking Current (mA)
8
9
10
-20
0.01
G009
1
10
Frequency - GHz
Figure 10.
Figure 9.
OFF STATE DATA SWITCH ISOLATION
vs
FREQUENCY
ON STATE CROSS-CHANNEL ISOLATION
vs
FREQUENCY
60
XTALK - ON State Cross-Channel Isolation - dB
80
50
OIRR - Off State Isolation - dB
0.1
40
30
20
10
70
60
50
40
30
20
10
0
0
0.01
0.1
1
10
0.01
0.1
1
10
Frequency - GHz
Figure 12.
Frequency - GHz
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN
(with data switch)
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
Differential Signal (V)
Differential Signal (V)
EYE DIAGRAM USING USB COMPLIANCE TEST PATTERN
(with no switch)
0.1
0
–0.1
–0.2
0.1
0
–0.1
–0.2
–0.3
–0.3
–0.4
–0.4
–0.5
–0.5
0
0.2
0.4
0.6
0.8
1 1.2
Time (ns)
1.4
1.6
1.8
0
2
G013
0.4
0.6
0.8
1 1.2
Time (ns)
1.4
1.6
1.8
2
G014
Figure 13.
Figure 14.
TURN-ON RESPONSE
TURN-OFF RESPONSE
VOUT
2 V/div
VOUT
2 V/div
VEN
5 V/div
VEN
5 V/div
RLOAD = 5 Ω
CLOAD = 150 µF
RLOAD = 5 Ω
CLOAD = 150 µF
IIN
500 mA/div
t - Time - 1 ms/div
Figure 15.
10
0.2
IIN
500 mA/div
G021
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t - Time - 1 ms/div
Figure 16.
G022
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TYPICAL CHARACTERISTICS (continued)
DEVICE ENABLED INTO SHORT CIRCUIT - THERMAL
CYCLING
DEVICE ENABLED INTO SHORT CIRCUIT
V/FAULT
5 V/div
V/FAULT
5 V/div
VEN
5 V/div
VEN
5 V/div
RILM_LO = 80.6 kΩ
IIN
500 mA/div
t - Time - 2 ms/div
Figure 17.
RILM_HI = 20 kΩ
IIN
1 A/div
t - Time - 5 ms/div
Figure 18.
G023
G024
SHORT CIRCUIT to FULL LOAD RECOVERY
V/FAULT
5 V/div
VOUT
2 V/div
RILIM_HI = 20 kΩ
RLOAD = 5 Ω
CLOAD = 150 µF
IIN
2 A/div
t - Time - 2 ms/div
Figure 19.
G025
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PARAMETER MEASUREMENT DESCRIPTION
OUT
RL
VOUT
CL
tr
tf
90%
10%
Figure 20. OUT Rise/Fall Test Load
Figure 21. Power-On and Off Timing
5V
VEN
50 %
50 %
tDCHG
VOUT
ton
toff
0V
90 %
VOUT
10 %
Figure 22. Enable Timing, Active High Enable
Figure 23. OUT Discharge During Mode Change
IOS
IOUT
tIOS
Figure 24. Output Short Circuit Parameters
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DEVICE INFORMATION
IN
1
DM_OUT
2
ILIM_HI
ILIM_LO
GND
FAULT
TPS2544 RTE PACKAGE
(Top View)
16
15
14
13
12
OUT
11
DM_IN
DP_IN
Thermal Pad
ILIM_SEL
4
9
6
7
NC
8
CLT3
5
CLT2
10
CLT1
3
EN
DP_OUT
PIN FUNCTIONS
NO.
(1)
NAME
TYPE (1)
P
DESCRIPTION
Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close
to the device as possible
1
IN
2
DM_OUT
I/O
D– data line to USB host controller
3
DP_OUT
I/O
D+ data line to USB host controller
4
ILIM_SEL
I
Logic-level input signal used to control the charging mode current limit threshold; see the control truth
table. Can be tied directly to IN or GND without pull-up or pull-down resistor.
5
EN
I
Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal
and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pull-up or
pull-down resistor.
6
CTL1
I
7
CTL2
I
8
CTL3
9
-
N/C
Connect to GND or leave open
10
DP_IN
I/O
D+ data line to downstream connector
11
DM_IN
I/O
D– data line to downstream connector
12
OUT
P
Power-switch output
13
FAULT
O
Active-low open-drain output, asserted during over-temperature or current limit conditions
14
GND
P
Ground connection
15
ILIM_LO
I
External resistor connection used to set the low current-limit threshold. A resistor to ILIM_LO is optional;
see Current-Limit Settings in DETAILED DESCRIPTION.
16
ILIM_HI
I
External resistor connection used to set the high current-limit threshold
NA
PowerPAD
Logic-level inputs used to control the charging mode and the signal switches; see the control truth table.
Can be tied directly to IN or GND without pull-up or pull-down resistor.
I
Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect to GND
plane.
G = Ground, I = Input, O = Output, P = Power, N/C = No Connect
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TPS2544 FUNCTIONAL BLOCK DIAGRAM
Current
Sense
CS
IN
OUT
Disable + UVLO+Discharge
ILIM_HI
Current
Limit
Current Limit
select
Charge
Pump
ILIM_LO
GND
OC
8-ms Deglitch
OTSD
Thermal
Sense
UVLO
ILIM_SEL
Driver
EN
discharge
FAULT
8-ms Deglitch
(falling edge)
DM_OUT
DM_IN
DP_OUT
DP_IN
ILIM_SEL
OC
CTL1
CTL2
Logic
control
CDP
Detection
DCP
Detection
Divider
Mode
Auto-Detection
Discharge
CTL3
Discharge
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DETAILED DESCRIPTION
Overview
The following overview references various industry standards. It is always recommended to consult the most upto-date standard to ensure the most recent and accurate information. Rechargeable portable equipment requires
an external power source to charge its batteries. USB ports are a convenient location for charging because of an
available 5V power source. Universally accepted standards are required to make sure host and client-side
devices operate together in a system to ensure power management requirements are met. Traditionally, host
ports following the USB 2.0 specification must provide at least 500mA to downstream client-side devices.
Because multiple USB devices can be attached to a single USB port through a bus-powered hub, it is the
responsibility of the client-side device to negotiate its power allotment from the host to ensure the total current
draw does not exceed 500mA. In general, each USB device is granted 100mA and may request more current in
100mA unit steps up to 500mA. The host may grant or deny based on the available current. A USB 3.0 host port
not only provides higher data rate than USB 2.0 port but also raises the unit load from 100mA to 150mA. It is
also required to provide a minimum current of 900mA to downstream client-side devices.
Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables.
This allows a portable device to charge from both a wall adapter and USB port with only one connector. As USB
charging has gained popularity, the 500mA minimum defined by USB 2.0 or 900mA for USB 3.0 has become
insufficient for many handset and personal media players which need a higher charging rate. Wall adapters can
provide much more current than 500mA/900mA. Several new standards have been introduced defining protocol
handshaking methods that allow host and client devices to acknowledge and draw additional current beyond the
500mA/900mA minimum defined by USB 2.0/3.0 while still using a single micro-USB input connector.
The TPS2544 supports four of the most common USB charging schemes found in popular hand-held media and
cellular devices:
• USB Battery Charging Specification BC1.2
• Chinese Telecommunications Industry Standard YD/T 1591-2009
• Divider Mode
• 1.2V Mode
YD/T 1591-2009 is a subset of BC1.2 spec. supported by vast majority of devices that implement USB changing.
Divider and 1.2V charging schemes are supported in devices from specific yet popular device makers.
BC1.2 lists three different port types as listed below.
• Standard Downstream Port (SDP)
• Charging Downstream Port (CDP)
• Dedicated Charging Port (DCP)
BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable
equipment, under this definition CDP and DCP are defined as charging ports
Table 1 shows the differences between these ports.
Table 1. Operating Modes
PORT TYPE
SUPPORT USB
2.0 COMMUNICATION
MAX. ALLOWABLE CURRENT
DRAW BY PORTABLE DEVICE (A)
SDP (USB 2.0)
Yes
0.5
SDP (USB 3.0)
Yes
0.9
CDP
Yes
1.5
DCP
No
1.5
Standard Downstream Port (SDP) USB 2.0/USB 3.0
An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per
port. USB 2.0/3.0 communications is supported, and the host controller must be active to allow charging.
TPS2544 supports SDP mode in system power state S0 when system is completely powered ON and fully
operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device
truth table.
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Charging Downstream Port (CDP)
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5A per port. It provides power and
meets USB 2.0 requirements for device enumeration. USB 2.0 communications is supported, and the host
controller must be active to allow charging. What separates a CDP from an SDP is the host-charge handshaking
logic that identifies this port as a CDP. A CDP is identifiable by a compliant BC1.2 client device and allows for
additional current draw by the client device.
The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal
0.6V output on its D+ line and reads the voltage input on its D- line. The portable device concludes it is
connected to an SDP if the voltage is less than the nominal data detect voltage of 0.3V. The portable device
concludes that it is connected to a Charging Port if the D- voltage is greater than the nominal data detect voltage
of 0.3V and optionally less than 0.8V.
The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The
portable device outputs a nominal 0.6V output on its D- line and reads the voltage input on its D+ line. The
portable device concludes it is connected to a CDP if the data line being read remains less than the nominal data
detect voltage of 0.3V. The portable device concludes it is connected to a DCP if the data line being read is
greater than the nominal data detect voltage of 0.3V.
TPS2544 supports CDP mode in system power state S0 when system is completely powered ON and fully
operational. For more details on control pin (CTL1-CTL3) settings to program this state please refer to device
truth table.
Dedicated Charging Port (DCP)
A DCP only provides power but does not support data connection to an upstream port. As shown in following
sections, a DCP is identified by the electrical characteristics of its data lines. The TPS2544 emulates DCP in two
charging states, namely DCP Forced and DCP Auto as shown in Figure 32. In DCP Forced state the device will
support one of the two DCP charging schemes, namely Divider1 or Shorted. In the DCP Auto state, the device
charge detection state machine is activated to selectively implement charging schemes involved with the
Shorted, Divider1, Divider2, and 1.2V modes. Shorted DCP mode complies with BC1.2 and Chinese
Telecommunications Industry Standard YD/T 1591-2009, while the Divider and 1.2V modes are employed to
charge devices that do not comply with BC1.2 DCP standard.
DCP BC1.2 and YD/T 1591-2009
Both standards define that the D+ and D- data lines should be shorted together with a maximum series
impedance of 200 Ω. This is shown in Figure 25.
TPS2546
D- Out
D1.2V
2.7V
CDP
Detect
Auto
Detect
D+
USB
Connector
2.0V
<200Ÿ
USB Host/Hub
VBUS
GND
D+ Out
Figure 25. DCP Supporting BC1.2/YD/T 1591-2009
DCP Divider Charging Scheme
There are two Divider charging scheme supported by the device, Divider1 and Divider2 as shown in Figure 26
and Figure 27. In Divider1 charging scheme the device applies 2.0V and 2.7V to D+ and D- data line
respectively. This is reversed in Divider2 mode.
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TPS2546
D- Out
VBUS
USB Host/Hub
2.7V
2.0V
CDP
Detect
USB
Connector
1.2V
<200Ÿ
DAuto
Detect
D+
GND
D+ Out
Figure 26. DCP Divider1 Charging Scheme
D- Out
TPS2546
VBUS
USB Host/Hub
2.0V
2.7V
CDP
Detect
USB
Connector
1.2V
<200Ÿ
DAuto
Detect
D+
GND
D+ Out
Figure 27. Divider2 Charging Scheme
DCP 1.2V Charging Scheme
1.2V charging scheme is used by some handheld devices to enable fast charging at 2.0A. TPS2544 supports this
scheme in the DCP-Auto mode before the device enters BC1.2 shorted mode. To simulate this charging scheme
D+/D- lines are shorted and pulled-up to 1.2V for fixed duration then device moves to DCP shorted mode as
defined in BC1.2 spec. This is shown inFigure 28
D- Out
TPS2546
VBUS
USB Host/Hub
2.0V
2.7V
CDP
Detect
USB
Connector
1.2V
<200Ÿ
DAuto
Detect
D+
GND
D+ Out
Figure 28. DCP 1.2V Charging Scheme
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DCP Auto Mode
As mentioned above the TPS2544 integrates an auto-detect state machine that supports all the above DCP
charging schemes. It starts in Divider1 scheme, however if a BC1.2 or YD/T 1591-2009 compliant device is
attached, the TPS2544 responds by discharging OUT, turning back on the power switch and operating in 1.2V
mode briefly and then moving to BC1.2 DCP mode. It then stays in that mode until the device releases the data
line, in which case it goes back to Divider1 scheme. When a Divider1 compliant device is attached the TPS2544
will stay in Divider1 state.
Also, the TPS2544 will automatically switch between the Divider1 and Divider2 schemes based on charging
current drawn by the connected device. Initially the device will set the data lines to Divider1 scheme. If charging
current of >750mA is measured by the TPS2544 it switches to Divider2 scheme and test to see if the peripheral
device will still charge at a high current. If it does then it stays in Divider2 scheme otherwise it will revert to
Divider1 scheme
TPS2546
To USB 2.0 Host
DCP Auto
BC1.2 CDP
D-
BC1.2 DCP/
1.2V Mode
D+
From Charging
Peripheral
Divider1/2
Controlled by CTL pins
settings
Figure 29. DCP Auto Mode
DCP Forced Shorted / DCP Forced Divider1
In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider1) as
commanded by its control pin setting per device truth table.
High-Bandwidth Data Line Switch
The TPS2544 passes the D+ and D- data lines through the device to enable monitoring and handshaking while
supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device
without corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes.
The EN input also needs to be at logic High for the data line switches to be enabled.
NOTE
1. While in CDP mode, the data switches are ON even while CDP handshaking is occurring.
2. The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode. They are not
automatically turned off if the power switch (IN to OUT) is in current limit.
3. The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the super speed
differential pairs must be routed directly to the USB connector without passing through the TPS2544.
4. Data switches are OFF during OUT (VBUS) discharge
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Device Operation
Please refer to the simplified device state diagram in Figure 30. Power-on-reset (POR) holds device in initial
state while output is held in discharge mode. Any POR event will take the device back to initial state. After POR
clears, device goes to the next state depending on the CTL lines as shown in Figure 30.
Reset
DCP_Auto
DCP_SHORT/
DCP_DIVIDER
Sample
CTL Pins
DCP Forced
(DCP Shorted or
Divider 1)
DCH/SDP/
CDP
DCH
Done
DCH
DCP_SHT/
DCP_DIV
DCP_Auto
Discharge
(2s)
SDP2
(1110)
CDP
(1111)
DCH/SDP/
CDP
SDP1
(110X/
010X)
Not SDP1
DCP Auto
(Shorted/1.2V Pull-Up/
Divider 1/Divider 2)
SDP1
Note:
1)All shaded boxes are device charging modes
2) See below table for CTL settings corresponding to
flow line conditions
Not CDP
Or SDP2
CDP
CDP
(1111)
SDP2
Device Control Pins
SDP2
(1110)
Not SDP2
Or CDP
Flow Line Condition
DCH (Discharge)
CDP
SDP2
(No Discharge from/to
CDP)
SDP1
(Discharge from/to any
charging state including
CDP)
DCP_SHORT
DCP_DIVIDER
DCP_Auto
CTL1 CTL2 CTL3 ILIM_SEL
0
0
0
X
1
1
1
1
1
1
1
1
1
0
0
X
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
X
X
X
X
X
Figure 30. TPS2544 Charging States
Output Discharge
To allow a charging port to renegotiate current with a portable device, TPS2544 uses the OUT discharge
function. It proceeds by turning off the power switch while discharging OUT, then turning back on the power
switch to reassert the OUT voltage. This discharge function is automatically applied as shown in device state
diagram.
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Wake on USB Feature (Mouse/Keyboard Wake Feature)
USB 2.0 Background Information
The TPS2544 data lines interface with USB 2.0 devices. USB 2.0 defines three types of devices according to
data rate. These devices and their characteristics relevant to TPS2544 Wake on USB operation are shown below
Low-speed USB devices
• 1.5 Mb/s
• Wired mice and keyboards are examples
• No devices that need battery charging
• All signaling performed at 2.0V and 0.8V hi/lo logic levels
• D- high to signal connect and when placed into suspend
• D- high when not transmitting data packets
Full-speed USB devices
• 12 Mb/s
• Wireless mice and keyboards are examples
• Legacy phones and music players are examples
• Some legacy devices that need battery charging
• All signaling performed at 2.0V and 0.8V hi/lo logic levels
• D+ high to signal connect and when placed into suspend
• D+ high when not transmitting data packets
High-speed USB devices
• 480 Mb/s
• Tablets, phones and music players are examples
• Many devices that need battery charging
• Connect and suspend signaling performed at 2.0V and 0.8V hi/lo logic levels
• Data packet signaling performed a logic levels below 0.8V
• D+ high to signal connect and when placed into suspend (same as a full-speed device)
• D+ and D- low when not transmitting data packets
Wake On USB
Wake on USB is the ability of a wake configured USB device to wake a computer system from its S3 sleep state
back to its S0 working state. Wake on USB requires the data lines to be connected to the system USB host
before the system is placed into its S3 sleep state and remain continuously connected until they are used to
wake the system.
The TPS2544 supports low and high speed HID (human interface device like mouse/key board) wake function.
There are two scenarios under which wake on mouse are supported by the TPS2544. The specific CTL pin
changes that the TPS2544 will override are shown below. The information is presented as CTL1, CTL2, CTL3.
The ILIM_SEL pin plays no role
1. 111 (CDP/SDP2) to 011 (DCP-Auto)
2. 010 (SDP1) to 011 (DCP-Auto)
Note that the 110 (SDP1) to 011 (DCP-Auto) transition is not supported. This is done for practical reasons since
the transition involves changes to two CTL pins. Depending on which CTL pin changes first, the device will see
either a temporary 111 or 010 command. The 010 command is safe but the 111 command will cause an OUT
discharge as the TPS2544 will instead proceed to the 111 state.
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USB Slow-Speed / Full-Speed Device Recognition
TPS2544 is capable of detecting LS or FS device attachment when TPS2544 is in SDP or CDP mode. Per USB
spec when no device is attached, the D+ and D- lines are near ground level. When a low speed compliant device
is attached to the TPS2544 charging port, D- line will be pulled high in its idle state (mouse/keyboard not
activated). However when a FS device is attached the opposite is true in its idle state, i.e. D+ is pulled high and
D- remains at ground level.
TPS2544 monitors both D+ and D- lines while CTL pin settings are in CDP or SDP mode to detect LS or FS HID
device attachment. To support HID sleep wake, TPS2544 must first determine that it is attached to a LS or FS
device when system is in S0 power state. TPS2544 does this as described above. While supporting a LS HID
wake is straight forward, supporting FS HID requires making a distinction between a FS and a HS device. This is
because a high speed device will always present itself initially as a full speed device (by a 1.5K pull up resistor
on D+). The negotiation for high speed then makes the distinction whereby the 1.5K pull up resistor gets
removed.
TPS2544 handles the distinction between a FS and HS device at connect by memorizing if the D+ line goes low
after connect. A HS device after connect will always undergo negotiation for HS which will require the 1.5KΩ
resistor pull-up on D+ to be removed. To memorize a FS device, TPS2544 requires the device to remain
connected for at least 60 sec while system is in S0 mode before placing it in sleep or S3 mode. If system is
placed in sleep mode earlier than the 60 sec window, a FS device may not get recognized and hence could fail
to wake system from S3.This requirement does not apply for LS device.
No CTL Pin Timing Requirement After Wake Event and Transition from S3 to S0
Unlike the TPS2543, there is no CTL pin timing requirement for the TPS2544 when the wake configured USB
device wakes the system from S3 back to S0. The TPS2543 requires the CTL pins to transition from the DCPAuto setting back to the SDP/CDP setting within 64ms of the attached USB device signaling a wake event (e.g.
mouse clicked or keyboard key pressed). No such timing condition exists for the TPS2544.
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Device Truth Table (TT)
Device TT lists all valid bias combinations for the three control pins CTL1-3 and ILIM_SEL pin and their
corresponding charging mode. It is important to note that the TT purposely omits matching charging modes of the
TPS2544 with global power states (S0-S5) as device is agnostic to system power states. The TPS2544 monitors
its CTL inputs and will transition to whatever charging state it is commanded to go to (except when LS/FS HID
device is detected). For example if sleep charging is desired when system is in standby or hibernate state then
user must set TPS2544 CTL pins to correspond to DCP_Auto charging mode per below table. When system is
put back to operation mode then set control pins to correspond to SDP or CDP mode and so on.
Table 2. Truth Table
CTL1
CTL2
CTL3
ILIM_SEL
MODE
CURRENT
LIMIT
SETTING
0
0
0
0
Discharge
NA
0
0
0
1
Discharge
NA
0
X
1
X
DCP_Auto
ILIM_HI
0
1
0
0
SDP1
ILIM_LO
0
1
0
1
SDP1
ILIM_HI
0
1
1
0
DCP_Auto
ILIM_HI
Data Lines Disconnected
0
1
1
1
DCP_Auto
ILIM_HI
Data Lines Disconnected
1
0
0
0
DCP _Shorted
ILIM_LO
1
0
0
1
DCP_Shorted
ILIM_HI
1
0
1
0
DCP / Divider1
ILIM_LO
1
0
1
1
DCP / Divider1
ILIM_HI
1
1
0
0
SDP1
ILIM_LO
1
1
0
1
SDP1
ILIM_HI
1
1
1
0
SDP2 (1)
ILIM_LO
1
1
1
1
CDP (1)
ILIM_HI
(1)
COMMENT
OUT held low
Data Lines Disconnected
Data Lines connected
Device Forced to stay in DCP BC1.2 charging mode
Device Forced to stay in DCP Divider1 Charging Mode
Data Lines Connected
Data Lines Connected
No OUT discharge when changing between 1111 and 1110.
Table 3 can be used as an aid to program the TPS2544 per system states however not restricted to below
settings only.
Table 3. Control Pin Settings Matched to System Power States
SYSTEM
GLOBAL
POWER
STATE
TPS2544 CHARGING MODE
CTL1
CTL2
CTL3
ILIM_SEL
CURRENT LIMIT
SETTING
S0
SDP1
1
1
0
1 or 0
ILIM_HI / ILIM_LO
S0
SDP2, no discharge to / from CDP
1
1
1
0
ILIM_LO
S0
CDP
1
1
1
1
ILIM_HI
ILIM_HI
S3/S4/S5
Auto mode
0
0
1
0
S3
Auto mode, keyboard/mouse wake-up
0
1
1
0
ILIM_HI
S3
SDP1, keyboard/mouse wake-up
0
1
0
1 or 0
ILIM_HI / ILIM_LO
CDP/SDP Auto Switch
TPS2544 is equipped with a CDP/SDP auto-switch feature to support some popular phones in the market that
are not compliant to the BC1.2 specification, as they fail to establish data connection in CDP mode. These
phones use primary detection (used to distinguish between an SDP and different types of Charging Ports) to only
identify ports as SDP (data / no charge) or DCP (no data / charge). They do not recognize CDP (data /charge)
ports. When connected to a CDP port, these phones classify the port as a DCP and will only charge. Since
charging ports are configured as CDP when the computer is in S0, users do not get the expected data
connection. See Figure 39
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Primary Detection
D+
Device never
signals connect
and enumerates.
Data connection
LOST!
DVbus
Vbus Current
Device only pulls
charging current
Figure 31. CDP/SDP Auto
To remedy this problem TPS2544 employs a CDP/SDP Auto Switch scheme to ensure these BC1.2 noncompliant phones will establish data connection by following below steps:
• The TPS2544 will determine when a non-compliant phone has wrongly classified a CDP port as a DCP port
and has not made a data connection
• The TPS2544 will then automatically do a OUT (VBUS) discharge and reconfigure the port as an SDP
• This allows the phone to discover it is now connected to an SDP and establish a data connection
• The TPS2544 will then switch automatically back to CDP without doing an OUT (VBUS) discharge
• The phone will continue to operate like it is connected to a SDP since OUT (VBUS) was not interrupted
• The port is now ready in CDP if a new device is attached
Over-Current Protection
When an over-current condition is detected, the device maintains a constant output current and reduces the
output voltage accordingly. Two possible overload conditions can occur. In the first condition, the output has
been shorted before the device is enabled or before VIN has been applied. The TPS2544 senses the short and
immediately switches into a constant-current output. In the second condition, a short or an overload occurs while
the device is enabled. At the instant the overload occurs, high currents may flow for nominally one to two
microseconds before the current-limit circuit can react. The device operates in constant-current mode after the
current-limit circuit has responded. Complete shutdown occurs only if the fault is present long enough to activate
thermal limiting. The device will remain off until the junction temperature cools approximately 20°C and will then
re-start. The device will continue to cycle on/off until the over-current condition is removed.
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TPS2544
SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
Current-Limit Settings
The TPS2544 has two independent current limit settings that are each programmed externally with a resistor.
The ILIM_HI setting is programmed with RILIM_HI connected between ILIM_HI and GND. The ILIM_LO setting is
programmed with RILIM_LO connected between ILIM_LO and GND. Consult the Device Truth Table (Table 2) to
see when each current limit is used. Both settings have the same relation between the current limit and the
programming resistor.
RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following condition is met:
• ILIM_SEL is always set high
The following equation programs the typical current limit:
50,250
IOS_typ (mA) =
RILIM_XX (kΩ)
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.
TYPICAL CURRENT LIMIT SETTING
vs
PROGRAMMING RESISTOR
3500
Full RILIM_XX Range
OUT Short Circuit Current Limit (mA)
3000
2500
2000
1500
1000
500
0
0
80
160 240 320 400 480 560 640 720
Current-Limit Programming Resistor (kΩ)
800
G018
Figure 32.
24
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TPS2544
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SLVSBU8A – FEBRUARY 2013 – REVISED FEBRUARY 2013
Many applications require that the current limit meet specific tolerance limits. When designing to these tolerance
limits, both the tolerance of the TPS2544 current limit and the tolerance of the external programming resistor
must be taken into account. The following equations approximate the TPS2544 minimum / maximum current
limits to within a few mA and are appropriate for design purposes. The equations do not constitute part of TI’s
published device specifications for purposes of TI’s product warranty. These equations assume an ideal - no
variation - external programming resistor. To take resistor tolerance into account, first determine the minimum /
maximum resistor values based on its tolerance specifications and use these values in the equations. Because of
the inverse relation between the current limit and the programming resistor, use the maximum resistor value in
the IOS_min equation and the minimum resistor value in the IOS_max equation.
45,271
IOS_min (mA) =
- 30
(RILIM_XX (kΩ))0.98437
(2)
IOS_max (mA) =
55,325
(RILIM_XX (kΩ))1.0139
+ 30
(3)
CURRENT LIMIT SETTING
vs
PROGRAMMING RESISTOR
CURRENT LIMIT SETTING
vs
PROGRAMMING RESISTOR
600
3500
500
OUT Short Circuit Current Limit (mA)
3000
OUT Short Circuit Current Limit (mA)
Upper RILIM_XX Range
Min IOS
Typ IOS
Max IOS
2500
2000
1500
1000
Min IOS
Typ IOS
Max IOS
400
300
200
100
500
Lower RILIM_XX Range
0
0
10
20
30
40
50
60
70
80
Current-Limit Programming Resistor (kΩ)
90
100
0
100 150 200 250 300 350 400 450 500 550 600 650 700 750
Current-Limit Programming Resistor (kΩ)
G019
Figure 33.
G020
Figure 34.
The traces routing the RILIM_XX resistors should be a sufficiently low resistance as to not affect the current-limit
accuracy. The ground connection for the RILIM_XX resistors is also very important. The resistors need to reference
back to the TPS2544 GND pin. Follow normal board layout practices to ensure that current flow from other parts
of the board does not impact the ground potential between the resistors and the TPS2544 GND pin.
FAULT Response
The FAULT open-drain output is asserted (active low) during an over-temperature or current limit condition. The
output remains asserted until the fault condition is removed. The TPS2544 is designed to eliminate false FAULT
reporting by using an internal deglitch circuit for current limit conditions without the need for external circuitry.
This ensures that FAULT is not accidentally asserted due to normal operation such as starting into a heavy
capacitive load. Over-temperature conditions are not deglitched and assert the FAULT signal immediately.
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Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turnon threshold. Built-in hysteresis prevents unwanted oscillations on the output due to input voltage drop from large
current surges.
Thermal Sense
The TPS2544 protects itself with two independent thermal sensing circuits that monitor the operating temperature
of the power distribution switch and disables operation if the temperature exceeds recommended operating
conditions. The device operates in constant-current mode during an over-current condition, which increases the
voltage drop across power switch. The power dissipation in the package is proportional to the voltage drop
across the power switch, so the junction temperature rises during an over-current condition. The first thermal
sensor turns off the power switch when the die temperature exceeds 135°C and the part is in current limit. The
second thermal sensor turns off the power switch when the die temperature exceeds 155°C regardless of
whether the power switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on
after the device has cooled by approximately 20°C. The switch continues to cycle off and on until the fault is
removed. The open-drain false reporting output FAULT is asserted (active low) during an over-temperature
shutdown condition.
spacer
REVISION HISTORY
Changes from Original (February 2013) to Revision A
•
26
Page
Changed the device From: Preview To: Production ............................................................................................................. 1
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS2544RTER
ACTIVE
WQFN
RTE
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2544
TPS2544RTET
ACTIVE
WQFN
RTE
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2544
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS2544RTER
WQFN
RTE
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS2544RTET
WQFN
RTE
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2544RTER
WQFN
RTE
16
3000
367.0
367.0
35.0
TPS2544RTET
WQFN
RTE
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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