PHILIPS HEF4011BF

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011B
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4011B
gates
Quadruple 2-input NAND gate
DESCRIPTION
The HEF4011B provides the positive quadruple 2-input
NAND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4011BP(N):
14-lead DIL; plastic
(SOT27-1)
HEF4011BD(F):
14-lead DIL; ceramic (cerdip)
(SOT73)
Fig.1 Functional diagram.
HEF4011BT(D):
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4011B
gates
Quadruple 2-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
Propagation delays
In → On
Output transition times
HIGH to LOW
LOW to HIGH
5
TYPICAL EXTRAPOLATION
FORMULA
TYP
MAX
55
110
ns
28 ns + (0,55 ns/pF) CL
25
45
ns
14 ns + (0,23 ns/pF) CL
15
20
35
ns
12 ns + (0,16 ns/pF) CL
5
60
120
ns
10 ns + (1,0 ns/pF) CL
10
tPHL; tPLH
30
60
ns
9 ns + (0,42 ns/pF) CL
15
20
40
ns
6 ns + (0,28 ns/pF) CL
5
60
120
ns
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
10
tTHL
10
tTLH
15
VDD
V
Dynamic power
SYMBOL
5
10 ns + (1,0 ns/pF) CL
TYPICAL FORMULA FOR P (µW)
1300 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
dissipation per
10
6000 fi + ∑ (foCL) ×
package (P)
15
20 100 fi + ∑ (foCL) ×
VDD2
VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3