GD25Q41BxIGx (Uniform sector dual and quad serial flash)

GD25Q41B
DATASHEET
48 - 1
Rev.1.0
Uniform Sector
Dual and Quad Serial
Flash
GD25Q41B
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Contents
1.
FEATURES .........................................................................................................................................................4
2.
GENERAL DESCRIPTION ................................................................................................................................5
3.
MEMORY ORGANIZATION...............................................................................................................................77
4.
DEVICE OPERATION ........................................................................................................................................88
5.
DATA PROTECTION..........................................................................................................................................9
6.
STATUS REGISTER.........................................................................................................................................11
11
7.
COMMANDS DESCRIPTION..........................................................................................................................13
13
7.1.
WRITE ENABLE (WREN) (06H)................................................................................................................................ 16
16
7.2.
WRITE DISABLE (WRDI) (04H) ................................................................................................................................ 16
16
7.3.
WRITE ENABLE FOR VOLATILE STATUS REGISTER (50H) ................................................................................................. 16
16
7.4.
READ STATUS REGISTER (RDSR) (05H OR 35H) .......................................................................................................... 17
17
7.5.
WRITE STATUS REGISTER (WRSR) (01H) ................................................................................................................... 17
17
7.6.
WRITE STATUS REGISTER (WRSR) (31H) ................................................................................................................... 18
18
7.7.
READ DATA BYTES (READ) (03H)............................................................................................................................. 19
19
7.8.
READ DATA BYTES AT HIGHER SPEED (FAST READ) (0BH).............................................................................................. 19
19
7.9.
DUAL OUTPUT FAST READ (3BH).............................................................................................................................. 20
20
7.10.
QUAD OUTPUT FAST READ (6BH) ............................................................................................................................. 20
20
7.11.
DUAL I/O FAST READ (BBH) .................................................................................................................................... 21
21
7.12.
QUAD I/O FAST READ (EBH) ................................................................................................................................... 22
22
7.13.
QUAD I/O WORD FAST READ (E7H) ......................................................................................................................... 24
24
7.14.
SET BURST WITH WRAP (77H) ................................................................................................................................. 25
25
7.15.
PAGE PROGRAM (PP) (02H).................................................................................................................................... 26
26
7.16.
SECTOR ERASE (SE) (20H)....................................................................................................................................... 27
27
7.17.
32KB BLOCK ERASE (BE) (52H) ............................................................................................................................... 27
27
7.18.
64KB BLOCK ERASE (BE) (D8H)............................................................................................................................... 28
28
7.19.
CHIP ERASE (CE) (60/C7H)..................................................................................................................................... 29
29
7.20.
DEEP POWER-DOWN (DP) (B9H)............................................................................................................................. 29
29
7.21.
RELEASE FROM DEEP POWER-DOWN OR HIGH PERFORMANCE MODE AND READ DEVICE ID (RDI) (ABH).............................. 30
30
7.22.
READ MANUFACTURE ID/ DEVICE ID (REMS) (90H) ................................................................................................... 31
31
7.23.
READ MANUFACTURE ID/ DEVICE ID DUAL I/O (92H) ................................................................................................. 32
32
7.24.
READ MANUFACTURE ID/ DEVICE ID QUAD I/O (94H)................................................................................................. 33
33
7.25.
READ IDENTIFICATION (RDID) (9FH) ......................................................................................................................... 33
33
7.26.
HIGH PERFORMANCE MODE (HPM) (A3H) ................................................................................................................ 34
34
7.27.
ERASE SECURITY REGISTERS (44H) ............................................................................................................................ 35
35
7.28.
PROGRAM SECURITY REGISTERS (42H)....................................................................................................................... 35
35
7.29.
READ SECURITY REGISTERS (48H) ............................................................................................................................. 36
36
7.30.
CONTINUOUS READ MODE RESET (CRMR) (FFH)........................................................................................................ 37
37
7.31.
PROGRAM/ERASE SUSPEND (PES) (75H) ................................................................................................................... 38
38
2
48 - 2
Rev.1.0
GD25Q41BxIGx Uniform sector dual and quad serial flash
Uniform Sector
Dual and Quad Serial Flash
7.32.
GD25Q41B
PROGRAM/ERASE RESUME (PER) (7AH) ................................................................................................................... 38
38
ELECTRICAL CHARACTERISTICS ..............................................................................................................39
39
8.
8.1.
POWER-ON TIMING ........................................................................................................................................... 39
39
8.2.
INITIAL DELIVERY STATE ..................................................................................................................................... 39
36
39
35
8.3.
DATA RETENTION AND ENDURANCE ................................................................................................................. 39
39
8.4.
LATCH UP CHARACTERISTICS ............................................................................................................................. 39
39
8.5.
ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 40
40
8.6.
CAPACITANCE MEASUREMENT CONDITIONS .................................................................................................... 40
40
8.7.
41
DC CHARACTERISTICS......................................................................................................................................... 41
8.8.
42
AC CHARACTERISTICS......................................................................................................................................... 42
ORDERING INFORMATION............................................................................................................................44
44
9.
10.
PACKAGE INFORMATION .........................................................................................................................45
45
10.1.
PACKAGE SOP8 150MIL ........................................................................................................................................ 45
45
10.2.
PACKAGE SOP8 208MIL ........................................................................................................................................ 46
46
10.3.
PACKAGE TSSOP8 173MIL..................................................................................................................................... 47
10.4.
PACKAGE USON8 (3*2MM).................................................................................................................................... 48
48
11.
REVISION HISTORY....................................................................................................................................49
48 3- 3
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
1. FEATURES
�
4M-bit Serial Flash
� Program/Erase
Speed
-512K-byte
-Page Program time:0.35ms typical
-256 bytes per programmable page
-Sector Erase time:50ms typical
-Block Erase time: 0.18/0.25s typical
�
Standard, Dual, Quad SPI
-Chip Erase time:1.5 s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI:SCLK, CS#, IO0, IO1, WP#, HOLD#
�
-Quad SPI:SCLK, CS#, IO0, IO1, IO2, IO3
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64K-byte
�
High Speed Clock Frequency
-104MHz for fast read with 30PF load
� Low
Power Consumption
-Dual I/O Data transfer up to 208Mbits/s
-20mA maximum active current
-Quad I/O Data transfer up to 416Mbits/s
-5uA maximum power down current
� Software/Hardware
Write Protection
�
-Write protect all/portion of memory via software
Single Power Supply Voltage
-Full voltage range:2.7~3.6V
-Enable/Disable protection with WP# Pin
-Top or Bottom, Sector or Block selection
�
�
Minimum 100,000 Program/Erase Cycles
Advanced security Features
-Power Supply Lock-Down
-3*512-Byte Security Registers With OTP Locks
- Volatile and Non-volatile Status Register Bits
4
48 - 4
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
2. GENERAL DESCRIPTION
The GD25Q41B Serial flash supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and
I/O3 (HOLD#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz for Dual
Output & Dual I/O read command, and 416MHz for Quad output & Quad I/O read command.
CONNECTION DIAGRAM
8
VCC
7
HOLD#
8
VCC
CS#
1
7
HOLD#
SO
2
3
6
SCLK
WP# 3
6 SCLK
4
5
SI
VSS 4
5
CS#
1
SO
2
WP#
VSS
Top View
Top View
SI
8–LEAD USON
8–LEAD SOP/TSSOP
PIN DESCRIPTION
Pin Name
I/O
Description
CS#
I
Chip Select Input
SO (IO1)
I/O
Data Output (Data Input Output 1)
WP# (IO2)
I/O
Write Protect Input (Data Input Output 2)
Ground
VSS
SI (IO0)
I/O
Data Input (Data Input Output 0)
SCLK
I
Serial Clock Input
HOLD# (IO3)
I/O
Hold Input (Data Input Output 3)
VCC
Power Supply
5
48 - 5
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Write Protect Logic
and Row Decode
Status
Register
High Voltage
Generators
Page Address
Latch/Counter
Flash
Memory
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
6
48 - 6
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
3. MEMORY ORGANIZATION
GD25Q41B
Each device has
Each block has
Each sector has
Each page has
512K
64/32K
4K
256
bytes
2K
256/128
16
-
pages
128
16/8
-
-
sectors
8/16
-
-
-
blocks
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25Q41B 64K Bytes Block Sector Architecture
Block
7
6
……
……
2
1
0
Sector
Address range
127
07F000H
07FFFFH
……
……
……
112
070000H
070FFFH
111
06F000H
06FFFFH
……
……
……
96
060000H
060FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
7
48 - 7
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q41B feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial
Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q41B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q41B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,
“Quad I/O Word Fast Read”, ”Quad Page Program” (6BH, EBH, E7H, 32H). These commands allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins
become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require
the non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
8
48 - 8
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
5. DATA PROTECTION
The GD25Q41B provides the following data protection methods:
�
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will
return to reset by the following situation:
-Power-Up
-Write Disable (WRDI)
-Write Status Register (WRSR)
-Page Program (PP)
-Sector Erase (SE)
-Block Erase (BE)
-Chip Erase (CE)
-Erase Security Register / Program Security Register
�
Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
�
Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
�
Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep
Power-Down Mode command.
Table1.0. GD25Q41B Protected area size
Status Register Content
(CMP=0)
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
7
070000H-07FFFFH
64KB
Upper 1/8
0
0
0
1
0
6 and 7
060000H-07FFFFH
128KB
Upper 1/4
0
0
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/8
0
1
0
1
0
0 and 1
000000H-01FFFFH
128KB
Lower 1/4
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
X
1
X
X
0 to 7
000000H-07FFFFH
512KB
ALL
1
0
0
0
1
7
07F000H-07FFFFH
4KB
Top Block
1
0
0
1
0
7
07E000H-07FFFFH
8KB
Top Block
1
0
0
1
1
7
07C000H-07FFFFH
16KB
Top Block
1
0
1
0
X
7
078000H-07FFFFH
32KB
Top Block
1
0
1
1
0
7
078000H-07FFFFH
32KB
Top Block
1
1
0
0
1
0
000000H-000FFFH
4KB
Bottom Block
1
1
0
1
0
0
000000H-001FFFH
8KB
Bottom Block
1
1
0
1
1
0
000000H-003FFFH
16KB
Bottom Block
1
1
1
0
X
0
000000H-007FFFH
32KB
Bottom Block
1
1
1
1
0
0
000000H-007FFFH
32KB
Bottom Block
1
X
1
1
1
0 to 7
000000H-07FFFFH
512KB
ALL
9
48 - 9
Rev.1.0
GD25Q41BxIGx
Uniform SectorUniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Table1.0(a). GD25Q41B Protected area size (CMP=1)
Status Register Content
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
X
X
0
0
0
0 to 7
000000H-07FFFFH
512KB
ALL
0
0
0
0
1
0 to 6
000000H-06FFFFH
448KB
Lower 7/8
0
0
0
1
0
0 to 5
000000H-05FFFFH
384KB
Lower 3/4
0
0
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
1
0
0
1
1 to 7
010000H-07FFFFH
448KB
Upper 7/8
0
1
0
1
0
2 to 7
020000H-07FFFFH
384KB
Upper 3/4
0
1
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
X
1
X
X
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 7
000000H-07EFFFH
508KB
Lower 127/128
1
0
0
1
0
0 to 7
000000H-07DFFFH
504KB
Lower 63/64
1
0
0
1
1
0 to 7
000000H-07BFFFH
496KB
Lower 31/32
1
0
1
0
X
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
0
1
1
0
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
1
0
0
1
0 to 7
001000H-07FFFFH
508KB
Upper 127/128
1
1
0
1
0
0 to 7
002000H-07FFFFH
504KB
Upper 63/64
1
1
0
1
1
0 to 7
004000H-07FFFFH
496KB
Upper 31/32
1
1
1
0
X
0 to 7
008000H-07FFFFH
480KB
Upper 15/16
1
1
1
1
0
0 to 7
008000H-07FFFFH
480KB
Upper 15/16
1
X
1
1
1
NONE
NONE
NONE
NONE
10
48 - 10
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
6. STATUS REGISTER
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
HPF
QE
SRP1
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP4
BP3
BP2
BP1
BP0
WEL
WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress.
When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0,
means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile (Default Value is 0). They define the size of the
area to be software protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as
defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands.
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Chip Erase (CE) command is executed, if the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to “None
protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time
programmable protection.
SRP1
SRP0
#WP
Status Register
0
0
X
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
X
Power Supply Lock-Down(1)
1
1
X
One Time Program(2)
Description
WP# pin has no control. The Status Register can be written to
after a Write Enable command, WEL=1.(Default)
When WP# pin is low the Status Register locked and can not
be written to.
When WP# pin is high the Status Register is unlocked and
can be written to after a Write Enable command, WEL=1.
Status Register is protected and can not be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and can not be
written to.
NOTE:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact GigaDevice for details.
11
48 - 11
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground).
HPF bit
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit sets to 1,
it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is not in High
Performance Mode.
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide the
write protect control and status to the Security Registers. The default state of LB3-LB1 are 0, the security registers are
unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register instruction. The LB3-LB1 bits are One
Time Programmable, once its set to 1, the Security Registers will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS bit
The SUS bit is read only bit in the status register (S15) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down,
power-up cycle.
12
48 - 12
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Command Name
Byte 1
Write Enable
Write Disable
Volatile SR
Write Enable
Read Status Register
06H
04H
50H
Byte 2
Byte 3
Byte 4
05H
(S7-S0)
35H
01H
31H
03H
0BH
3BH
(S15-S8)
(S7-S0)
(S15-S8)
A23-A16
A23-A16
A23-A16
BBH
A23-A8
6BH
A23-A16
EBH
A23-A0
(5)
M7-M0
A23-A0
(5)
M7-M0
dummy
Read Status Register-1
Write Status Register
Write Status Register-1
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
(8)
Fast Read
Continuous Read Reset
Page Program
Quad Page Program
FFH
02 H
32H
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
Set Burst with Wrap
20H
52H
D8H
C7/60 H
77H
Program/Erase
Suspend
75H
E7H
Byte 5
Byte 6
n-Bytes
(continuous)
(S15-S8)
(continuous)
(1)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
(3)
M7-M0
A15-A8
(D7-D0)
(6)
(D7-D0)
(4)
(continuous)
dummy
(7)
(D7-D0)
(4)
(continuous)
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(3)
(D7-D0)
dummy
dummy
(Next byte)
(D7-D0)
(2)
(D7-D0)
(2)
A7-A0
(continuous)
(continuous)
(continuous)
(continuous)
dummy
D7-D0
(D7-D0)
(D7-D0)
(4)
(continuous)
Next byte
(4)
(10)
dummy
W7-W0
13
48 - 13
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Manufacturer/
Device ID
Manufacturer/
Device ID by Dual I/O
Manufacturer/
Device ID by Quad I/O
7AH
B9H
ABH
GD25Q41B
dummy
dummy
dummy
(DID7DID0)
dummy
dummy
00H
(MID7MID0)
A23-A8
A7-A0,
M7-M0
(MID7-MID
0)
(DID7-DID
0)
(continuous)
ABH
90H
92H
(11)
(DID7DID0)
(continuous)
(continuous)
94H
A23-A0,
M7-M0
Read Identification
9FH
(M7-M0)
High Performance Mode
Erase Security
(9)
Registers
Program Security
(9)
Registers
Read Security
(9)
Registers
A3H
44H
dummy
A23-A16
dummy
(MID7MID0)
(DID7-DID0)
(JDID15JDID8)
dummy
A15-A8
42H
A23-A16
A15-A8
A7-A0
(D7-D0)
(D7-D0)
48H
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
(continuous)
(JDID7JDID0)
dummy
A7-A0
(continuous)
NOTE:
1. Write Status Register (01H)
Normally, Write Status Register (01H) is used to write both lower status register and higher status register;
However, if CS# goes up at the eighth bit of the data byte, the data byte would be written as lower byte of status
register, without changing the higher byte of status register.
2. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
3. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8
A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9
A7, A5, A3, A1, M7, M5, M3, M1
4. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
5. Quad Input Address
IO0 = A20, A16, A12, A8,
A4, A0, M4, M0
14
48
- 14
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
IO1 = A21, A17, A13, A9,
GD25Q41B
A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
6. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
8. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
9. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000b, A8-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000b, A8-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000b, A8-A0= Byte Address.
10. Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4,x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
11. Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
IO1 = (A21, A17, A13, A9, A5, A1, M5, M1, x, x, x, x, MID5, MID1, DID5, DID1, …)
IO2 = (A22, A18, A14, A10, A6, A2, M6, M2,
x, x, x, x, MID6, MID2, DID6, DID2, …)
IO3 = (A23, A19, A15, A11, A7, A3, M7, M3,
x, x, x, x, MID7, MID3, DID7, DID3, …)
Table of ID Definitions:
GD25Q41B
Operation Code
M7-M0
ID15-ID8
ID7-ID0
9FH
C8
40
13
90H
C8
12
ABH
12
15
48 - 15
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status
Register (WRSR), Program Security Register, Erase Security Register command. The Write Enable (WREN) command
sequence: CS# goes low � sending the Write Enable command � CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes low�Sending the Write Disable command �CS# goes high. The WEL bit is reset by following condition:
Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase, Chip Erase,
Program Security Register, Erase Security Register commands.
Figure 3. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
Command
04H
High-Z
7.3. Write Enable for Volatile Status Register (50H)
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change the
system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or
affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile Status Register command
must be issued prior to a Write Status Register command. The Write Enable for Volatile Status Register command will not
set the Write Enable Latch bit, it is only valid for the Write Status Register command to change the volatile Status Register
bit values.
16
48 - 16
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command(50H)
SI
SO
High-Z
7.4. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is
also possible to read the Status Register continuously. For command code “05H”, the SO will output Status Register bits
S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 5. Read Status Register Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Command
05H or 35H
High-Z
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
7
S7~S0 or S15~S8 out
6 5 4 3 2 1 0
7
MSB
MSB
7.5. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) (01H) command has no effect on S15, S10, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register
(WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction is entered by
driving CS# low, sending the instruction code “01h”, and then writing the status register data byte
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been
17
48 - 17
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB3, LB2,
LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon power off, the volatile Status
Register bit values will be lost, and the non-volatile Status Register bit values will be restored when power on again.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP3, BP2,
BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write Status
Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in
accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
Figure 6. Write Status Register Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
6
Command
SI
SO
01H
Status Register in
4
5
MSB
3
2
1
0 15 14 13 12 11 10 9
8
High-Z
7.6. Write Status Register (WRSR) (31H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it can be
accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable (WREN)
command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command (31H) has no effect on S15 and S10 of the Status Register. CS# must
be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command
is not executed. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is
completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been
executed for the device to accept the Write Status Register Instruction. Once write enabled, the instruction is entered by
driving CS# low, sending the instruction code “31h”, and then writing the status register data byte.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been
executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRP1 and LB3, LB2,
LB1 can not be changed from 1 to 0 because of the OTP protection for these bits. Upon power off, the volatile Status
Register bit values will be lost, and the non-volatile Status Register bit values will be restored when power on again.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in
accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect
(WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register (WRSR) command is
not executed once the Hardware Protected Mode is entered.
18
48 - 18
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
Figure 7. Write Status Register Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
Command
SI
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Status Register in
31H
15 14 13 12 11 10 9 8
MSB
SO
High-Z
7.7. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in during
the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a
Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 8. Read Data Bytes Sequence Diagram
CS#
SCLK
0
1
SI
SO
2
3
4
5
6
7
8
Command
03H
High-Z
9 10
28 29 30 31 32 33 34 35 36 37 38 39
24-bit address
3
23 22 21
2
1
0
MSB
MSB
7
6
5
Data Out1
4 3 2 1
Data Out2
0
7.8. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
19
48 - 19
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 9. Read Data Bytes at Higher Speed Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10
Command
SI
28 29 30 31
24-bit address
0BH
3
23 22 21
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Dummy Byte
7
6
5
4
3
2
1
0
7 6
MSB
SO
Data Out1
5 4 3 2
1
0
Data Out2
7 6 5
MSB
7.9. Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 10. Dual Output Fast Read Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
24-bit address
Command
3BH
23 22 21
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Dummy Clocks
6
SO
7.10.
4
2
0
6
4
2
0
6
Data Out2
Data Out1
7 5 3 1 7 5 3 1
MSB
MSB
7
Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1
20
48 - 20
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
and IO0. The command sequence is shown in followed Figure11. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 11. Quad Output Fast Read Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10
Command
SI(IO0)
24-bit address
6BH
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
SCLK
3
23 22 21
SO(IO1)
CS#
28 29 30 31
2
1
0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
7.11.
SI(IO0)
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
Dual I/O Fast Read (BBH)
The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input
the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in
during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The
command sequence is shown in followed Figure12. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. To ensure optimum
performance the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Dual I/O Fast Read
command.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next
Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The
command sequence is shown in followed Figure13. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first BBH command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M7-0) before issuing normal command.
21
48 - 21
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 12. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0
SCLK
1
2
3
4
5
6
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
Command
SI(IO0)
BBH
0 6
2
4
6
0
2
4 2 0 6 4 2 0
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16
A15-8
A7-0
M7-0
SO(IO1)
CS#
SCLK
8
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SI(IO0)
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
6
SO(IO1)
7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
Byte1
Byte2
Byte3
Byte4
7
Figure 13. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
A23-16
A15-8
A7-0
M7-0
CS#
SCLK
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
7.12.
Byte2
Byte3
Byte4
Quad I/O Fast Read (EBH)
The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to input the
3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each
bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0,
IO1, IO2, IO3. The command sequence is shown in followed Figure14. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit
22
48 - 22
Rev.1.0
Uniform SectorUniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
(QE) of Status Register (S9) must be set to enable for the Quad I/O Fast read command. To ensure optimum performance
the High Performance Mode (HPM) command (A3H) must be executed once, prior to the Quad I/O Fast Read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the next
Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the EBH command code. The
command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next command requires the first EBH command code, thus returning to normal operation. A “Continuous Read
Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 14. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
0
SCLK
Command
SI(IO0)
EBH
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1 Byte2
Figure 15. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)
CS#
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0 M7-0
Dummy
Byte1 Byte2
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst with
Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or disable the “Wrap
Around” feature for the following EBH commands. When “Wrap Around” is enabled, the data being accessed can be limited
to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the
command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning
boundary automatically until CS# is pulled high to terminate the command.
23
48 - 23
Rev.1.0
Uniform SectorUniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst
with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.
7.13.
Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure16. The first
byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word
Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be
executed once, prior to the Quad I/O Word Fast Read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the
next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not require the E7H command code.
The command sequence is shown in followed Figure17. If the “Continuous Read Mode” bits (M7-0) are any value other
than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous
Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.
Figure 16. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
Command
SI(IO0)
E7H
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
24
48 - 24
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
Figure 17. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)
CS#
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
SCLK
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable or disable the
“Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data being accessed can be
limited to either an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the
command, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around the beginning
boundary automatically until CS# is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the
cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The “Set Burst
with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable or disable the “Wrap Around”
operation while W6-W5 is used to specify the length of the wrap around section within a page.
7.14.
Set Burst with Wrap (77H)
The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word Fast Read”
command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low � Send Set Burst with Wrap command � Send 24
dummy bits � Send 8 bits “Wrap bits” � CS# goes high.
W6,W5
W4=0
W4=1 (default)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0, 0
Yes
8-byte
No
N/A
0, 1
Yes
16-byte
No
N/A
1, 0
Yes
32-byte
No
N/A
1, 1
Yes
64-byte
No
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and “Quad I/O
Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the
“Wrap Around” function and return to normal read operation, another Set Burst with Wrap command should be issued to set
W4=1.
25
48 - 25
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 18. Set Burst with Wrap Sequence Diagram
CS#
8
9 10 11 12 13 14 15
x
x
x
x
x
x
4
x
SO(IO1)
x
x
x
x
x
x
5
x
WP#(IO2)
x
x
x
x
x
x
6
x
HOLD#(IO3)
x
x
x
x
x
x
x
x
SCLK
0
1
2
3
4
5
6
7
Command
SI(IO0)
77H
W6-W4
7.15.
Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond the end of the current page are programmed from the start address of the same page (from the address
whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The
Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least
1 byte data on SI � CS# goes high. The command sequence is shown in Figure19. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly
within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of
the last data byte has been latched in; otherwise the Page Program command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page
Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0)
is not executed.
48 26- 26
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 19. Page Program Sequence Diagram
CS#
5
6
7
8
24-bit address
02H
23 22 21
3
2
Data Byte 1
0 7
1
MSB
6
5
4
3
2
1
2078
Command
SI
28 29 30 31 32 33 34 35 36 37 38 39
9 10
2079
4
2076
3
2077
2
2075
1
2074
0
SCLK
1
0
0
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
MSB
CS#
7
6
SCLK
Data Byte 3
Data Byte 2
SI
7
6
5
4
3
2
0 7
1
5
4
3
Data Byte 256
2
1
MSB
MSB
7.16.
6
0
5
4
3
2
MSB
Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI �
CS# goes high. The command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1.) is not executed.
Figure 20. Sector Erase Sequence Diagram
CS#
SCLK
SI
7.17.
0
1
2
3
4
5
6
7
8
Command
20H
9
29 30 31
24 Bits Address
23 22
MSB
2
1
0
32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address
inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration
of the sequence.
27
48 - 27
Rev.1.0
GD25Q41BxIGx
Uniform SectorUniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
The 32KB Block Erase command sequence: CS# goes low � sending 32KB Block Erase command � 3-byte
address on SI � CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth
bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon
as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.
Figure 21. 32KB Block Erase Sequence Diagram
CS#
SCLK
0
1
3
4
5
6
7
8
Command
SI
7.18.
2
9
29 30 31
24 Bits Address
23 22
MSB
52H
2
1
0
64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address
inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration
of the sequence.
The 64KB Block Erase command sequence: CS# goes low � sending 64KB Block Erase command � 3-byte
address on SI � CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after the eighth
bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon
as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0) bits (see Table1.) is not executed.
Figure 22. 64KB Block Erase Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
Command
D8H
9
29 30 31
24 Bits Address
23 22
MSB
28
48 - 28
2
1
0
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
7.19.
GD25Q41B
Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit The Chip Erase (CE) command is entered by
driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration
of the sequence.
The Chip Erase command sequence: CS# goes low � sending Chip Erase command � CS# goes high. The
command sequence is shown in Figure23. CS# must be driven high after the eighth bit of the command code has been
latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase
cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP4,BP3,BP2, BP1, BP0) bits are set to “None
protected”. The Chip Erase (CE) command is ignored if one or more sectors are protected.
Figure 23. Chip Erase Sequence Diagram
CS#
SCLK
0
1
2
4
5
6
7
Command
SI
7.20.
3
60H or C7H
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption mode
(the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while the device is not in
active use, since in this mode, the device ignores all Write, Program and Erase commands. Driving CS# high deselects the
device, and puts the device in the Standby Mode (if there is no internal cycle currently in progress). But this mode is not the
Deep Power-Down Mode. The Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP)
command. Once the device has entered the Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The Release from Deep
Power-Down and Read Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the Standby
Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command code on SI. CS#
must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low � sending Deep Power-Down command � CS# goes
high. The command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code has
been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it
requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-Down Mode is entered. Any Deep
Power-Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
29
48 - 29
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
Figure 24. Deep Power-Down Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
Command
SI
tDP
7
Stand-by mode Deep Power-down mode
B9H
7.21. Release from Deep Power-Down or High Performance Mode and Read
Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be
used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic
identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the
CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure25. Release from Power-Down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
c ommand are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the
CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure25. The Device ID value for the
GD25Q41B is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The
command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the same
as previously described, and shown in Figure25, except that after CS# is driven high it must remain high for a time
duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other
command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or
Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle.
Figure 25. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
t RES1
7
Command
ABH
Deep Power-down mode
30
48 - 30
Stand-by mode
Rev.1.0
Uniform Sector Uniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
Figure 26. Release Power-Down/Read Device ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
t RES2
3 Dummy Bytes
23 22
ABH
2
1
0
MSB
High-Z
MSB
7.22.
7
Device ID
5 4 3 2
6
1
0
Deep Power-down Mode Stand-by Mode
Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure27. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure 27. Read Manufacture ID/ Device ID Sequence Diagram
CS#
0
SCLK
2
3
4
5
6
7
8
9 10
Command
SI
28 29 30 31
24-bit address
90H
3
23 22 21
2
1
0
High-Z
SO
CS#
1
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
SO
7
MSB
Manufacturer ID
6 5 4 3 2 1
Device ID
0
7
6
5
4
3
2
1
0
MSB
31
48 - 31
Rev.1.0
Uniform Sector
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Uniform
Serial Flash
GD25Q41B
7.23.
Read Manufacture ID/ Device ID Dual I/O (92H)
The Read Manufacturer/Device ID Dual I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by dual I/O.
The command is initiated by driving the CS# pin low and shifting the command code “92H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure28. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure 28. Read Manufacture ID/ Device ID Dual I/O Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Command
SI(IO0)
92H
SO(IO1)
A23-16
A15-8
A7-0
M7-0
CS#
SCLK
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
MFR ID
Device ID
MFR ID
(Repeat)
Device ID
(Repeat)
MFR ID
(Repeat)
Device ID
(Repeat)
32
48 - 32
Rev.1.0
Uniform Sector
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Uniform
Serial Flash
GD25Q41B
7.24.
Read Manufacture ID/ Device ID Quad I/O (94H)
The Read Manufacturer/Device ID Quad I/O command is an alternative to the Release from Power-Down / Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by quad I/O.
The command is initiated by driving the CS# pin low and shifting the command code “94H” followed by a 24-bit
address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on the falling edge of
SCLK with most significant bit (MSB) first as shown in Figure29. If the 24-bit address is initially set to 000001H, the Device
ID will be read first.
Figure 29. Read Manufacture ID/ Device ID Quad I/O Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI(IO0)
4 0 4 0
4 0 4 0 4 0 4 0
94H
SO(IO1)
5 1 5 1 5 1 5 1
WP#(IO2)
6 2 6 2 6 2 6 2
HOLD#(IO3)
7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0
5 1 5 1
6 2 6 2
7 3 7 3
Dummy
MFR ID DID
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4 0 4 0 4 0 4 0
SO(IO1)
5 1 5 1 5 1 5 1
WP#(IO2)
6 2 6 2 6 2 6 2
HOLD#(IO3) 7 3 7 3 7 3 7 3
MFR ID DID MFR ID DID
(Repeat)(Repeat)
(Repeat)(Repeat)
7.25.
Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two
bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity
of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress,
is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be
issued while the device is in Deep Power-Down Mode.
33
48 - 33
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted in. This is
followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being
shifted out during the falling edge of Serial Clock. The command sequence is shown in Figure30. The Read Identification
(RDID) command is terminated by driving CS# to high at any time during data output. When CS# is driven high, the device
is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and
execute commands.
Figure 30. Read Identification ID Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
7
6
9FH
SI
SO
MSB
CS#
Manufacturer ID
5 4 3 2 1
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
7
SO
Memory Type ID15-ID8
6 5 4 3 2 1 0
MSB
7.26.
7
Capacity ID7-ID0
6 5 4 3 2 1
0
MSB
High Performance Mode (HPM) (A3H)
The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of
internal charge pumps so the voltages required for accessing the flash memory array are readily available. The
command sequence: CS# goes low�Sending A3H command� Sending 3-dummy byte�CS# goes high. See
Figure31. After the HPM command is executed, the device will maintain a slightly higher standby current (Icc8) than
standard SPI operation. The Release from Power-Down or HPM command (ABH) can be used to return to standard SPI
standby current (Icc1). In addition, Power-Down command (B9H) will also release the device from HPM mode back to
deep power down state.
Figure 31. High Performance Mode Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
Command
A3H
6
7
8
9
29 30 31
t HPM
3 Dummy Bytes
23 22
MSB
2
1
0
SO
High Performance Mode
34
48 - 34
Rev.1.0
Uniform Sector
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Uniform
Serial Flash
GD25Q41B
7.27.
Erase Security Registers (44H)
The GD25Q41B provides three 512-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information separately
from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low � sending Erase Security Registers command �
CS# goes high. The command sequence is shown in Figure32. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Erase Security Registers command is not executed. As soon as CS# is
driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The
Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit
(LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security
Registers will be permanently locked; the Erase Security Registers command will be ignored.
Address
Security Register #1
Security Register #2
Security Register #3
A23-16
00H
00H
00H
A15-12
0001
0010
0011
A11-9
000
000
000
A8-0
Byte Address
Byte Address
Byte Address
Figure 32. Erase Security Registers command Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
7.28.
44H
29 30 31
24 Bits Address
Command
SI
9
23 22
MSB
2
1
0
Program Security Registers (42H)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512 bytes
Security Registers data to be programmed. A Write Enable (WREN) command must previously have been executed to set
the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The Program Security
Registers command is entered by driving CS# Low, followed by the command code (42H), three address bytes and at least
one data byte on SI. As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP)
is initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check the value
of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL)
bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked. Program
Security Registers command will be ignored.
35
48 - 35
Rev.1.0
GD25Q41BxIGx
Uniform SectorUniform sector dual and quad serial flash
Dual and Quad Serial Flash
Address
Security Register #1
Security Register #2
Security Register #3
A23-16
00H
00H
00H
GD25Q41B
A15-12
0001
0010
0011
A11-9
000
000
000
A8-0
Byte Address
Byte Address
Byte Address
Figure 33. Program Security Registers command Sequence Diagram
CS#
5
6
7
8
Command
24-bit address
23 22 21
3
2
0 7
1
MSB
6
5
4
3
2
1
2079
42H
Data Byte 1
2078
SI
28 29 30 31 32 33 34 35 36 37 38 39
9 10
2077
4
2075
3
2076
2
1
0
0
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
MSB
2073
1
2074
0
SCLK
SCLK
SI
7
6
MSB
7.29.
Data Byte 3
Data Byte 2
5
4
3
2
1
0 7
6
5
4
3
2
MSB
Data Byte 256
1
0
7
6
5
4
3
2
MSB
Read Security Registers (48H)
The Read Security Registers command is similar to Fast Read command. The command i is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. Once the A8-A0 address reaches the last byte of the register (Byte 1FFH), it will reset to 000H,
the command is completed by driving CS# high.
Address
Security Register #1
Security Register #2
Security Register #3
A23-16
00H
00H
00H
A15-12
0001
0010
0011
48 36
- 36
A11-9
000
000
000
A8-0
Byte Address
Byte Address
Byte Address
Rev.1.0
GD25Q41BxIGx
Uniform Sector Uniform sector dual and quad serial flash
Dual and Quad Serial Flash
GD25Q41B
Figure 34. Read Security Registers command Sequence Diagram
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10
Command
SI
28 29 30 31
24-bit address
48H
3
23 22 21
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
7.30.
Data Out1
5 4 3 2
7 6
MSB
SO
1
0
Data Out2
7 6 5
MSB
Continuous Read Mode Reset (CRMR) (FFH)
The Dual/Quad I/O Fast Read operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce
command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the
BBH/EBH/E7H command code.
If the system controller is reset during operation it will likely send a standard SPI command, such as Read ID (9FH) or
Fast Read (0BH), to the device. Because the GD25Q41B has no hardware reset pin, so if Continuous Read Mode bits are
set to “AXH”, the GD25Q41B will not recognize any standard SPI commands. So Continuous Read Mode Reset command
will release the Continuous Read Mode from the “AXH” state and allow standard SPI command to be recognized.
Figure 35. Continuous Read Mode Reset Sequence Diagram
Mode Bit Reset for Quad/Dual I/O
CS#
0
1
2
3
4
5
6
7
SCLK
SI(IO0)
FFH
SO(IO1)
Don`t Care
WP#(IO2)
Don`t Care
HOLD#(IO3)
Don`t Care
37
48 - 37
Rev.1.0
Uniform Sector
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Uniform
Serial Flash
GD25Q41B
7.31.
Program/Erase Suspend (PES) (75H)
The Erase/Program Suspend instruction “75H”, allows the system to interrupt a sector/block erase or page program
operation and then read data from any other sector or block. The Write Status Register command (01H), Page
Program command (02H) and Erase commands (20H, 52H, D8H, C7H, 60H ) are not allowed during suspend.
Erase/Program Suspend is valid only during the sector/block erase or page program operation. A maximum of time of
“tsus” (See AC Characteristics) is required to suspend the program/erase operation.
While the Erase/Program suspend cycle is in progress, the Read Status Register command may still be accessed
for checking the status of the BUSY bit. The BUSY bit is a 1 during the Erase/Program suspend cycle and becomes
a 0 when the cycle is finished and the device is ready to accept read command. A power-off during the suspend period
will reset the device and release the suspend state. The command sequence is show in Figure36.
Figure 36. Program/Erase Suspend Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
tSUS
Command
SI
75H
High-Z
SO
Accept read command
7.32.
Program/Erase Resume (PER) (7AH)
The Program/Erase Resume command must be written to resume the sector/block erase or program operation after
a Program/Erase Suspend command. After issued the BUSY bit in the status register will be set to 1 and the sector/block
erase or program operation will completed. The Program/Erase Resume command will be ignored unless a Program/Erase
Suspend is active. The command sequence is show in Figure37.
Figure 37. Program/Erase Resume Sequence Diagram
CS#
SCLK
SI
0
1
2
3
4
5
6
7
Command
7AH
SO
Resume Erase/Program
38
48 - 38
Rev.1.0
Uniform SectorUniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
8. ELECTRICAL CHARACTERISTICS
8.1. POWER-ON TIMING
Vcc(max)
Program, Erase and Write command are ignored
Chip Selection is not allowed
Vcc(min)
VWI
tVSL
Reset
State
Read command
is allowed
Device is fully
accessible
tPUW
Time
Table3. Power-Up Timing and Write Inhibit Threshold
Symbol
Parameter
Min
tVSL
VCC(min) To CS# Low
10
tPUW
Time Delay Before Write Instruction
1
VWI
Write Inhibit Voltage
2.1
Typ
Max
Unit
us
2.3
10
ms
2.5
V
8.2. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register
contains 00H (all Status Register bits are 0).
8.3. DATA RETENTION AND ENDURANCE
Parameter
Minimum Pattern Data Retention Time
Erase/Program Endurance
Test Condition
Min
Units
150�
10
Years
125�
20
Years
-40 to 85�
100K
Cycles
8.4. LATCH UP CHARACTERISTICS
Parameter
Min
Input Voltage Respect To VSS On I/O Pins
VCC Current
39
48 - 39
Max
-1.0V
VCC+1.0V
-100mA
100mA
Rev.1.0
Uniform SectorUniform sector dual and quad serial flash
GD25Q41BxIGx
Dual and Quad Serial Flash
GD25Q41B
8.5. ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Ambient Operating Temperature
-40 to 85
�
Storage Temperature
-65 to 150
�
Output Short Circuit Current
200
mA
Applied Input/Output Voltage
-0.5 to 4.0
V
-0.5 to 4.0
V
VCC
0.8VCC
Input timing reference level
0.7VCC
0.2VCC
0.1VCC
Output timing reference level
AC Measurement Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
8.6. CAPACITANCE MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
Input Rise And Fall time
pF
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
Output Timing Reference Voltage
0.5VCC
V
Figure 38. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
40
48 - 40
20ns
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
8.7. DC CHARACTERISTICS
(T= -40�~85�, VCC=2.7~3.6V)
Symbol
Parameter
Test Condition
Min.
Typ
Max.
Unit.
ILI
Input Leakage Current
±2
��
ILO
Output Leakage Current
±2
��
ICC1
Standby Current
20
30
��
1
5
��
15
mA
12
mA
4
mA
2
mA
1
mA
CS#=VCC,
VIN=VCC or VSS
ICC2
Deep Power-Down Current
CS#=VCC,
VIN=VCC or VSS
CLK=0.1VCC / 0.9VCC
at 104MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 80MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
ICC3
Operating Current (Read)
at 33MHz,
Q=Open(*1,*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 4MHz,
Q=Open(*2,*4 I/O)
CLK=0.1VCC / 0.9VCC
at 4MHz,
Q=Open(*1 I/O)
ICC4
Operating Current (PP)
CS#=VCC
10
15
mA
ICC5
Operating Current(WRSR)
CS#=VCC
8
12
mA
ICC6
Operating Current (SE)
CS#=VCC
10
15
mA
ICC7
Operating Current (BE)
CS#=VCC
10
15
mA
I CC8
Operating Current (CE)
10
15
mA
I CC9
High Performance Current
400
600
uA
VIL
Input Low Voltage
-0.5
0.2VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
IOL =1.6mA
0.4
V
VOH
Output High Voltage
IOH =-�����
VCC-0.2
V
41
48 - 41
Rev.1.0
Uniform Sector
Dual and Quad Serial
Flash
GD25Q41B
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
8.8. AC CHARACTERISTICS
(T= -40�~85�, VCC=2.7~3.6V, CL=30pf)
Symbol
Parameter
Min.
Typ.
Max.
Unit.
DC.
104
MHz
Serial Clock Frequency For: Read
DC.
80
MHz
tCLH
Serial Clock High Time
3.5
ns
tCLL
Serial Clock Low Time
3.5
ns
tCLCH
Serial Clock Rise Time (Slew Rate)
0.2
V/ns
tCHCL
Serial Clock Fall Time (Slew Rate)
0.2
V/ns
tSLCH
CS# Active Setup Time
5
ns
tCHSH
CS# Active Hold Time
5
ns
tSHCH
CS# Not Active Setup Time
5
ns
tCHSL
CS# Not Active Hold Time
5
ns
tSHSL
CS# High Time (read/write)
20
ns
tSHQZ
Output Disable Time
tCLQX
Output Hold Time
tDVCH
Serial Clock Frequency For: FAST_READ, PP, SE, BE,
fC
DP, RES, WREN, WRDI, WRSR, RDSR, RDID (*1,*2,*4
I/O)
fR
6
ns
1.2
ns
Data In Setup Time
2
ns
tCHDX
Data In Hold Time
5
ns
tHLCH
Hold# Low Setup Time (relative to Clock)
3.5
ns
tHHCH
Hold# High Setup Time (relative to Clock)
3.5
ns
tCHHL
Hold# High Hold Time (relative to Clock)
3.5
ns
tCHHH
Hold# Low Hold Time (relative to Clock)
3.5
ns
tHLQZ
Hold# Low To High-Z Output
6
ns
tHHQX
Hold# Low To Low-Z Output
6
ns
tCLQV
Clock Low To Output Valid
6
ns
tWHSL
Write Protect Setup Time Before CS# Low
20
ns
tSHWL
Write Protect Hold Time After CS# High
100
ns
tDP
CS# High To Deep Power-Down Mode
tRES1
tRES2
CS# High To Standby Mode Without Electronic Signature
Read
CS# High To Standby Mode With Electronic Signature
Read
0.1
��
5
��
5
��
tHPM
CS# High To High Performance Mode
0.2
us
tSUS
CS# High To Next Command After Suspend
20
us
10
30
ms
0.35
2.4
ms
tW
Write Status Register Cycle Time
tPP
Page Programming Time
tSE
tBE
tCE
Uniform Sector
Sector Erase Time
Dual and Quad Serial Flash
Block Erase Time(32K\64K)
Chip Erase Time
50
0.18\0.25
1.5
200\400 (1)
ms
GD25Q41B
0.6\0.8
s
3.0
s
42
Note:
1. Max Value tSE with <50K cycles is 200 ms and >50K
48 - &
42<100K cycles is 400 ms.
Figure 39. Serial Input Timing
CS#
tSHSL
Rev.1.0
Uniform Sector
Dual and Quad Serial Flash
tCE
GD25Q41B
Uniform sector dual and quad
serial3.0flash
GD25Q41BxIGx
Chip Erase Time
1.5
s
Note:
1. Max Value tSE with <50K cycles is 200 ms and >50K & <100K cycles is 400 ms.
Figure 39. Serial Input Timing
tSHSL
CS#
tCHSL
SCLK
tSLCH
tDVCH
tCHSH
tSHCH
tCHCL
tCLCH
tCHDX
LSB
SI
MSB
SO
High-Z
Figure 40. Output Timing
CS#
tCLH
SCLK
tCLQV
tCLQX
tCLQV
tSHQZ
tCLL
tCLQX
LSB
SO
SI
Least significant address bit (LIB) in
Figure 41. Hold Timing
CS#
SCLK
SO
tCHHL
tHLCH
tCHHH
tHLQZ
tHHCH
tHHQX
HOLD#
SI do not care during HOLD operation.
43
48 - 43
Rev.1.0
Uniform Sector
Dual and Quad Serial
Flash
GD25Q41B
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
9. ORDERING INFORMATION
GD XX X XX X X X X X
Packing Type
T or no mark:Tube
Y:Tray
R:Tape & Reel
Green Code
G:Pb Free & Halogen Free Green Package
Temperature Range
I:Industrial(-40� to +85�)
Package Type
T:SOP8 150mil
S:SOP8 208mil
O:TSSOP8 173mil
U: USON8 (3*2mm)
Generation
B: B Version
Density
41:4Mb
Series
Q:2.7~3.6V, 4KB Uniform Sector, Quad I/O
Product Family
25:Serial Flash
NOTE:
1.
Standard bulk shipment is in Tube. Any alternation of packing method (for Tape, Reel and Tray etc.), please
advise in advance.
44
48 - 44
Rev.1.0
Uniform Sector
Dual and Quad Serial
Flash
GD25Q41B
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
10. PACKAGE INFORMATION
10.1.
Package SOP8 150MIL
8
�
5
E1
E
L
1
4
L1
C
D
A2
S
Seating plane
A1
b
e
A
Gauge plane
0.10
Detail "�"
Dimensions
Symbol
A
Unit
mm
Inch
A1
A2
b
C
D
E
E1
e
L
L1
S
�
�
�
Min
1.35
0.05
1.35
0.31
0.15
4.77
5.80
-
-
0.40
0.85
0.71
0°
6°
11°
Nom
-
-
-
-
-
4.90
6.00
3.90
1.27
-
1.06
0.76
-
7°
12°
Max
1.75
0.25
1.55
0.51
0.25
5.03
6.20
-
-
0.90
1.27
0.81
8°
8°
13°
Min
0.053
0.002
0.053
0.012
0.006
0.188
0.228
-
-
0.016
0.033
0.028
0°
6°
11°
Nom
-
-
-
0.016
-
0.193
0.236
0.154
0.050
-
0.042
0.030
-
7°
12°
Max
0.069
0.010
0.061
0.020
0.010
0.198
0.244
-
-
0.035
0.050
0.032
8°
8°
13°
Note:Both package length and width do not include mold flash.
45
48 - 45
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
10.2.
Package SOP8 208MIL
8
�
5
E1
E
L
1
L1
4
C
D
A2
S
A1
b
e
A
Dimensions
Symbol
A1
A2
b
C
D
E
E1
Min
0.05
1.70
0.31
0.18
5.13
7.70
5.18
Nom
0.15
1.80
0.41
0.21
5.23
7.90
5.28
0.25
1.91
0.51
0.25
5.33
8.10
Min
0.002
0.067
0.012
0.007
0.202
Nom
0.006
0.071
0.016
0.008
0.010
0.075
0.020
0.010
Unit
mm
Max
Inch
Max
A
2.16
0.085
e
L
L1
S
�
0.50
1.21
0.62
0
0.67
1.31
0.74
5
5.38
0.85
1.41
0.88
8
0.303
0.204
0.020
0.048
0.024
0
0.206
0.311
0.208
0.026
0.052
0.029
5
0.210
0.319
0.212
0.033
0.056
0.035
8
1.27
0.050
Note:Both package length and width do not include mold flash.
46
48 - 46
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
10.3.
Package TSSOP8 173MIL
8
�
5
E1
E
L1
L
1
4
C
D
A2
S
b
e
A
A1
Dimensions
Symbol
A
Unit
mm
Inch
A1
A2
b
C
D
E
E1
e
L
L1
�
Min
-
0.05
0.80
0.19
0.09
2.83
6.20
4.30
-
0.45
0.85
0
Nom
-
0.10
0.92
0.24
0.14
2.96
6.40
4.40
0.65
0.60
1.00
4
Max
1.20
0.15
1.05
0.30
0.20
3.10
6.60
4.50
-
0.75
1.15
8
Min
-
0.002
0.031
0.007
0.003
0.111
0.244
0.169
-
0.018
0.033
0
Nom
-
0.004
0.036
0.010
0.006
0.116
0.252
0.173
0.026
0.024
0.039
4
Max
0.047
0.006
0.041
0.012
0.008
0.122
0.260
0.177
-
0.030
0.045
8
Note:Both package length and width do not include mold flash.
47
48 - 47
Rev.1.0
Uniform Sector
Uniform
sector dual and quad serial
flash
GD25Q41BxIGx
Dual and Quad Serial
Flash
GD25Q41B
10.4.
Package USON8 (3*2mm)
D
A2
y
E
A
Top View
L
A1
Side View
D1
b
1
E1
e
Bottom View
Dimensions
Symbol
Unit
mm
Inch
A
A1
A2
b
D
D1
E
E1
e
y
L
0.00
0.30
Min
0.50
0.13
0.18
2.90
0.15
1.90
1.50
Nom
0.55
0.15
0.25
3.00
0.20
2.00
1.60
Max
0.60
0.18
0.30
3.10
0.30
2.10
1.70
0.05
0.45
Min
0.020
0.005
0.007
0.114
0.006
0.075
0.059
0.000
0.012
Nom
0.022
0.006
0.010
0.118
0.008
0.079
0.063
Max
0.024
0.007
0.012
0.122
0.012
0.083
0.067
0.05
0.002
0.50
0.35
0.020
0.014
0.002
0.018
Note:Both package length and width do not include mold flash.
48
48 - 48
Rev.1.0