Datasheet

204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Advantech
AQD-SD3L4GN16-MQ
Datasheet
Rev. 0.0
2014-03-8
1
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Description
Pin Identification
AQD-SD3L4GE16-MG is a DDR3L SO DIMM
Symbol
Function
of 256Mx8bits DDR3 low voltage SDRAM in FBGA
A0~A15, BA0~BA2
Address/Bank input
package and a 2K bits serial EEPROM on a 204-pin
DQ0~DQ63
Bi-direction data bus.
DQS0~DQS7
Data strobes
/DQS0~/DQS7
Differential Data strobes
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
use of system clock. Data I/O transactions are possible
CKE0, CKE1
Clock Enable Input.
on both edges of DQS. Range of operation frequencies,
ODT0 &ODT1
On-die termination control line
programmable latencies allow the same device to be
/S0 &/S1
DIMM rank select lines.
useful for a variety of high bandwidth, high performance
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
DM0~DM7
Data masks/high data strobes
 JEDEC standard 1.35V(1.28V~1.45V) Power supply
VDD
Core power supply
 JEDEC standard 1.5V(1.425V~1.575V) Power supply
VDDQ
I/O driver power supply
 VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
VREFDQ
DQ reference supply
high-speed, low power memory module that use 16 pcs
printed circuit board. AQD-SD3L4GN16-MQ is a Dual
In-Line Memory Module and is intended for mounting into
204-pin edge connector sockets.
Synchronous design allows precise cycle control with the
memory system applications.
Features
 RoHS compliant products.
 Clock Freq: 800MHZ for 1600MT/s.
Command/address reference
 Programmable CAS Latency: 6, 7, 8, 9, 10, 11
VREFCA
 Programmable Additive Latency (Posted /CAS):
 0,CL-2 or CL-1 clock
VDDSPD
 Programmable /CAS Write Latency (CWL)
supply
SPD EEPROM power supply
I2C serial bus address select for
SA0~SA1
 = 8(DDR3-1600)
EEPROM
 8 bit pre-fetch
SCL
I2C serial bus clock for EEPROM
 Bi-directional Differential Data-Strobe
SDA
I2C serial bus data for EEPROM
 Internal calibration through ZQ pin
VSS
Ground
 On Die Termination with ODT pin
/RESET
Set DRAMs Known State
VTT
DRAM I/O termination supply
NC
No Connection
 Burst Length: 4, 8
 Serial presence detect with EEPROM
Asynchronous reset
 PCB edge connector treated with 30u” Gold-Plating
2
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Dimensions (Unit: millimeter)
Note:1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Pin Assignments
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
No
Name
No
Name
No
Name
No
Name
No
Name
No
01 VREFDQ 41
DQ17
81
VDD
121
/S1
161
VSS
201
02
VSS
42
DQ21
82
VDD
122
NC
162
VSS
202
03
VSS
43
VSS
83
A12/BC
123
VDD
163
DQ48
203
04
DQ4
44
VSS
84
A11
124
VDD
164
DQ52
204
05
DQ0
45
/DQS2
85
A9
125
TEST
165
DQ49
06
DQ5
46
DM2
86
A7
126 VREFCA 166
DQ53
07
DQ1
47
DQS2
87
VDD
127
VSS
167
VSS
08
VSS
48
VSS
88
VDD
128
VSS
168
VSS
09
VSS
49
VSS
89
A8
129
DQ32
169
/DQ56
10
/DQS0
50
DQ22
90
A6
130
DQ36
170
DM6
11
DM0
51
DQ18
91
A5
131
DQ33
171
DQS6
12
DQS0
52
DQ23
92
A4
132
DQ37
172
VSS
13
VSS
53
DQ19
93
VDD
133
VSS
173
VSS
14
VSS
54
VSS
94
VDD
134
VSS
174
DQ54
15
DQ2
55
VSS
95
A3
135
/DQS4
175
DQ50
16
DQ6
56
DQ28
96
A2
136
DM4
176
DQ55
17
DQ3
57
DQ24
97
A1
137
DQS4
177
DQ51
18
DQ7
58
DQ29
98
A0
138
VSS
178
VSS
19
VSS
59
DQ25
99
VDD
139
VSS
179
VSS
20
VSS
60
VSS
100
VDD
140
DQ38
180
DQ60
21
DQ8
61
VSS
101
141
DQ34
181
DQ56
CK0
22
DQ12
62
/DQ3
102
CK1
142
DQ39
182
DQ61
23
DQ9
63
DM3
103
/CK0
143
DQ35
183
DQ57
24
DQ13
64
DQ3
104
/CK1
144
VSS
184
VSS
25
VSS
65
VSS
105
VDD
145
VSS
185
VSS
26
VSS
66
VSS
106
VDD
146
DQ44
186
/DQS7
27
/DQS1
67
DQ26
107
A10/AP
147
DQ40
187
DM7
28
DM1
68
DQ30
108
148
DQ45
188
DQS7
BA1
29
DQS1
69
DQ27
109
BA0
149
DQ41
189
VSS
30 /RESET
70
DQ31
110
/RAS
150
VSS
190
VSS
31
VSS
71
VSS
111
VDD
151
VSS
191
DQ58
32
VSS
72
VSS
112
VDD
152
/DQS5
192
DQ62
33
DQ10
73
CKE0
113
/WE
153
DM5
193
DQ59
34
DQ14
74
CKE1
114
154
DQS5
194
/S0
DQ63
35
DQ11
75
VDD
115
/CAS
155
VSS
195
VSS
36
DQ15
76
VDD
116
ODT0
156
VSS
196
VSS
37
VSS
77
NC
117
VDD
157
DQ42
197
SA0
38
VSS
78
A15
118
VDD
158
DQ46
198
NC
39
QC16
79
BA2
119
A13
159
DQ43
199
VDDSPD
40
DQ20
80
A14
120
160
DQ47
200
ODT1#
SDA
/S1,ODT1,CKE1：Used for dual-rank UDIMMs; NC on single-rank UDIMMs.
CK1 and /CK1：Used for dual-rank UDIMMs; not used on single-rank UDIMMs but terminated.
4
Pin
Name
SA1
SCL
VTT
VTT
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
4GB, 2Gbx16 Module(2 Rank x8)
5
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes
in specifications at any time without prior notice.
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Operating Temperature
TOPER -10 to 85 C
Note:
Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
Note
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
C
1,2
1. Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions
Rating
Parameter
Supply voltage
Supply voltage for Output
Symbol
VDD
VDDQ
I/O Reference Voltage (DQ)
VREFDQ(DC)
I/O Reference Voltage (CMD/ADD) VREFCA(DC)
AC Input Logic High
VIH(AC)
AC Input Logic Low
VIL(AC)
DC Input Logic High
VIH(DC)
DC Input Logic Low
VIL(DC)
Voltage
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
6
Unit Notes
Min
Typ.
Max
1.283
1.425
1.283
1.425
0.49*VDDQ
0.49*VDDQ
VREF+0.160
VREF+0.175
VREF+0.09
VREF+0.1
VSS
VSS
1.35
1.5
1.35
1.5
0.50*VDDQ
0.50*VDDQ
-
1.45
1.575
1.45
1.575
0.51*VDDQ
0.51*VDDQ
VREF-0.160
VREF-0.175
VDD
VDD
VREF-0.09
VREF-0.1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1, 2
1, 2
3
3
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
IDD Specification parameters Definition - 4GB (2 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Symbol
DDR3 1600 CL11
Unit
IDD0
440
mA
IDD1
528
mA
IDD2P
144
mA
IDD2Q
256
mA
IDD2N
256
mA
IDD3P
304
mA
IDD3N
304
mA
IDD4R
1256
mA
IDD4W
1000
mA
IDD5
1240
mA
IDD6
160
mA
IDD7
1760
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT
= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =
0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
Note:
1.Module IDD was calculated on the specific brand DRAM(4xnm) component IDD and can be differently
measured according to DQ loading capacitor.
7
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Timing Parameters & Specifications
Speed
Parameter
DDR3 1600
Unit
Symbol
Min
Max
Average Clock Period
tCK
1.25
-
ns
CK high-level width
tCH
0.47
0.53
tCK
CK low-level width
tCL
0.47
0.53
tCK
tDQSQ
-
125
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-450
225
ps
tHZ(DQ)
-
225
tDS
10
-
tDH
45
tDIPW
360
-
ps
DQS, /DQS Read preamble
DQS, /DQS differential Read
postamble
tRPRE
0.9
-
tCK
tRPST
0.3
-
tCK
DQS, /DQS Write preamble
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-450
225
ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
225
ps
tDQSL
0.45
0.55
tCK
tDQSH
0.45
0.55
tCK
tDQSS
-0.27
0.27
tCK
tDSS
0.18
-
tCK
tDSH
0.18
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
tWR
15
-
ns
Mode register set command cycle
time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
nCK
Auto precharge write recovery +
precharge time
tDAL
DQS, /DQS to DQ skew, per group,
per access
DQ high-impedance time from CK,
/CK
Data setup time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
DQ and DM input pulse width for each
input
DQS, /DQS differential input low pulse
width
DQS, /DQS differential input high
pulse width
DQS, /DQS rising edge to CK, /CK
rising edge
DQS, /DQS falling edge setup time to
CK, /CK rising edge
DQS, /DQS falling edge hold time to
CK, /CK rising edge
Delay from start of Internal write
transaction to Internal read command
Write recovery time
ps
ps
tWR+tRP/tck
8
ps
nCK
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
Active to active command period for
1KB page size
Speed
Parameter
Active to active command period for
2KB page size
Four Activate Window for 1KB page
size
tRRD
Max
(4tck, 7.5ns)
DDR3 1600
Unit
Min
Max
(4tck, 6ns)
Max
tFAW
30
-
ns
Power-up and RESET calibration time
tZQinitl
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
tZQcs
64
-
tCK
tXS
Max
(5tCK, tRFC+10ns)
-
tXSDLL
tDLLK(min)
-
Normal operation short calibration
time
Exit self refresh to commands not
requiring a locked DLL
Exit self refresh to commands
requiring a locked DLL
Internal read to precharge command
delay
Minimum CKE low width for Self
refresh entry to exit timing
Exit power down with DLL to any valid
command: Exit Precharge Power
Down with DLL
CKE minimum pulse width (high and
low pulse width)
Symbol
ns
tRRD
Max
tRTP
(4tck, 7.5ns)
tCKESR
tCK(min)+1tCK
Max
tXP
(3tCK, 6ns)
-
tCK
-
tCKE
Max
(3tCK, 5ns)
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-225
225
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Asynchronous RTT turn-on delay
(Power-Down mode)
Asynchronous RTT turn-off delay
(Power-Down mode)
9
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
SERIAL PRESENCE DETECT SPECIFICATION
AQD-SD3L4GE16-MG Serial Presence Detect
Byte No.
Function Described
0
Number of SPD Bytes written / SPD device size / CRC
coverage during module production
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
SPD Revision
Key Byte / DRAM Device Type
Key Byte / Module Type
SDRAM Density and Banks
SDRAM Addressing
Reserved
Module Organization
Module Memory Bus Width
Fine Timebase Dividend and Divisor
Medium Timebase Dividend
Medium Timebase Divisor
SDRAM Minimum Cycle Time (tCKmin)
Reserved
CAS Latencies Supported, Least Significant Byte
CAS Latencies Supported, Most Significant Byte
Minimum CAS Latency Time (tAAmin)
Minimum Write Recovery Time (tWRmin)
Minimum /RAS to /CAS Delay Time (tRCDmin)
Minimum Row Active to Row Active Delay Time
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
Minmum Active to Active/Refresh Time (tRCmin)
Minmum Refresh Recovery Time (tRFCmin), Least
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
Significant Byte
Minmum Internal Write to Read Command Delay Time
(tWTmin)
Minimum Internal Read to Precharge Command Delay
Time (tRTPmin)
Upper Nibble for tFAW
Minmum Four Active Window Delay Time (tFAWmin)
30
SDRAM Optional Features
31
SDRAM Thermal and Refresh Options
19
20
21
22
23
24
25
26
27
10
Standard Specification
CRC:0-116Byte
SPD Byte use: 176Byte
SPD Byte total: 256Byte
Version 1.0
DDR3 SDRAM
SO-DIMM
2Gb 8banks
ROW:15, Column:10
1.35V and 1.5V
2Rank / x8
Non ECC 64bit
2.5ps
0.125ns
0.125ns
1.25ns
6, 7, 8, 9,10,11
6, 7, 8, 9,10,11
13.125ns
15ns
13.125ns
Vendor Part
6ns
30
13.125ns
35ns
48.125ns
69
11
18
81
160ns
00
160ns
05
7.5ns
3C
7.5ns
3C
30ns
30ns
DLL off Mode,
RZQ/6, RZQ/7
ASR / 85℃~95℃ 2X
refresh rate /95℃
00
F0
92
10
0B
03
03
19
02
09
03
52
01
08
0A
00
FE
00
69
78
69
83
05
204Pin DDR3L 1.35V 1600 SODIMM
4GB Based on 256Mx8
AQD-SD3L4GN16-MQ
32
33
34-59
60
61
62
63
64-116
117
118
119
120
121
122-125
126
127
128-145
146-147
148
149
150-151
152-163
164-175
176-255
Module Thermal Sensor
SDRAM Device Type
Reserved, General Section
Module Nominal Height
Module Max Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module ID: Module Manufacturing Date(Year)
Module ID: Module Manufacturing Date(Week)
Module ID : Module Serial Number
Cyclical Redundancy Code
Cyclical Redundancy Code
Module Part Number
Revision Code
DRAM Manufacturer ID Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Manufacturer’s Specific Data (Working Order Number)
Manufacturer’s Specific Data (SPD Naming Number)
Open for customer use
Non Thermal Sensor
30mm
Raw Card F
Revision 0
Standard
ADATA
ADATA
*Note: 1
*Note: 2
*Note: 3
*Note: 4
CRC-CCITT(LOW)
CRC-CCITT(HIGH)
*Note: 5
-
*Note: 5
*Note: 6
*Note: 7
*Note :
1. Byte 119 -- Manufacturing location by manufacturing location (00:Taiwan /01:China)
2. Byte 120 -- Module manufacturing date by year (YY).
3. Byte 121 -- Module manufacturing date by
week (WW).
4. Bytes 122~125 -- Module Serial Number.
5. Bytes 128~145 -- Manufacturer Part Number by module part number ,
(Unused digits are coded as ASCII blanks (20h)).
6. Bytes 152~163 -- Manufacturer's Specific Data by working order number.
(Unused digits are coded as 00h.)
7. Bytes 164~175 -- Manufacturer's Specific Data by SPD naming number.
(Unused digits are coded as 00h.)
8. Bytes 176~255 --These bytes are undefined and can be used for A-DATA's own purpose.
Digits are coded as 00h except 218=ADh now.
11
00
00
00
0F
11
05
00
00
04
CB
2F
97
00
00
00
00
-