Datasheet

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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Description
•
Pin Identification
DDR3 SO-DIMM is high-speed, low power memory
•
Pin Identification
module that use 256Mx8bits DDR3 SDRAM in FBGA
Symbol
package and a 2048 bits serial EEPROM on a 204-pin
A0~A14, BA0~BA2
Address/Bank input
printed circuit board. DDR3 SO-DIMM is a Dual In-Line
DQ0~DQ63
Data Input / Output.
DQS0~DQS7
Data strobes
/DQS0~/DQS7
Differential Data strobes
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
on both edges of DQS. Range of operation frequencies,
CKE0, CKE1
Clock Enable Input.
programmable latencies allow the same device to be
ODT0, ODT1
On-die termination control line
useful for a variety of high bandwidth, high performance
/CS0, /CS1
DIMM Rank Select Lines.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DM0~DM7
Data masks/high data strobes
VDD
Voltage power supply
VREFDQ/ VREFCA
Power Supply for Reference
VDDSPD
SPD EEPROM Power Supply
Memory Module and is intended for mounting into 204-pin
edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
memory system applications.
Features
• RoHS compliant products.
• JEDEC standard 1.5V ± 0.075V Power supply
• VDDQ=1.5V ± 0.075V
• Clock Freq: 667MHZ for 1333Mb/s/Pin.
• Programmable CAS Latency: 5, 6, 7, 8, 9 ,10 ,11
• Programmable Additive Latency (Posted /CAS):
Function
I2C serial bus address select for
SA0~SA2
0,CL-2 or CL-1 clock
EEPROM
• Programmable /CAS Write Latency (CWL)
SCL
I2C serial bus clock for EEPROM
SDA
I2C serial bus data for EEPROM
VSS
Ground
/RESET
Set DRAMs Known State
• Internal calibration through ZQ pin
VTT
SDRAM I/O termination supply
• On Die Termination with ODT pin
NC
No Connection
= 7(DDR3-1333)
• 8 bit pre-fetch
• Burst Length: 4, 8
• Bi-directional Differential Data-Strobe
• Serial presence detect with EEPROM
• Asynchronous reset
Transcend Information Inc.
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Dimensions (Unit: millimeter)
Note:
1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
Transcend Information Inc.
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Pin Assignments
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
No
Name
No
Name
No
Name
No
Name
No
Name
No
01
VREFDQ 69
DQ27
137
DQS4
02
VSS
70
DQ31
138
03
VSS
71
VSS
139
VSS
04
DQ4
72
VSS
140
05
DQ0
73
CKE0
141
DQ34
06
DQ5
74
CKE1,NC 142
07
DQ1
75
VDD
143
DQ35
08
VSS
76
VDD
144
09
VSS
77
NC
145
VSS
10
/DQS0
78
NC
146
11
DM0
79
BA2
147
DQ40
12
DQS0
80
A14
148
13
VSS
81
VDD
149
DQ41
14
VSS
82
VDD
150
15
DQ2
83
A12
151
VSS
16
DQ6
84
A11
152
17
DQ3
85
A9
153
DM5
18
DQ7
86
A7
154
19
VSS
87
VDD
155
VSS
20
VSS
88
VDD
156
21
DQ8
89
A8
157
DQ42
22
DQ12
90
A6
158
23
DQ9
91
A5
159
DQ43
24
DQ13
92
A4
160
25
VSS
93
VDD
161
VSS
26
VSS
94
VDD
162
27
/DQS1
95
A3
163
DQ48
28
DM1
96
A2
164
29
DQS1
97
A1
165
DQ49
30
/RESET
98
A0
166
31
VSS
99
VDD
167
VSS
32
VSS
100
VDD
168
33
DQ10
101
CK0
169
/DQS6
34
DQ14
102
CK1,NC 170
35
DQ11
103
/CK0
171
DQS6
36
DQ15
104 /CK1,NC 172
37
VSS
105
VDD
173
VSS
38
VSS
106
VDD
174
39
DQ16
107
A10/AP 175
DQ50
40
DQ20
108
BA1
176
41
DQ17
109
BA0
177
DQ51
42
DQ21
110
/RAS
178
43
VSS
111
VDD
179
VSS
44
VSS
112
VDD
180
45
/DQS2
113
/WE
181
DQ56
46
DM2
114
/CS0
182
47
DQS2
115
/CAS
183
DQ57
48
VSS
116
ODT0
184
49
VSS
117
VDD
185
VSS
50
DQ22
118
VDD
186
51
DQ18
119
A13
187
DM7
52
DQ23
120 ODT1,NC 188
53
DQ19
121 /CS1,NC 189
VSS
54
VSS
122
NC
190
55
VSS
123
VDD
191
DQ58
56
DQ28
124
VDD
192
57
DQ24
125
TEST
193
DQ59
58
DQ29
126 VREFCA 194
59
DQ25
127
VSS
195
VSS
60
VSS
128
VSS
196
61
VSS
129
DQ32
197
SA0
62
/DQS3
130
DQ36
198
63
DM3
131
DQ33
199
VDDSPD 64
DQS3
132
DQ37
200
65
VSS
133
VSS
201
SA1
66
VSS
134
VSS
202
67
DQ26
135
/DQS4
203
Vtt
68
DQ30
136
DM4
204
/CS1,ODT1,CKE1：Used for dual-rank SO-DIMMs; NC on single-rank SO-DDIMMs.
CK1 and /CK1：Used for dual-rank SO-DIMMs; not used on single-rank SO-DIMMs but terminated.
Transcend Information Inc.
3
Pin
Name
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
/DQS5
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
/DQS7
DQS7
VSS
DQ62
DQ63
VSS
NC
SDA
SCL
Vtt
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N2288444422--33S
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Block Diagram
4GB, 512Mx64 Module(2 Rank x8)
/S0
/S1
/DQS4
DQS4
DM4
/DQS0
DQS0
DM0
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D0
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D8
ZQ
/DQS1
DQS1
DM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
9
10
11
12
13
14
15
/CS DQS /DQS
0
1
2
3
4
5
6
7
D1
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D4
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D12
ZQ
D9
ZQ
40
41
42
43
44
45
46
47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D5
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D13
ZQ
/DQS6
DQS6
DM6
DM
16
17
18
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D2
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D10
ZQ
/DQS3
DQS3
DM3
48
49
50
51
52
53
54
55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D6
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D14
ZQ
/DQS7
DQS7
DM7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
/CS DQS /DQS
0
1
2
3
4
5
6
7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
/DQS2
DQS2
DM2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/DQS5
DQS5
DM5
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
25
26
27
28
29
30
31
/CS DQS /DQS
0
1
2
3
4
5
6
7
D3
ZQ
ZQ of D0–D15
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
D11
ZQ
240 Ohm *16
56
57
58
59
60
61
62
63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EEPROM
SCL
BA0~BA2
A0~A15
CKE1
CKE0
/RAS
/CAS
/WE
ODT0
ODT1
CK0
/CK0
CK1
/CK1
BA0–BA2: SDRAMs D0–D15
A0-A15: SDRAMs D0–D15
CKE: SDRAMs D8– D15
CKE: SDRAMs D0– D7
/RAS: SDRAMs D0–D15
/CAS: SDRAMs D0–D15
/WE: SDRAMs D0–D15
ODT: SDRAM s D0–D7
ODT: SDRAM s D8–D15
CK: SDRAMs D0– D7
/CK: SDRAMs D0–D7
CK: SDRAMs D8– D15
/CK: SDRAMs D8–D15
WP
A0 A1 A2
SA0 SA1SA2
/CS DQS /DQS
0
1
2
3
4
5
6
7
D7
ZQ
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
/CS DQS /DQS
0
1
2
3
4
5
6
7
D15
VDDSPD
VDD/VDDQ
SDA
VREFDQ
VSS
VREFCA
ZQ
EEPROM
D0~D15
D0~D15
D0~D15
D0~D15
NOTE:
1.
2.
3.
4.
DQ-to-I/O wiring is shown as recommended but may be changed.
DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be
maintained as shown.
DQ,DM,DQS,/DQS resistors: Refer to associated topology
diagram.
For each DRAM,a unique ZQ resistor is connected to ground. The
ZQ resistor is 240 Ohm +/-1%
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
Transcend Information Inc.
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Note
Operating Temperature
TOPER
0 to 85
°C
Note: 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be
supported.
1,2
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on VDD relative to Vss
VDD
-0.4 ~ 1.975
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.4 ~ 1.975
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.4 ~ 1.975
V
1
Storage temperature
TSTG
-55~+100
°C
1,2
1.
Stress
greater
than
those
listed
under
“Absolute
Maximum
Ratings”
may
cause
permanent
damage
to
the
Note:
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.5)
Rating
Parameter
Symbol
Unit Note
Min
Typ.
Max
Supply voltage
VDD
1.425
1.5
1.575
V
Supply voltage for Output
VDDQ
1.425
1.5
1.575
V
I/O Reference Voltage (DQ)
VREFDQ(DC) 0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
I/O Reference Voltage (CMD/ADD)
VREFCA(DC) 0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
AC Input Logic High
VIH(AC)
VREF+0.175
V
AC Input Logic Low
VIL(AC)
VREF-0.175
V
DC Input Logic High
VIH(DC)
VREF+0.1
VDD
V
DC Input Logic Low
VIL(DC)
VSS
VREF-0.1
V
Note: There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance.
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.
3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.
1, 2
1, 2
3
3
AC Input Level for Differential Signals
Parameter
Differential Input Logical High
Differential Input Logical Low
Transcend Information Inc.
Symbol
VIHdiff
VILdiff
5
Value
+200
-200
Unit
mV
Note
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
IDD Specification parameters Definition( IDD values are for full operating range of Voltage and Temperature)
4GB, 512Mx64 Module(2 Rank x8)
Parameter
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC =
tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid
commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Symbol
DDR3 1333 CL9
Unit
IDD0
760
mA
IDD1
880
mA
IDD2P
320
mA
IDD2Q
480
mA
IDD2N
560
mA
IDD3P
480
mA
IDD3N
720
mA
IDD4R
1200
mA
IDD4W
1400
mA
IDD5
1640
mA
IDD6
192
mA
IDD7
1960
mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD),
tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is
HIGH, /CS is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
/CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Active power - down current; All banks open; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT
= 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL =
8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING IDD4R
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and /CK at 0V; CKE ≒ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT =
0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
Note:
1.Module IDD was calculated on the specific brand DRAM component IDD and can be differently measured
according to DQ loading capacitor.
Transcend Information Inc.
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Timing Parameters & Specifications
Speed
Parameter
DDR3 1333
Unit
Symbol
Min
Max
Average Clock Period
tCK
1.5
<1.875
ns
CK high-level width
tCH
0.47
0.53
tCK
CK low-level width
tCL
0.47
0.53
tCK
tDQSQ
-
125
ps
DQ output hold time from DQS, /DQS
tQH
0.38
-
tCK
DQ low-impedance time from CK, /CK
tLZ(DQ)
-500
250
ps
tHZ(DQ)
-
250
ps
tDS
30
-
ps
tDH
65
-
tDIPW
400
-
ps
DQS, /DQS Read preamble
tRPRE
0.9
-
tCK
DQS, /DQS differential Read
postamble
tRPST
0.3
-
tCK
DQS, /DQS Write preamble
tWPRE
0.9
-
tCK
DQS, /DQS Write postamble
tWPST
0.3
-
tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-500
250
ps
DQS, /DQS high-impedance time
tHZ(DQS)
-
250
ps
tDQSL
0.45
0.55
tCK
tDQSH
0.45
0.55
tCK
tDQSS
-0.25
+0.25
tCK
tDSS
0.2
-
tCK
tDSH
0.2
-
tCK
tWTR
Max
(4tck, 7.5ns)
-
tWR
15
-
ns
Mode register set command cycle
time
tMRD
4
-
tCK
/CAS to /CAS command delay
tCCD
4
-
nCK
DQS, /DQS to DQ skew, per group,
per access
DQ high-impedance time from CK,
/CK
Data setup time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
Data hold time to DQS, /DQS
reference to Vih(ac)Vil(ac) levels
DQ and DM input pulse width for each
input
DQS, /DQS differential input low pulse
width
DQS, /DQS differential input high
pulse width
DQS, /DQS rising edge to CK, /CK
rising edge
DQS, /DQS falling edge setup time to
CK, /CK rising edge
DQS, /DQS falling edge hold time to
CK, /CK rising edge
Delay from start of Internal write
transaction to Internal read command
Write recovery time
Transcend Information Inc.
7
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204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
Auto precharge write recovery +
precharge time
Speed
Parameter
Active to active command period for
1KB page size
tDAL
tWR+tRP/tck
nCK
DDR3 1333
Unit
Min
Max
(4tck, 6ns)
Max
(4tck, 7.5ns)
Max
tFAW
30
-
ns
tFAW
45
-
ns
Power-up and RESET calibration time
tZQinitl
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
tCK
tZQcs
64
-
tCK
tXS
Max
(5tCK, tRFC+10)
-
tXSDLL
tDLL(min)
-
Active to active command period for
2KB page size
Four Activate Window for 1KB page
size
Four Activate Window for 2KB page
size products
Normal operation short calibration
time
Exit self refresh to commands not
requiring a locked DLL
Exit self refresh to commands
requiring a locked DLL
Internal read to precharge command
delay
Minimum CKE low width for Self
refresh entry to exit timing
Exit power down with DLL to any valid
command: Exit Precharge Power
Down with DLL
CKE minimum pulse width (high and
low pulse width)
Symbol
tRRD
tRRD
Max
tRTP
(4tCK, 7.5ns)
tCKESR
tCK(min)+1tCK
Max
tXP
(3tCK, 6ns)
-
ns
-
tCK
-
tCKE
Max
(3tCK,5.625ns)
tAONPD
2
8.5
ns
tAOFPD
2
8.5
ns
ODT turn-on
tAON
-250
250
ps
ODT turn-off
tAOF
0.3
0.7
tCK
Asynchronous RTT turn-on delay
(Power-Down mode)
Asynchronous RTT turn-off delay
(Power-Down mode)
Transcend Information Inc.
8
T
TS
S77K
KS
SN
N2288444422--33S
S
204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
SERIAL PRESENCE DETECT SPECIFICATION
TS7KSN28442-3S Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-59
Function Described
Standard Specification
CRC:0-116Byte
Number of SPD Bytes written / SPD device size / CRC
SPD
Byte use: 176Byte
coverage during module production
SPD Byte total: 256Byte
SPD Revision
Version 0.5
Key Byte / DRAM Device Type
DDR3 SDRAM
Key Byte / Module Type
SODIMM
SDRAM Density and Banks
2GB 8banks
SDRAM Addressing
ROW:15, Column:10
Reserved
Module Organization
2Rank / x8
Module Memory Bus Width
Non ECC, 64bit
Fine Timebase Dividend and Divisor
2.5ps
Medium Timebase Dividend
0.125ns
Medium Timebase Divisor
0.125ns
SDRAM Minimum Cycle Time (tCKmin)
1.5ns
Reserved
CAS Latencies Supported, Least Significant Byte
5, 6, 7, 8, 9
CAS Latencies Supported, Most Significant Byte
Minimum CAS Latency Time (tAAmin)
13.125ns
Minimum Write Recovery Time (tWRmin)
15ns
Minimum /RAS to /CAS Delay Time (tRCDmin)
13.125ns
Minimum Row Active to Row Active Delay Time
6ns
(tRRDmin)
Minimum Row Precharge Time (tRPmin)
13.125ns
Upper Nibble for tRAS and tRC
Minmum Active to Precharge Time (tRASmin)
36ns
Minmum Active to Active/Refresh Time (tRCmin)
49.125ns
Minmum Refresh Recovery Time (tRFCmin), Least
160ns
Significant Byte
Minmum Refresh Recovery Time (tRFCmin), Most
160ns
Significant Byte
Minmum Internal Write to Read Command Delay Time
7.5ns
(tWTmin)
Minimum Internal Read to Precharge Command Delay
7.5ns
Time (tRTPmin)
Upper Nibble for tFAW
30ns
Minmum Four Active Window Delay Time (tFAWmin)
30ns
DLL off Mode,
SDRAM Optional Features
RZQ/6, RZQ/7
SDRAM Thermal and Refresh Options
No ODTs, Support ASR
Reserved
-
Transcend Information Inc.
9
Vendor Part
92
10
0B
03
03
19
00
09
03
52
01
08
0C
00
3E
00
69
78
69
30
69
11
20
89
00
05
3C
3C
00
F0
83
05
00
T
TS
S77K
KS
SN
N2288444422--33S
S
204Pin DDR3 1333 SO-DIMM
4GB Based on 256Mx8
60
61
62
63
64-116
117
118
119
120-121
122-125
126-127
Module Nominal Height
Module Max Thickness
Reference Raw Card Used
Address Mapping from Edge Connector to DRAM
Reserved
Module Manufacturer ID Code, Least Significant Byte
Module Manufacturer ID Code, Most Significant Byte
Module Manufacturing Location
Module Manufacturing Date
Module Serial Number
Cyclical Redundancy Code
30mm
Planar Double Sides
R/C F1
Standard
Transcend
Transcend
Taipei
-
0F
11
25
00
00
01
4F
54
00
00
94, 29
54 53 37 4B 53 4E
128-145 Module Part Number
TS7KSN28442-3S
32 38 34 34 32 2D
33 53 20 20 20 20
146-147
148-149
150-175
176-255
Revision Code
DRAM Manufacturer ID Code
Manufacturer Specific Data
Open for customer use
Transcend Information Inc.
By Manufacturer
By Manufacturer
Undefined
1
00
Variable
Variable
00