Data Sheet

S6AE102A / S6AE103A
Energy Harvesting PMIC for Wireless Sensor Node
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Cypress
product(s) described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.
Publication Number S6AE102A_DS405-00029
CONFIDENTIAL
Revision 0.2
Issue Date July 31, 2015
v1.2
D a t a S h e e t
( P r e l i m i n a r y )
Notice On Data Sheet Designations
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advise readers of product information or intended specifications throughout the product life cycle, including
development, qualification, initial production, and full production. In all cases, however, readers are
encouraged to verify that they have the latest information before finalizing their design. The following
descriptions of Cypress data sheet designations are presented here to highlight their presence and
definitions.
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The Advance Information designation indicates that Cypress Semiconductor Corp. is developing one or
more specific products, but has not committed any design to production. Information presented in a
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discontinue. Cypress Semiconductor Corp. therefore places the following conditions upon Advance
Information content:
“This document contains information on one or more products under development at Cypress
Semiconductor Corp. The information is intended to help you evaluate this product. Do not design in
this product without contacting the factory. Cypress Semiconductor Corp. reserves the right to
change or discontinue work on this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Cypress
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Cypress product(s)
described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
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When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
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applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Cypress product(s)
described herein. Cypress Semiconductor Corp. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change.
However, typographical or specification corrections, or modifications to the valid combinations
offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
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S6AE102A_DS405-00029-0v02-E, July 31, 2015
v1.2
S6AE102A / S6AE103A
Energy Harvesting PMIC for Wireless Sensor Node
Data Sheet (Preliminary)
1.
Description
The S6AE102A/103A is a power management IC (PMIC) for energy harvesting that is built into circuits of
solar cells connected in series, dual output power control circuits, output capacitor storage circuits, power
switching circuits of primary batteries, a LDO, a comparator and timers. Super-low-power operation is
possible using a consumption current of only 280 nA and startup power of only 1.2 μW. As a result, even
slight amounts of power generation can be obtained from compact solar cells under low-brightness
environments of approximately 100 lx.
This IC stores power generated by solar cells to an output capacitor using built-in switch control, and it turns
on the power switching circuit while the capacitor voltage is within a preset maximum and minimum range for
supplying energy to a load. The output power control circuit has 2 outputs, and 1 of 2 outputs can control On
and OFF of the power gating circuit using interrupt signal. The output capacitor storage circuits have 2
capacitor connection circuit for a storage of system load and a storage of surplus power, and if the power
generated from solar cells is enough, the power is stored to the capacitor of surplus power storage. If the
power generated from solar cells is not enough, energy can also be supplied in the same way as solar cells
from the capacitor of surplus power storage or connected primary batteries for auxiliary power.
This IC has also an independent LDO. The LDO can provide stable voltage that a sensor requires. And also
an independent comparator which can make voltage comparison signal output a lot of flexibility is built in.
Also, an overvoltage protection (OVP) function is built into the input pins of the solar cells, and the open
voltage of solar cells is used by this IC to prevent an overvoltage state.
The S6AE102A/103A is provided as a battery-free wireless sensor node solution that is operable by
super-compact solar cells or non-disconnect energy harvesting based wireless sensor node solution with the
capacitor of surplus storage or primary batteries for auxiliary power
Publication Number S6AE102A_DS405-00029
Revision 0.2
Issue Date July 31, 2015
This document states the current technical specifications regarding the Cypress product(s) described herein. The Preliminary status of this document indicates that product
qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this
document may be revised by subsequent versions or modifications due to changes in technical specifications.
CONFIDENTIAL
v1.2
D a t a S h e e t
2.
Features
 Operation input voltage range
− Solar cell power
− Primary battery power















3.
( P r e l i m i n a r y )
: 2.0V to 5.5 V
: 2.0V to 5.5 V
Adjustable output voltage range
: 1.1V to 5.2V
Low-consumption current
: 280 nA
Minimum input power at startup
: 1.2 μW
Low-consumption current LDO
: 400 nA
Low-consumption current Timer
: 30 nA
Low-consumption current comparator
: 20 nA (S6AE103A only)
Hybrid control of solar cell and primary battery with power path control
Solar powered power control without battery
System power reduction control with power gating
Power gating control with interrupt signal
Power gating control with timer (S6AE103A only)
Hybrid storage system for a storage of system load and a storage of surplus power
Power supply and switch control signal output for external path switch control
Input overvoltage protection
: 5.4V
Compact QFN-20/QFN-24 package
: 4 mm × 4 mm
Applications






4
CONFIDENTIAL
Energy harvesting power system with a very small solar cell
®
Bluetooth Smart sensor
Wireless HVAC sensor
Wireless lighting control
Security system
Smart home / Building / Industrial wireless sensor
S6AE102A_DS405-00029-0v02-E, July 31, 2015
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Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Description ..................................................................................................................................... 3
Features ......................................................................................................................................... 4
Applications .................................................................................................................................... 4
Product Lineup ............................................................................................................................... 7
Packages ........................................................................................................................................ 7
Pin Assignment............................................................................................................................... 8
Pin Descriptions.............................................................................................................................. 9
Block Diagram .............................................................................................................................. 10
Absolute Maximum Ratings .......................................................................................................... 12
Recommended Operating Conditions........................................................................................... 13
Electrical Characteristics .............................................................................................................. 14
Functional Description .................................................................................................................. 17
12.1 Power Supply Control........................................................................................................ 17
12.2 Power Gating .................................................................................................................... 28
12.3 Discharge ......................................................................................................................... 33
12.4 SW_CNT Control............................................................................................................... 33
12.5 General-Purpose Comparator ........................................................................................... 33
12.6 LDO
......................................................................................................................... 34
12.7 Over Voltage Protection (OVP Block)................................................................................ 34
Application Circuit Example and Parts list .................................................................................... 35
Application Note ........................................................................................................................... 38
14.1 Setting the Operation Conditions ...................................................................................... 38
Usage Precaution ......................................................................................................................... 40
RoHS Compliance Information ..................................................................................................... 40
Ordering Information..................................................................................................................... 40
Package Dimensions .................................................................................................................... 41
Major Changes ............................................................................................................................. 43
Figures
Figure 6-1 Pin Assignment of S6AE102A ................................................................................................... 8
Figure 6-2 Pin Assignment of S6AE103A ................................................................................................... 8
Figure 8-1 Block Diagram of S6AE102A .................................................................................................. 10
Figure 8-2 Block Diagram of S6AE103A ................................................................................................... 11
Figure 12-1 VDD Input Power Operation.................................................................................................. 19
Figure 12-2 VBAT Input Power Operation ................................................................................................ 21
Figure 12-3 VDD/VBAT Input Power Operation ........................................................................................ 23
Figure 12-4 VDD/VSTORE2 Input Power Operation ................................................................................ 25
Figure 12-5 VSTORE2 Input Power Operation......................................................................................... 27
Figure 12-6 Power Gating Operation (VDD Input Power) ......................................................................... 31
Figure 12-7 Power Gating Operation (VBAT Input Power) ....................................................................... 32
Figure 12-8 OVP Operation ...................................................................................................................... 34
Figure 13-1 Application Circuit Example of S6AE102A ............................................................................ 35
Figure 13-2 Application Circuit Example of S6AE103A ............................................................................ 36
Figure 14-1 Setting of Output Voltage (VOUT1, VOUT2) ......................................................................... 38
Figure 14-2 Setting of LDO Output Voltage (VOUT_LDO) ....................................................................... 39
Figure 18-1 Package Dimensions of S6AE102A (VNF020) ...................................................................... 41
Figure 18-2 Package Dimensions of S6AE103A (VNF024) ...................................................................... 42
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Tables
Table 7-1 Pin Descriptions .......................................................................................................................... 9
Table 11-1 Electrical Characteristics (System Overall) ............................................................................. 14
Table 11-2 Electrical Characteristics (Consumption Current) ................................................................... 15
Table 11-3 Electrical Characteristics (Switch) ........................................................................................... 15
Table 11-4 Electrical Characteristics (LDO) .............................................................................................. 16
Table 11-5 Electrical Characteristics (Timer) ............................................................................................ 16
Table 12-1 VINT Pin Voltage .................................................................................................................... 17
Table 12-2 Power Gating Operation Mode ............................................................................................... 28
Table 12-3 General-Purpose Comparator Operation ................................................................................ 33
Table 12-4 LDO Operation Mode.............................................................................................................. 34
Table 13-1 Parts List................................................................................................................................. 37
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4.
( P r e l i m i n a r y )
Product Lineup
Function
Product Name
S6AE102A
Pin count
20
24
Power supply voltage range
2.0V to 5.5 V
Output voltage range
1.1V to 5.2V
Output channel
2ch
LDO
1ch
Overvoltage protection (OVP)
5.
S6AE103A
VDD pin
Timer
1unit
3units
Comparator
−
1ch
S6AE102A
S6AE103A
VNF020
○
−
VNF024
−
○
Packages
Product Name
Package
○: Available
Note:
− See "18. Package Dimensions" for detailed information on each package.
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6.
( P r e l i m i n a r y )
Pin Assignment
Figure 6-1 Pin Assignment of S6AE102A
VBAT
VINT
VSTORE2
AGND
VDD
(TOP VIEW)
20
19
18
17
16
15 FB_LDO
VOUT1 １
14 VOUT_LDO
VSTORE1 2
VOUT2 3
13 VIN_LDO
CIN0 5
11 SET_VOUTH
8
9
10
SET_VOUTFB
ENA_LDO
7
STBY_LDO
6
INT
12 SET_VOUTL
SW_CNT
CIN2 4
(S6AE102A / VNF020)
Figure 6-2 Pin Assignment of S6AE103A
VBAT
VINT
VSTORE2
AGND
ENA_COMP
VDD
(TOP VIEW)
24
23
22
21
20
19
18 FB_LDO
VOUT1 １
17 VOUT_LDO
VSTORE1 2
VOUT2 3
16 VIN_LDO
CIN0 6
13 COMPP
8
9
10
11
12
SET_VOUTFB
SW_CNT/CMPOUT
7
COMPM
14 SET_VOUTH
ENA_LDO
CIN1 5
STBY_LDO
15 SET_VOUTL
INT
CIN2 4
(S6AE103A / VNF024)
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D a t a S h e e t
7.
( P r e l i m i n a r y )
Pin Descriptions
Table 7-1 Pin Descriptions
Pin No.
Pin Name
I/O
1
VOUT1
O
Output voltage pin
2
2
VSTORE1
O
Storage output pin
3
3
VOUT2
O
Output voltage pin
4
4
CIN2
O
−
5
CIN1
O
5
6
CIN0
O
−
7
SW_CNT/COMPOUT
O
VOUT1 switch interlocking output pin / Comparator output pin
6
−
SW_CNT
O
VOUT1 switch interlocking output pin
7
8
INT
I
S6AE102A
S6AE103A
1
Description
Timer time 2 (T2) setting pin(for connecting capacitor)
For the pin setting, refer to "Table 12-2 Power Gating Operation Mode"
Timer time 1 (T1) setting pin(for connecting capacitor)
For the pin setting, refer to "Table 12-2 Power Gating Operation Mode"
Timer time 0 (T0) setting pin(for connecting capacitor)
For the pin setting, refer to "Table 12-2 Power Gating Operation Mode"
Event driven mode control pin
For the pin setting, refer to "Table 12-2 Power Gating Operation Mode"
(when being not used, connect this pin to AGND )
LDO operation mode setting pin
8
9
STBY_LDO
I
For the pin setting, refer to "Table 12-4 LDO Operation Mode"
(when being not used, connect this pin to AGND )
LDO output control pin
9
10
ENA_LDO
I
For the pin setting, refer to "Table 12-4 LDO Operation Mode"
(when being not used, connect this pin to AGND )
Comparator Input pin
−
11
COMPM
I
10
12
SET_VOUTFB
O
−
13
COMPP
I
11
14
SET_VOUTH
I
VOUT1, VOUT2 output voltage setting pin (for connecting resistor)
12
15
SET_VOUTL
I
VOUT1, VOUT2 output voltage setting pin (for connecting resistor)
13
16
VIN_LDO
I
14
17
VOUT_LDO
O
15
18
FB_LDO
I
16
19
VDD
I
(when being not used, leave this pin open )
Reference voltage output pin (for connecting resistor)
Comparator input pin
(when being not used, leave this pin open )
LDO power input pin
(when being not used, connect this pin to AGND )
LDO output pin
LDO output voltage setting pin (for connecting resistor)
(when being not used, leave this pin open )
Solar cell input pin
(when being not used, leave this pin open )
Comparator control pin
−
20
ENA_COMP
I
For the pin setting, refer to "12.5 General-Purpose Comparator"
17
21
AGND
−
Ground pin
18
22
VSTORE2
O
Storage output pin
19
23
VINT
O
Internal circuit storage output pin
20
24
VBAT
I
(when being not used, connect this pin to AGND )
July 31, 2015, S6AE102A_DS405-00029-0v02-E
CONFIDENTIAL
Primary battery input pin
(when being not used, leave this pin open )
9
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D a t a S h e e t
8.
( P r e l i m i n a r y )
Block Diagram
Figure 8-1 Block Diagram of S6AE102A
Primary
Battery
Power supply block
VBAT
+
SW4
SW6
VOUT2
to system Load
Discharge
SW1
VDD
to system Load
Discharge
SW10
Solar
Cell
VOUT1
VSTORE1
SW2
VSTORE2
SW5
SW7
SW3
VINT
SW8
OVP block
VDD
+
VOVPH / VOVPL
-
SW9
VINT
Power supply
for internal circuit
VIN_LDO
ENA_LDO
VSTORE2
STBY_LDO
VVST2H / VVST2L
SET_VOUTFB
on/off
+
-
SET_VOUTH
+
VSTORE1
Discharge
+
-
INT
CIN0
FB_LDO
Control
-
SET_VOUTL
VOUT_LDO
LDO
1.15V
VSTORE1
LDO block
stby
SW_CNT
VINT
Timer block
Timer0 T0TM
CIN2
AGND
10
CONFIDENTIAL
S6AE102A_DS405-00029-0v02-E, July 31, 2015
v1.2
D a t a S h e e t
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Figure 8-2 Block Diagram of S6AE103A
Primary
Battery
Power supply block
VBAT
+
SW4
SW6
to system Load
VSTORE1
SW2
VSTORE2
SW5
SW7
SW3
VINT
SW8
OVP block
VDD
+
VOVPH / VOVPL
-
SW9
VINT
Power supply
for internal circuit
VIN_LDO
ENA_COMP
ENA_LDO
STBY_LDO
SET_VOUTFB
VSTORE2
+
VVST2H / VVST2L
-
on/off
VSTORE1
+
VSTORE1
+
Discharge
SW_CNT/COMPOUT
VINT
VINT
Timer block
Comparator block
Timer0 T0TM
CIN1
Timer1 T1TM
CIN2
Timer2 T2TM
FB_LDO
Control
-
CIN0
VOUT_LDO
LDO
-
SET_VOUTL
LDO block
stby
1.15V
SET_VOUTH
INT
VOUT2
Discharge
SW1
VDD
to system Load
Discharge
SW10
Solar
Cell
VOUT1
on/off
+
-
COMPP
COMPM
AGND
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9.
( P r e l i m i n a r y )
Absolute Maximum Ratings
Parameter
Power supply voltage (*1)
Symbol
VMAX
Condition
VDD, VBAT, VIN_LDO pin
Rating
Unit
Min
Max
−0.3
+6.9
V
−0.3
+6.9
V
−
0.1
mV/µs
−
1400 (*2)
mW
−55
+125
°C
SET_VOUTH, SET_VOUTL, INT,
Signal input voltage (*1)
VINPUTMAX
ENA_LDO, STBY_LDO,
ENA_COMP,
COMPP, COMPM pin
VDD slew rate
VSLOPE
Power dissipation (*1)
PD
Storage temperature
TSTG
VDD pin
Ta ≤+ 25°C
−
*1: When AGND = 0V
*2: θja (wind speed 0m/s): +50°C/W
Warning:
1. Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of
these ratings.
12
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10. Recommended Operating Conditions
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Power supply voltage 1 (*1)
VVDD
VDD pin
2.0
3.3
5.5
V
Power supply voltage 2 (*1)
VVBAT
VBAT pin
2.0
3.0
5.5
V
Power supply voltage 3 (*1)
VVINLDO
VIN_LDO pin
2.0
−
5.3
V
INT, ENA_LDO,
STBY_LDO,
Signal input voltage (*1)
VINPUT
ENA_COMP,
VINT pin
−
−
COMPP, COMPM
voltage
V
(*2)
pin
VOUT1 setting resistance
RVOUT
Sum of R1, R2, R3
10
−
−
MΩ
LDO setting resistance
RLDO
Sum of R4, R5
100
−
−
MΩ
VDD capacitance
CVDD
VDD pin
10
−
−
µF
VINT capacitance
CVINT
VINT pin
1
−
−
µF
VOUT upper limit setting voltage
VSYSH
VSTORE1 pin
1.25
−
5.2
V
VOUT lower limit setting voltage
General-purpose comparator
input voltage
LDO output setting voltage
VSYSL
VCOMP
VSETLD
VSTORE1 pin
1.1
−
0.2
−
VSYSH
×0.9
V
VINT pin
COMPP,
COMPM pins
voltage −1.5
V
(*2)
VOUT_LDO pin
1.3
−
5.0
V
Timer time 0
T0
CIN0 pin, Timer 0
0.1
−
3600
s
Timer time 1
T1
CIN1 pin, Timer 1
0.1
−
3600
s
Timer time 2
T2
CIN2 pin, Timer 2
0.1
−
3600
s
Operating ambient temperature
Ta
−40
−
+85
°C
−
*1: When AGND = 0V
*2: Refer to "Table 12-1 VINT Pin Voltage".
Warning:
1. The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on
this data sheet. If you are considering application under any conditions other than listed herein, please
contact sales representatives beforehand.
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11. Electrical Characteristics
The following electrical characteristics are the values excluding the effect of external resistors and external
capacitors.
Table 11-1 Electrical Characteristics (System Overall)
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
−
−
1.2
µW
VDD pin, Ta = +25°C, VVOUTH setting = 3V,
Minimum Input power
in start-up
WSTART
By applying 0.4 µA to VDD, when VOUT1
reaches 3V×95% after the point when VDD
reaches 3V.
Power detection voltage
VDETH
Power undetection voltage
VDETL
1.30
1.55
2.00
V
VDD, VBAT ,VINT, VSTORE2 pins
1.15
1.45
1.90
V
Power detection hysteresis
VDETHYS
Power detection voltage 2
−
0.1
−
V
VDETH2
VDD pin,
2.0
2.1
2.2
V
Power undetection voltage 2
VDETL2
When connecting a capacitor to VSTORE2
1.9
2.0
2.1
V
Power detection hysteresis 2
VDETHYS2
−
0.1
−
V
−
VSYSH
−
V
−
V
VOUT upper limit voltage
VVOUTH
Input power reconnect voltage
VVOUTM
VOUT lower limit voltage
VVOUTL
VSTORET2 upper limit voltage
VVST2H
VSTORET2 lower limit voltage
VVST2L
OVP detection voltage
VOVPH
OVP release voltage
VOVPL
OVP detection hysteresis
OVP protection current
pin
VSTORE1 pin,
VOUT1 Load = 0 mA, VOUT2 Load = 0 mA
VSTORE1 pin,
VOUT1 Load = 0 mA, VOUT2 Load = 0 mA
VSTORE1 pin,
VIH
Input voltage
VIL
VOH
×0.95
VSYSL
−
V
VSTORE2 pin, VVOUTH setting>2.4V
−
VVOUTH
−
V
VSTORE2 pin, VVOUTH setting≤2.4V
2.3
2.4
2.5
V
VSTORE2 pin, VVOUTH setting>2.4V
−
VVOUTL
−
V
VSTORE2 pin, VVOUTH setting≤2.4V
2.2
2.3
2.4
V
5.2
5.4
5.5
V
5.1
5.3
5.4
V
−
0.1
−
V
6
−
−
mA
VDD pin
VDD pin input current
INT, ENA_LDO, STBY_LDO, ENA_COMP
pins
INT, ENA_LDO, STBY_LDO, ENA_COMP
pins
SW_CNT/COMPOUT, SW_CNT pins,
Load = 2 µA
Output voltage
VOL
VVOUTH
−
VOUT1 Load = 0 mA, VOUT2 Load = 0 mA
VOVPHYS
IOVP
−
SW_CNT/COMPOUT, SW_CNT pins,
Load = 2 µA
1.1
−
0
−
0.7×VINT
pin voltage
−
(*1)
VINT pin
voltage (*1)
0.3
VINT pin
voltage (*1)
V
V
V
0.3×VINT
0
−
pin voltage
V
(*1)
*1: Refer to "Table 12-1 VINT Pin Voltage".
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Table 11-2 Electrical Characteristics (Consumption Current)
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Parameter
Symbol
Condition
Value
Unit
Min
Typ
Max
−
280
420
nA
−
680
1020
nA
−
300
450
nA
VDD pin input current,
Energy driven mode (*2), SW2 = OFF, VDD = 3V,
open VBAT pin, open VSTORE2 pin,
Consumption current 1
IQIN1
VIN_LDO = GND, INT = GND, ENA_COMP = GND,
ENA_LDO = GND, STBY_LDO = GND,
VVOUTH setting = 1.25V, Ta = +25°C,
SET_VOUTFB resistance˃100 MΩ,
VOUT1 Load = 0 mA, VOUT2 Load = 0 mA
Consumption current 2
IQIN2
Consumption current 3
IQIN3
Sum of IQIN1 and IINLD2 (LDO operation current)
ENA_LDO = VINT (*1)
Sum of IQIN1 and comparator operation current,
ENA_COMP = VINT (*1)
*1: Refer to "Table 12-1 VINT Pin Voltage".
*2: Refer to "12.2 Power Gating"
Table 11-3 Electrical Characteristics (Switch)
VDD ≥ 3V, VBAT ≥ 3V, VINT ≥ 3V, VSTORE2 ≥ 3V, VVOUTL ≥ 3V, VSTORE1 ≥ VVOUTL
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Switch resistance 1
RON1
SW1, In connection of VSTORE1 pin and VOUT1 pin
−
1.5
2.5
Ω
Switch resistance 2
RON2
SW2, In connection of VDD pin and VSTORE1 pin
−
50
100
Ω
Switch resistance 3
RON3
SW3, In connection of VSTORE2 pin and VSTORE1 pin
−
50
100
Ω
Switch resistance 4
RON4
SW4, In connection of VBAT pin and VOUT1 pin
−
1.5
2.5
Ω
Switch resistance 5
RON5
SW5, In connection of VDD pin and VSTORE2 pin
−
50
100
Ω
Switch resistance 6
RON6
SW6, In connection of VSTORE1 pin and VOUT2 pin
−
1.5
2.5
Ω
Switch resistance 10
RON10
SW10, In connection of VBAT pin and VOUT2 pin
−
1.5
2.5
Ω
Discharge resistance
RDIS
VOUT1, VOUT2 pins
−
1
2
kΩ
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Table 11-4 Electrical Characteristics (LDO)
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Parameter
Symbol
Value
Condition
Min
VSETLD
VOUT_LDO pin, Load = 0.01 mA
Output voltage
Input/output voltage difference
(Normal mode)
Input/output voltage difference
(Standby mode)
Maximum output current
(Normal mode)
Maximum output current
(Standby mode)
Line regulation
Load regulation
(Normal mode)
Load regulation
(Standby mode)
OVP operation current
LDO consumption current
(Normal mode)
LDO consumption current 2
(Standby mode)
VOUTLD
VDELLD1
VDELLD2
IOUTLD1
IOUTLD2
LINELD
LOADLD1
LOADLD2
ILIMLD
IINLD1
×0.95
VOUT_LDO pin, Ta = +25°C, VIN_LDO = VOUTLD+1V
VSETLD
STBY_LDO = VINT (*1) , Load = 0.01 mA
×0.98
Between VIN_LDO and VOUT_LDO pins,
STBY_LDO = VINT (*1), Load ≤ 1 mA
Between VIN_LDO and VOUT_LDO pins,
STBY_LDO = AGND, Load ≤ 0.001 mA
VOUT_LDO pin, (VIN_LDO−VOUTLD×1.05) > 0.7V
STBY_LDO = VINT (*1)
VOUT_LDO pin, (VIN_LDO−VOUTLD×1.05) > 0.7V,
STBY_LDO = AGND
VOUT_LDO pin, VIN_LDO = (VOUTLD×1.05+0.7V) to 5.3V
VOUT_LDO pin,
STBY_LDO = VINT (*1) , Load = 1 mA to 10 mA
VOUT_LDO pin,
STBY_LDO = AGND, Load = 0.001 mA to 0.1 mA
VOUT_LDO pin,
STBY_LDO = VINT (*1)
Sum of VINT and VIN_LDO input current, Ta = +25°C,
STBY_LDO = VINT (*1), Load = 0 mA
Typ
−
−
Max
VSETLD
×1.05
VSETLD
×1.02
Unit
V
V
0.3
−
−
V
0.3
−
−
V
10
−
−
mA
0.1
−
−
mA
−
−
50
mV
−
−
50
mV
−
−
50
mV
−
50
100
mA
−
6
9
µA
−
400
600
nA
−
60
120
nA
−
1
2
kΩ
Sum of VINT and VIN_LDO input current, Ta = +25°C,
IINLD2
STBY_LDO = AGND, Load = 0 mA,
VOUT_LDO resistance > 100 MΩ, VOUTLD setting = 1.3V
OFF current
IOFFLD
Discharge resistance
RDISLD
VIN_LDO pin, Ta = +25°C,
ENA_LDO = AGND
VOUT_LDO pin,
1.35 ≤ V OUTLD ≤ 5.0V
*1: Refer to "Table 12-1 VINT Pin Voltage".
Table 11-5 Electrical Characteristics (Timer)
(Unless specified otherwise, these are the electrical characteristics under the recommended operating environment.)
Parameter
Accuracy
Each timer
consumption current
16
CONFIDENTIAL
Symbol
Condition
TATM
Ta = +25°C
IQTM
Timer 0, Timer 1, Timer 2, Ta = +25°C
Value
Unit
Min
Typ
Max
−15
−
+15
%
−
30
45
nA
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12. Functional Description
12.1 Power Supply Control
This IC can operate by two input power supplies, namely, the solar cell voltage VDD and the primary battery
voltage VBAT.
When a capacitor is connected to the VSTORE2 pin, the surplus power of the solar cell accumulates in this
capacitor and operates as input power supply.
The input power (from solar cell or VSTORE2 capacitor) is accumulated once in the capacitor connected to
the VSTORE1 pin. When the voltage of the VSTORE1 pin reaches the threshold or higher, the power gating
switch connects VSTORE1 to VOUT1 and VOUT2.
The input power (from primary battery) is not accumulated in the capacitor connected to the VSTORE1 pin.
When the voltage of the VBAT pin reaches the threshold or higher, the switch for power gating connects
VBAT to VOUT1 and VOUT2.
The VINT pin voltage is output as shown in the table below.
Table 12-1 VINT Pin Voltage
VDD Voltage
VBAT Voltage
(Solar Cell)
(Primary Battery)
VDETL or less
VDETL or less
VDETH or higher
VDETL or less
VDETH or higher
VSTORE2 Voltage
VSTORE1 Voltage
VINT Voltage
(Output)
VDETL or less
−
−
VDETH or higher
−
VSTORE2
VDETL or less
−
VBAT
VDETH or higher
VDETL or less
VDETH or higher
VDETL or less
VDETH or higher
VDETH or higher
VVOUTL detection (*1)
VBAT
VVOUTH detection (*2)
VSTORE2
−
VDD
−
VDD
VVOUTL detection (*1)
VBAT
VVOUTH detection (*2)
VDD
VVOUTL detection (*1)
VBAT
VVOUTH detection (*2)
VDD
*1: Value from when voltage at VSTORE1 pin reaches VVOUTL voltage until it reaches VVOUTH voltage
*2: Value from when voltage at VSTORE1 pin reaches VVOUTH voltage until it reaches VVOUTL voltage
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VDD Input Power Operation
This section describes operation when the VDD pin is set as the input power (Figure 12-1).
When the voltage of the VBAT pin falls to the power undetection voltage (VDETL = 1.45 V) or less, and a
capacitor is not connected to the VSTORE2 pin.
[1] When the voltage of the VDD pin reaches the power detection voltage (VDETH = 1.55V) or higher, the
switch (SW2) connects VDD and VSTORE1 (path S1). Also, when the voltage of the VDD pin falls to the
power undetection voltage (VDETL = 1.45V) or less, SW2 disconnects the path S1.
[2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the
SET_VOUTH pin, SW2 disconnects the path S1. Also, the VOUT1 switch (SW1) connects VSTORE1 and
VOUT1, and the VOUT2 switch (SW6) connects VSTORE1 and VOUT2 (path S2).
[3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (VVOUTM) or less, SW2
connects the path S1 (path S1+S2).
[4] In addition, when the voltage falls to the threshold value (VVOUTL) or less that was set by the SET_VOUTL
pin, SW1 and SW6 disconnect the path S2.
[5] When SW1 and SW6 disconnects the path S2, the discharge function is activated.
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Figure 12-1 VDD Input Power Operation
(a) Internal Operation Diagram
S6AE102A / S6AE103A
VOUT1
SW1
VOUT2
SW6
Solar
Cell
S2
VDD
VSTORE1
SW2
S1
SW7
VINT
(b) Operation Sequence
[1]
[2]
[3]
[4]
[V]
VDD
VINT
[5]
Open Voltage
of Solar Cell
VDD
VDETH
VDETL
VINT
[V]
S2
VVOUTH
VVOUTM
VSTORE1
S1
S1
+
S2
S2
S1
+
S2
S1
VVOUTL
S1
+
S2
S2
S1
[V]
VOUT1
VOUT2
[mA]
VOUT1
VOTU2
Load
time
SW1,SW6
SW2
SW7
off
off
on
on
off
on
on
off
off
on
on
on
off
VDETH
VDETL
VVOUTH
VVOUTM
VVOUTH
VVOUTL
VVOUTM
VVOUTH
VVOUTM
VVOUTH
VDETH(VINT)
VDETH(VDD)
July 31, 2015, S6AE102A_DS405-00029-0v02-E
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on
off
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VBAT Input Power Operation
This section describes operation when the VBAT pin is set as the input power (Figure 12-2).
When the voltage of the VDD pin falls to the power undetection voltage (VDETL = 1.45 V) or less, and a
capacitor is not connected to the VSTORE2 pin.
[1] When the voltage of the VBAT pin reaches the power detection voltage (VDETH = 1.55V) or higher, the
switch (SW4) connects VBAT and VOUT1, and the switch (SW10) connects VBAT and VOUT2 (path S3).
[2] When the voltage of the VBAT pin falls to the power undetection voltage (VDETL = 1.45V) or less, SW4 and
SW10 disconnects the path S3.
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Figure 12-2 VBAT Input Power Operation
(a) Internal Operation Diagram
S6AE102A / S6AE103A
Primary
Battery
VOUT1
SW4
S3
VBAT
VOUT2
SW10
+
VINT
SW9
(b) Operation Sequence
[1]
[2]
[V]
VBAT
VINT
VBAT
VDETH
VDETL
VINT
[V]
VOUT1
VOUT2
time
SW4,SW10
SW9
off
off
CONFIDENTIAL
off
on
off
VDETL(VBAT,VINT)
VDETH(VINT)
VDETH(VBAT)
July 31, 2015, S6AE102A_DS405-00029-0v02-E
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VDD/VBAT Input Power Operation
This section describes operation when the VDD and VBAT pins are set as the input power (Figure 12-3).
A capacitor is not connected to the VSTORE2 pin.
[1] When the voltage of the VDD pin and the VBAT pin reaches the power detection voltage (V DETH = 1.55 V)
or higher and the voltage of the VSTORE1 pin is not detected as the VOUT upper limit voltage (VVOUTH),
the VOUT1 switch (SW4) connects VBAT and VOUT1 and the VOUT2 switch (SW10) connects VBAT and
VOUT2 (path S3). Also, the switch (SW2) connects VDD and VSTORE1 (path S1).
[2] When the voltage of the VSTORE1 pin reaches the VOUT upper limit voltage (VVOUTH) or higher, SW4
and SW10 disconnect path S3.Also, the VOUT1 switch (SW1) connects VSTORE1 and VOUT1 and the
VOUT2 switch (SW6) connects VSTORE1 and VOUT2 (path S2).
[3] When the voltage of the VSTORE1 pin falls to the input power reconnect voltage (V VOUTM) or less, SW2
connects path S1 (path S1 + S2).
[4] When the voltage of the VSTORE1 pin falls to the VOUT lower limit voltage (V VOUTL) or less, switches
SW1 and SW6 disconnect path S2. Also, SW4 and SW10 connect path S3 (path S1 + S3).
[5] When the voltage of the VBAT pin falls to the power undetection voltage (V DETL = 1.45 V) or less, switches
SW4 and SW10 disconnect path S3.
[6] When the voltage of the VSTORE1 pin reaches the VOUT upper limit voltage (VVOUTH) or higher, SW1
and SW6 connect path S2 (path S2).
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Figure 12-3 VDD/VBAT Input Power Operation
Primary
Battery
(a) Internal Operation Diagram
VBAT
S6AE102A / S6AE103A
SW4
+
S3
SW9
SW10
VOUT1
SW1
VOUT2
SW6
Solar Cell
S2
VDD
VSTORE1
SW2
S1
SW7
VINT
(b) Operation Sequence
[2]
[V]
[3]
[5]
[4]
[6]
[1]
VINT
VBAT
VINT
VDETH
VDETL
VBAT
[V]
VDD
VDETH
VDETL
[V]
VVOUTH
VVOUTM
VSTORE1
S1
+
S3
S2
VVOUTL
S1
+
S3
S1
+
S2
S1
S2
[V]
VOUT1
VOUT2
VBAT
VSTORE1
VBAT
VSTORE1
time
SW1,SW6
Off
On
Off
SW4, SW10
On
Off
On
SW2
On
Off
SW7
Off
On
Off
On
SW9
On
Off
On
Off
Off
VVOUTH
VDETL
VVOUTL
CONFIDENTIAL
Off
On
VVOUTM
VVOUTH
July 31, 2015, S6AE102A_DS405-00029-0v02-E
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VDD/VSTORE2 Input Power Operation
This section describes operation when the VDD pin is set as the input power (Figure 12-4).
A capacitor is connected to the VSTORE2 pin.
[1] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the
SET_VOUTH pin, switch (SW5) connects VDD and VSTORE2 (path S4).
[2] When the voltage of the VDD pin falls to the power undetection voltage 2 (V DETL2 = 2.0 V) or less, SW5
disconnects path S4. When it reaches the power detection voltage 2 (V DETH2 = 2.1 V) or higher, SW5
connects path S4.
[3] When the voltage of the VSTORE1 pin falls to the threshold value (V VOUTM) or less that was set by the
SET_VOUTH pin, SW5 disconnects path S4.
[4] When the voltage of the VSTORE2 pin reaches the VSTORE2 upper limit voltage (V VST2H) or higher, SW5
disconnects path S4.
24
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Figure 12-4 VDD/VSTORE2 Input Power Operation
(a) Internal Operation Diagram
S6AE102A / S6AE103A
VOUT1
SW1
VOUT2
SW6
Solar
Cell
S2
VDD
VSTORE1
SW2
SW5
SW7
[1]
[3] [1]
[2]
[V]
S1
VSTORE2
S4
VINT
(b) Operation Sequence
[3] [1]
[4]
Open Voltage
of Solar Cell
VDD
VDETH2
VDETL2
VDETH
VDETL
VDD
VINT
VINT
[V]
VVOUTH
VVOUTM
VSTORE1
S1
S1
+
S2
S2
S2
S1
+
S2
S2
[V]
VVST2H
VVST2L
VSTORE2
S4
S4
S4
[V]
VOUT1
VOUT2
time
SW1,SW6
Off
SW2
Off
SW5
Off
SW7
Off
On
On
Off
On
VVOUTH
VVOUTH
VVOUTM
VVOUTH
CONFIDENTIAL
VVOUTM
VVOUTH
July 31, 2015, S6AE102A_DS405-00029-0v02-E
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VSTORE2 Input Power Operation
This section describes operation when the VSTORE2 pin is set as the input power (Figure 12-5).
A capacitor is connected to the VSTORE2 pin.
[1] When the voltage of the VDD pin falls to the power undetection voltage (V DETL = 1.45 V) or less, and
when the voltage of the VSTORE1 pin falls to the threshold value (VVOUTM) or less set by SET_VOUTH pin,
switch (SW3) connects VSTORE2 and VSTORE1 (path S5 + S2).
[2] When the voltage of the VSTORE1 pin reaches the threshold value (VVOUTH) or higher that was set by the
SET_VOUTH pin, SW3 disconnects path S5.
[3] When the voltage of the VSTORE2 pin falls to the VSTORE2 lower limit voltage (V VST2L) or less, SW3
disconnects path S5.
[4] When the voltage of the VSTORE1 pin falls to the threshold value (V VOUTL) or less that was set by the
SET_VOUTL pin, the VOUT1 switch (SW1) disconnects VSTORE1 and VOUT1 and the VOUT2 switch
(SW6) disconnects VSTORE1 and VOUT2.
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S6AE102A_DS405-00029-0v02-E, July 31, 2015
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Figure 12-5 VSTORE2 Input Power Operation
(a) Internal Operation Diagram
S6AE102A / S6AE103A
VOUT1
SW1
VOUT2
SW6
Solar
Cell
S2
VDD
VSTORE1
SW2
S5
SW3
VSTORE2
SW5
SW8
VINT
SW7
(b) Operation Sequence
[1] [2]
[V]
[1] [3]
[1] [2]
[4]
VINT
VDD
VINT
Open Voltage
of Solar Cell
VDD
VDETH
VDETL
[V]
S5
+
S2
VVOUTH
VVOUTM
VVOUTL
VSTORE1
S2
S5
+
S2
S5
+
S2
S2
S2
S2
[V]
VVST2H
VVST2L
VSTORE2
[V]
VOUT1
VOUT2
time
SW1,SW6
On
SW2,SW5
Off
SW3
Off
SW7
On
Off
SW8
Off
On
Off
On
Off
VVOUTL
VVST2L
VVOUTM
CONFIDENTIAL
VVOUTH
VVOUTM
VVOUTH
VVOUTM
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12.2 Power Gating
This IC has a power gating function for external systems.
The power gating function is to control supplying power accumulated in VSTORE1 or power from VBAT to
external system loads connected to VOUT1 and VOUT2 by internal switches.
The power gating function has four operating modes.
This IC determines the power gating operation mode through the connection status of pins CIN1 and CIN2
at the power detection (VDETH = 1.55 V) timing of the VINT pin.
Table 12-2 Power Gating Operation Mode
Each Pin Settings
CIN1(*1)
CIN2
Open
Open
Operation Mode
Energy driven mode
Open
Connect AGND
Event driven mode 1
Connect capacitor (*2)
Open
Event driven mode 2 (*1)
Connect capacitor (*2)
Connect capacitor (*2)
Timer driven mode (*1)
*1: S6AE103A only
*2: For the timer time setting, refer to"14.1 Setting the Operation Conditions".
Energy Driven Mode
1) VDD input power operation
Switches are controlled by monitoring VSTORE1 voltage.
Internal switches (SW1 and SW6) connect VSTORE1 and VOUT1, as well as VSTORE1 and VOUT2 from
when VOUT upper limit voltage (VVOUTH) is detected until VOUT lower limit (VVOUTL) is detected.
2) VBAT input power operation
Switches are controlled by monitoring VBAT voltage.
Internal switches (SW4 and SW10) connect VBAT and VOUT1, as well as VBAT and VOUT2 from when
power detection voltage (VDETH) is detected until power undetection voltage (VDETL) is detected.
Event Driven Mode 1
Switches are controlled in the same way as the energy driven mode to supply to VOUT1. The INT input
controls switching to supply to VOUT2. While the timer 0 is counting, the flag output (T0TM) disables internal
switching controls through INT input. The timer time (T0) is set by the capacitor connected to CIN0.
1) VDD input power operation
Internal switch (SW6) connects VSTORE1 to VOUT2 while INT is high level. Detecting upper limit voltage
(VVOUTH) is a trigger to start timer 0, after the timer time reaches count (T0), it stops and is reset.
2) VBAT input power operation
Internal switch (SW10) connects VBAT to VOUT2 while INT is high level. Detecting power detection
voltage (VDETH) is a trigger to start timer 0, after the timer time reaches count (T0), it stops and is reset.
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Event Driven Mode 2
Switches are controlled in the same way as the energy driven mode to supply to VOUT1. The INT input and
the flag output (T1TM) control switching to supply to VOUT2.
1) VDD input power operation
Detecting upper limit voltage (VVOUTH) is a trigger to start counter, after the timer time reaches count (T0),
timer 0 stops and is reset. When the timer time (T0) is set by the capacitor connected to CIN0.
The highness of INT is a trigger to start counter, after the timer time reaches count (T1), timer 1 stops and
is reset. When the timer time (T1) is set by the capacitor connected to CIN1.
For each timer, they are reset by detecting VOUT lower limit voltage (V VOUTL).
Internal switch (SW6) connects VSTORE1 to VOUT2 while timer 1 is counting. Disables internal switching
controls through INT input while the timer 0 is counting.
2) VBAT input power operation
Detecting power detection voltage (VDETH) is a trigger to start counter, after the timer time reaches count
(T0), timer 0 stops and is reset. When the timer time (T0) is set by the capacitor connected to CIN0.
The highness of INT is a trigger to start counter, after the timer time reaches count (T1), timer 1 stops and
is reset. When the timer time (T1) is set by the capacitor connected to CIN1.
Each timer is reset by detecting power undetection voltage (VDETL).
Internal switch (SW10) connects VBAT to VOUT2 while timer 1 is counting. Disables internal switching
controls through INT input while the timer 0 is counting.
Timer Driven Mode
The timer 0 flag output (T0TM), timer 1 flag output (T1TM), and timer 2 flag output (T2TM) control switching
to supply to VOUT1 and VOUT2
1) VDD input power operation
This section describes the operation of each timer.
Detecting upper limit voltage (VVOUTH) the first time is a trigger to start counter, after the timer time reaches
count (T0), timer 0 stops and is reset. From the second time onward, the completion of timer 2 is a trigger
to start the count, after the timer time reaches count (T0), the timer stops and is reset. When the timer time
(T0) is set by the capacitor connected to CIN0.
Detecting upper limit voltage (VVOUTH) the first time is a trigger to start counter, after the timer time reaches
count (T1), timer 1 stops and is reset. From the second time onward, the completion of timer 2 is a trigger
to start the count, after the timer time reaches count (T1), the timer stops and is reset. When the timer time
(T1) is set by the capacitor connected to CIN1.
The completion of timer 1 is a trigger to start counter, after the timer time reaches count (T2), timer 2 stops
and is reset. When the timer time (T2) is set by the capacitor connected to CIN2.
Timer 0 and 1 are reset by detecting VOUT lower limit voltage (V VOUTL). Timer 2 is reset by power
undetection voltage (VDETL) of VINT.
This section describes the operation of VOUT1.
Internal switch (SW1) connects VSTORE1 to VOUT1 while timer 1 is counting. Internal switch (SW1)
disconnects VSTORE1 and VOUT1 while timer 2 is counting.
This section describes the operation of VOUT2.
Internal switch (SW6) connects VSTORE1 to VOUT2 while timer 1 is counting after timer 0 ends. Internal
switch (SW6) disconnects VSTORE1 and VOUT2 while timer 2 is counting.
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2) VBAT input power operation
This section describes the operation of each timer.
Detecting power detection voltage (VDETH) the first time is a trigger to start counter, after the timer time
reaches count (T0), timer 0 stops and is reset. From the second time onward, the completion of timer 2 is
a trigger to start the count, after the timer time reaches count (T0), the timer stops and is reset. When the
timer time (T0) is set by the capacitor connected to CIN0.
Detecting power detection voltage (VDETH) the first time is a trigger to start counter, after the timer time
reaches count (T1), timer 1 stops and is reset. From the second time onward, the completion of timer 2 is
a trigger to start the count, after the timer time reaches count (T1), the timer stops and is reset. When the
timer time (T1) is set by the capacitor connected to CIN1.
The completion of timer 1 is a trigger to start counter, after the timer time reaches count (T2), timer 2 stops
and is reset. When the timer time (T2) is set by the capacitor connected to CIN2.
Each timer is reset by detecting power undetection voltage (VDETL).
This section describes the operation of VOUT1.
Internal switch (SW4) connects VBAT to VOUT1 while timer 1 is counting. Internal switch (SW4)
disconnects VBAT and VOUT1 while timer 2 is counting.
This section describes the operation of VOUT2.
Internal switch (SW10) connects VBAT to VOUT2 while timer 1 is counting after timer 0 ends. Internal
switch (SW10) disconnects VBAT and VOUT2 while timer 2 is counting.
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Figure 12-6 Power Gating Operation (VDD Input Power)
Energy driven mode (S6AE102A / S6AE103A)
VSTORE1 < VVOUTL
From after VSTORE1 reaches VVOUTH until VVOUTL
VSTORE1 < VVOUTL
SW1
OFF
ON
ON
SW6
OFF
ON
OFF
Event driven mode 1 (S6AE102A / S6AE103A)
VSTORE1 < VVOUTL
INT
L
From after VSTORE1 reaches VVOUTH until VVOUTL
H
H
H
H
START
T0TM
OFF
SW6
OFF
H
STOP
RESET
T0
SW1
VSTORE1 < VVOUTL
ON
OFF
OFF
ON
OFF
ON
OFF
Event driven mode 2 (S6AE103A)
VSTORE1 < VVOUTL
INT
L
H
From after VSTORE1 reaches VVOUTH until VVOUTL
H
H
START
T0TM
H
STOP
RESET
T0
H
START
T1TM
T1
SW1
OFF
SW6
OFF
VSTORE1 < VVOUTL
START
STOP
RESET
T1
RESET
OFF
ON
OFF
ON
OFF
ON
OFF
Timer driven mode (S6AE103A)
VSTORE1 < VVOUTL
From after VSTORE1 reaches VVOUTH until VVOUTL
START
T0TM
T0
START
T1TM
START
STOP
RESET
T0
T2TM
OFF
SW6
OFF
ON
OFF
ON
July 31, 2015, S6AE102A_DS405-00029-0v02-E
OFF
STOP
RESET
STOP
RESET
START
T1
T2
SW1
CONFIDENTIAL
START
STOP
RESET
START
T1
VSTORE1 < VVOUTL
STOP
RESET
T2
ON
RESET
OFF
ON
OFF
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Figure 12-7 Power Gating Operation (VBAT Input Power)
Energy driven mode (S6AE102A / S6AE103A)
VBAT < VDETL
From after VBAT reaches VDETH until VDETL
VBAT < VDETL
SW4
OFF
ON
ON
SW10
OFF
ON
OFF
Event driven mode 1 (S6AE102A / S6AE103A)
VBAT < VDETL
INT
L
From after VBAT reaches VDETH until VDETL
H
H
H
H
START
T0TM
OFF
SW10
OFF
H
STOP
RESET
T0
SW4
VBAT < VDETL
ON
OFF
OFF
ON
OFF
ON
OFF
Event driven mode 2 (S6AE103A)
VBAT < VDETL
INT
L
H
From after VBAT reaches VDETH until VDETL
H
H
START
T0TM
H
STOP
RESET
T0
H
START
T1TM
T1
SW4
OFF
SW10
OFF
VBAT < VDETL
START
STOP
RESET
T1
RESET
OFF
ON
OFF
ON
OFF
ON
OFF
Timer driven mode (S6AE103A)
VBAT < VDETL
From after VBAT reaches VDETH until VDETL
START
T0TM
T0
START
T1TM
START
STOP
RESET
T0
T2TM
OFF
SW10
OFF
CONFIDENTIAL
ON
OFF
ON
OFF
STOP
RESET
STOP
RESET
START
T1
T2
SW4
32
START
STOP
RESET
START
T1
VBAT < VDETL
STOP
RESET
T2
ON
RESET
OFF
ON
OFF
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12.3 Discharge
This IC has VOUT1 pin, VOUT2 pin, and VOUT_LDO pin discharge functions.
While SW1 and SW4 are OFF, the discharge circuit function between the VOUT1 pin and GND works. The
VOUT1 pin's power is discharged to GND level.
While SW6 and SW10 are OFF, the discharge circuit function between the VOUT2 pin and GND works. The
VOUT2 pin's power is discharged to GND level.
While LDO is OFF, the discharge circuit function between the VOUT_LDO pin and GND works. The
VOUT_LDO pin's power is discharged to GND level.
12.4 SW_CNT Control
This IC has a control signal output function for external switching.
S6AE102A
The signal, which is interlocked with the switch for VOUT1, is output at the SW_CNT pin. While the VBAT
input power is operating, it is interlocked to the ON/OFF control of the switch (SW4) between VBAT and
VOUT1. While the VDD and VSTORE2 input power is operating, it is interlocked to the ON/OFF control of
the switch (SW1) between VSTORE1 and VOUT1. Output to the SW_CNT pin is High while SW1 or SW4 is
ON.
S6AE103A
While ENA_COMP pin is Low, the signal, which is interlocked with the switch for VOUT1, is output at the
SW_CNT/COMPOUT pin. While the VBAT input power is operating, it is interlocked to the ON/OFF control
of the switch (SW4) between VBAT and VOUT1. While the VDD and VSTORE2 input power is operating, it is
interlocked to the ON/OFF control of the switch (SW1) between VSTORE1 and VOUT1. Output to the
SW_CNT/COMPOUT pin is High while SW1 or SW4 is ON.
12.5 General-Purpose Comparator
S6AE103A
This IC has one general-purpose comparator.
It compares the voltage at the COMPP pin and the COMPM pin while ENA_COMP pin is High, and outputs
the results to the SW_CNT/COMPOUT pin.
Table 12-3 General-Purpose Comparator Operation
Each Pin Settings
ENA_COMP
L
H
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COMPP, COMPM
SW_CNT/COMPOUT (Output)
−
Operation described in "12.4 SW_CNT Control"
COMPP < COMPM
L
COMPP > COMPM
H
"COMPP = COMPM" is prohibited
L or H
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12.6 LDO
This IC has one LDO with VIN_LDO pin as a power supply.
The output voltage is set by the resistance value at VOUT_LDO pin and FB_LDO pin connection. The
discharge function operates while output is stopped.
Also, there are two operating modes, standby mode for operating at low power consumption, and normal
mode in which the maximum output current is 10 mA, which are set at the STBY_LDO pin.
Refer to the following table for the LDO operating modes.
Table 12-4 LDO Operation Mode
Each Pin Settings
ENA_LDO
STBY_LDO
L
L
H
H
LDO Output State
Output is stopped
L
Standby mode
H
Normal mode
12.7 Over Voltage Protection (OVP Block)
This IC has an input overvoltage protection (OVP) function for the VDD pin voltage.
When the VDD pin voltage reaches the OVP detection voltage (VOVPH = 5.4V) or higher, the OVP current
(IOVP) from the VDD pin is drawn in for limiting the increase in the VDD pin voltage for preventing damage
to the IC. Also, when the OVP release voltage (VOVPL = 5.3V) or less is reached, drawing-in of the OVP
current is stopped.
Figure 12-8 OVP Operation
[V]
VDD
[mA]
Open Voltage
of Solar Cell
VOVPH
VOVPL
IOVP
IOVP
time
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13. Application Circuit Example and Parts list
Figure 13-1 Application Circuit Example of S6AE102A
Primary +
Battery
VBAT
VOUT1
VDD
VOUT2
D1
C1
Solar
Battery
Sensor
VSTORE2
VSTORE1
C3
VINT
C2
C4
MCU/Sensor
MCU/Sensor
MCU/Sensor
STBY_LDO
ENA_LDO
INT
SET_VOUTFB
R1
R2
R3
VIN_LDO
S6AE102A
MCU + RF
SET_VOUTH
VOUT_LDO
SET_VOUTL
FB_LDO
CIN0
C6
C9
R4
R5
C5
Sensor
SW_CNT
CIN2
AGND
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Figure 13-2 Application Circuit Example of S6AE103A
Primary +
Battery
VBAT
VOUT1
VDD
VOUT2
D1
C1
Solar
Battery
Sensor
VSTORE2
VSTORE1
C3
VINT
C2
C4
MCU/Sensor
MCU/Sensor
MCU/Sensor
ENA_COMP
STBY_LDO
ENA_LDO
INT
SET_VOUTFB
R1
R2
R3
Sensor
Sensor
VIN_LDO
C9
S6AE103A
MCU + RF
SET_VOUTH
VOUT_LDO
SET_VOUTL
FB_LDO
COMPP
COMPM
R4
R5
C5
Sensor
SW_CNT/COMPOUT
CIN0
C6
CIN1
C7
CIN2
C8
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Table 13-1 Parts List
Part Number
Item
Specification
Remarks
C1
Ceramic capacitor
10 µF
−
C2
Ceramic capacitor
1 µF
−
C3
Ceramic capacitor
100 µF
−
C4
Ceramic capacitor
0.5F
−
C5
Ceramic capacitor
22 µF
−
C6
Ceramic capacitor
150 pF (*1)
−
C7
Ceramic capacitor
330 pF (*1)
−
C8
Ceramic capacitor
330 pF (*1)
−
C9
Ceramic capacitor
1 µF
−
R1
Resistor
33 MΩ (*2)
−
R2
Resistor
12 MΩ (*2)
−
R3
Resistor
47 MΩ (*2)
−
R4
Resistor
39 MΩ (*3)
−
R5
Resistor
68 MΩ (*3)
−
D1
Diode
−
−
*1: Timer time 0 (T0) ≈ 0.26s by the use of C6, Timer time 1 and 2 (T1, T2) ≈ 0.57s by the use of C7 or C8.
*2: VOUT upper limit voltage (VVOUTH) ≈ 3.32V, VOUT lower limit voltage (VVOUTL) ≈ 2.65V.
*3: LDO output voltage (VOUTLD) ≈ 1.81V
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14. Application Note
14.1 Setting the Operation Conditions
Setting of Output Voltage (VOUT1, VOUT2)
The VOUT1 and VOUT2 output voltage of this IC can be set by changing the resistors connecting the
SET_VOUTH pin and SET_VOUTL pin. This is because the VOUT upper limit voltage (VVOUTH) and VOUT
lower limit voltage (VVOUTL) are set based on the connected resistors. The SET_VOUTFB pin outputs a
reference voltage for setting the VOUT upper limit voltage and VOUT lower limit voltage. The voltages
applied to the SET_VOUTH and SET_VOUTL pins are produced by dividing this reference voltage outside
the IC.
Figure 14-1 Setting of Output Voltage (VOUT1, VOUT2)
S6AE102A / S6AE103A
SET_VOUTFB
R1
R2
SET_VOUTH
SET_VOUTL
R3
The VOUT upper limit voltage (VVOUTH) and VOUT lower limit voltage (VVOUTL) can be calculated using the
formulas below.
VOUT upper limit voltage
57.5 × (R2 + R3)
VVOUTH [V] =
11.1 × (R1 + R2 + R3)
VOUT lower limit voltage
57.5 × R3
VVOUTL [V] =
11.1 × (R1 + R2 + R3)
The characteristics when the total for R1, R2, and R3 is 10 MΩ or more (consumption current 1 is 100 MΩ or
more) are shown in "11. Electrical Characteristics".
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Setting of LDO Output Voltage (VOUT_LDO)
The VOUT_LDO output voltage of this IC can be set by changing the resistors connecting the VOUT_LDO
pin and FB_LDO pin.
Figure 14-2 Setting of LDO Output Voltage (VOUT_LDO)
S6AE102A / S6AE103A
VOUT_LDO
FB_LDO
R4
R5
The LDO output voltage (VOUTLD) can be calculated using the formula below.
VOUTLD [V] =
1.15 × (R4 + R5)
R5
Setting of Timer Time (T0, T1, T2)
The timer times 0, 1, and 2 (T0, T1, and T2) are set according to the capacitance value at the connections
between the CIN0, CIN1, and CIN2 pins and the AGND pin.
The timer time 0 (T0), timer time 1 (T1) and timer time 2 (T2) can be calculated using the formula below.
T [s] = 1.734 × 109 × C [F]
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15. Usage Precaution
Printed circuit board ground lines should be set up with consideration for common
impedance.
Take appropriate measures against static electricity.
− Containers for semiconductor materials should have anti−static protection or be made of conductive
material.
− After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
− Work platforms, tools, and instruments should be properly grounded.
− Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.
Do not apply negative voltages.
The use of negative voltages below −0.3V may make the parasitic transistor activated to the LSI, and can
cause malfunctions.
16. RoHS Compliance Information
This product has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated
biphenyls (PBB), and polybrominated diphenyl ethers (PBDE).
17. Ordering Information
Part Number
Package
S6AE102A0DGN1B000 (*1)
Plastic QFN-20 (0.5 mm pitch), 20-pin
S6AE102A0DEN1B000 (*2)
(VNF020)
S6AE103A0DGN1B000 (*1)
Plastic QFN-24 (0.5 mm pitch), 24-pin
S6AE103A0DEN1B000 (*2)
(VNF024)
*1: Commercial Sample (CS)
*2: Engineering Sample (ES)
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18. Package Dimensions
Figure 18-1 Package Dimensions of S6AE102A (VNF020)
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Figure 18-2 Package Dimensions of S6AE103A (VNF024)
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19. Major Changes
Page
Section
Change Results
Preliminary 0.1
-
-
Initial release
-
Typo error correction
Preliminary 0.2
-
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Cypress will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any
semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention
of over-current levels and other abnormal operating conditions. If any products described in this document represent goods
or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the
US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective
government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Cypress
product under development by Cypress. Cypress reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
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warranty, express, implied, or statutory. Cypress assumes no liability for any damages of any kind arising out of the use of
the information in this document.
®
Copyright © 2015 Cypress Semiconductor Corp. All rights reserved. Cypress , the Cypress logo, Spansion , the Spansion
®
®
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TM
logo, MirrorBit , MirrorBit Eclipse , ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks
and registered trademarks of Cypress Semiconductor Corp. in the United States and other countries. Other names used are
for informational purposes only and may be trademarks of their respective owners.
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