RENESAS HD74CBT3244

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April 1, 2003
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HD74CBT3244
Octal FET Bus Switch
ADE-205-643 (Z)
Preliminary
Rev. 0
August 2001
Description
The HD74CBT3244 provides eight bits of high speed TTL-compatible bus switching in a standard ’244
device pinout. The low on state resistance of the switch allows connections to be made with minimal
propagation delay. The device is organized as two 4-bit low impedance switches with separate output
enable (OE) inputs. When OE is low, the switch is on, and data can flow from port A to port B, or vice
versa. When OE is high, the switch is open, and the high impedance state exists between the two ports.
Features
• Standard ’244 type pinout.
• Minimal propagation delay through the switch.
• 5 Ω switch connection between two ports.
• TTL-compatible input levels.
• Ultra low quiescent power.
-Ideally suited for notebook applications.
HD74CBT3244
Function Table
Input OE
Function
L
A port = B port
H
Disconnect
H:
L:
High level
Low level
Pin Arrangement
1OE
1
20 VCC
1A1
2
19 2OE
2B4
3
18 1B1
1A2
4
17 2A4
2B3
5
16 1B2
1A3
6
15 2A3
2B2
7
14 1B3
1A4
8
13 2A2
2B1
9
12 1B4
GND
10
11 2A1
(Top view)
Rev.0, Aug. 2001, page 2 of 9
HD74CBT3244
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
VCC
−0.5 to 7.0
V
VI
−0.5 to 7.0
V
Input clamp current
IIK
−50
mA
VI < 0
Continuous output current
IO
128
mA
VO = 0 to VCC
Continuous current through
VCC or GND
ICC or IGND
±100
mA
Maximum power dissipation
*2
at Ta = 25°C (in still air)
PT
757
mW
Storage temperature
Tstg
−65 to 150
°C
Supply voltage range
Input voltage range
Notes:
*1
Conditions
TSSOP
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded even if the input and output clamp-current
ratings are observed.
2. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
4.5
5.5
V
Input voltage range
VI
0
5.5
V
Output voltage range
VI/O
0
5.5
V
Input transition rise or fall rate
∆t / ∆v
0
5
ns / V
Operating free-air temperature
Ta
−40
85
°C
Conditions
VCC = 4.5 to 5.5 V
Note: Unused or floating inputs must be held high or low.
Rev.0, Aug. 2001, page 3 of 9
HD74CBT3244
Block Diagram
1A1
2
18
1B1
•
•
•
1A4
1OE
2A1
•
•
•
8
12
1B4
1
11
9
2B1
•
•
•
2A4
2OE
•
•
•
17
19
Rev.0, Aug. 2001, page 4 of 9
3
2B4
HD74CBT3244
DC Electrical Characteristics
(Ta = −40 to 85°C)
Item
Symbol
VCC (V)
Min
Typ
Clamp diode voltage
VIK
4.5

Input voltage
VIH
4.5 to 5.5
VIL
RON
On-state switch
*2
resistance
*1
Max
Unit
Test conditions

−1.2
V
IIN = −18 mA
2.0


V
4.5 to 5.5


0.8
4.5

5
7
4.5

5
7
VIN = 0 V,
IIN = 30 mA
4.5

10
15
VIN = 2.4 V,
IIN = 15 mA
Ω
VIN = 0 V,
IIN = 64 mA
Input current
IIN
0 to 5.5


±1.0
µA
VIN = 5.5 V or GND
Off-state leakage
current
IOZ
5.5


±1.0
µA
0 ≤ A, B ≤ VCC
Quiescent supply
current
ICC
5.5


3
µA
VIN = VCC or GND,
IO = 0 mA
Increase in ICC
*3
per input
∆ICC
5.5


2.5
mA
One input at 3.4 V,
other inputs at VCC or
GND
Notes:
For condition shown as Min or Max use the appropriate values under recommended operating
conditions.
1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.
2. Measured by the voltage drop between the A and B terminals at the indicated current through the
switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.
3. This is the increase in supply current for each input that is at the specified TTL voltage level
rather than VCC or GND.
Capacitance
(Ta = 25°C)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
Test conditions
Control input
capacitance
CIN
5.0

3.5

pF
VIN = 0 or 3 V
Input / output
capacitance
CI/O (OFF)
5.0

5

pF
VO = 0 or 3 V
OE = VCC
Note: This parameter is determined by device characterization is not production tested.
Rev.0, Aug. 2001, page 5 of 9
HD74CBT3244
Switching Characteristics
(Ta = −40 to 85°C)
•
VCC = 5.0±0.5 V
Test
conditions
FROM
(Input)
TO
(Output)
ns
CL = 50 pF
RL = 500 Ω
A or B
B or A
8.9
ns
CL = 50 pF
RL = 500 Ω
OE
A or B
7.4
ns
CL = 50 pF
RL = 500 Ω
OE
A or B
Item
Symbol
Min
Max
Unit
Propagation delay
*1
time
tPLH
tPHL

0.25
Enable time
tZH
tZL
1.0
Disable time
tHZ
tLZ
1.0
Note:
1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the
switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
CL = 50 pF
500 Ω
Load circuit for outputs
Symbol
S1
t PLH / tPHL
OPEN
t ZH / t HZ
OPEN
t ZL / t LZ
7V
Note: 1. CL includes probe and jig capacitance.
Rev.0, Aug. 2001, page 6 of 9
HD74CBT3244
Waveforms – 1
tr
tf
90 %
1.5 V
Input
3V
90 %
1.5 V
10 %
10 %
t PLH
GND
t PHL
V OH
1.5 V
Output
1.5 V
V OL
Waveforms – 2
tf
tr
90 %
Output
Control
3V
90 %
1.5 V
1.5 V
10 %
t ZL
10 %
GND
t LZ
3.5 V
Waveform - A
1.5 V
V OL + 0.3 V
t ZH
t HZ
V OH - 0.3 V
Waveform - B
V OL
V OH
1.5 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform - A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.0, Aug. 2001, page 7 of 9
HD74CBT3244
Package Dimensions
As of January, 2001
Unit: mm
6.50
6.80 Max
11
1
10
4.40
20
0.65
*0.22 +0.08
−0.07
0.20 ± 0.06
1.0
0.13 M
6.40 ± 0.20
*Dimension including the plating thickness
Base material dimension
Rev.0, Aug. 2001, page 8 of 9
+0.03
−0.04
0° − 8° 0.50 ± 0.10
0.07
0.10
*0.17 ± 0.05
0.15 ± 0.04
1.10 Max
0.65 Max
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
TTP-20DA


0.07 g
HD74CBT3244
Disclaimer
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copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 5.0
Rev.0, Aug. 2001, page 9 of 9