M62050P/FP 3 V Supply System Reset with Watchdog Timer REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Description The M62050P/FP is a voltage threshold detector designed for detection of 3 V supply voltage and generation of a system reset pulse. It is suitable for microcontroller systems. The IC, a supervisor of the MCU operations, dissipates low current of 0.6 mA (Typ) during normal operations of the MCU systems. It has two selectable threshold voltages, which allows applying it to a high precision system design. Features • • • • Watchdog timer (supervisor for two system voltages) Power-on reset timer Low current consumption: 0.6 mA (Typ, VCC = 3 V) Wide supply voltage range: VCC(max) = 7 V Application • Supervisor for microcontroller systems Recommended Operating Condition • Recommended supply voltage: 3 V Block Diagram – + S + – R Q + – 1 WD R Q S S R Q 2 TC REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 1 of 11 3 RST1 4 GND – + 5 Ct1 6 VCC – + 7 RST2 8 ADJ M62050P/FP Pin Arrangement M62050P M62050FP 8 ADJ WD 1 7 RST2 TC 2 RST1 3 6 VCC GND 4 5 Ct1 (Top view) Outline: PRDP0008AA-A (8P4) [P] PRSP0008DE-C [FP] (recommend) PRSP0008DA-A (8P2S-A) [FP] (not recommend for new design) Pin Description Pin No. 1 Symbol WD Functional Description Input for watchdog timer 2 3 TC RST1 Time set for reset timer and watchdog timer Pin that outputs reset signal when abnormal signal is input to WD pin 4 5 GND Ct1 GND Capacitor installation pin for delay time setting 6 7 VCC RST2 Power supply Pin that outputs reset signal when power supply voltage becomes abnormal 8 ADJ Selection between two detection voltages Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Symbol Rating Unit Conditions Supply voltage Input voltage VCC VIN 7 –0.3 to +7 V V Output voltage Output current VOUT IOUT 15 10 V mA Power dissipation Pd 625 440 mW 8-pin DIP 8-pin SOP Thermal derating Kθ 6.25 4.4 mW/°C Ta ≥ 25°C Operating temperature Storage temperature Topr Tstg –20 to +75 –55 to +125 °C °C REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 2 of 11 8-pin DIP 8-pin SOP M62050P/FP Electrical Characteristics (Ta = –25°C, VCC = 3 V, unless otherwise noted) DC Characteristics Test Conditions Item WD input current WD input voltage Max 250 3.0 0.8 –1 3.5 — — 0.5 5.0 2.42 2.30 120 2.72 2.60 120 2.52 2.40 120 0.5 0.5 950 Unit µA V Pin WD WD µA mA V TC TC TC V µA V RST1 RST2 VCC(1) mV V VCC(2) mV V VCC(4) mV V V µA RST1 RST2 VCC Typ Max C × 1.1 × R1 0.5 1.1 1.7 Reset timer (1) tRST(1) C × 0.5 × R1 0.2 0.5 1.1 Reset timer (2) tRST(2) 830 × C 40 83 220 3 Reset timer delay time tdRST(1) 290 × 10 × Cd * 140 290 790 Input pulse width tWDIN 3 — — Propagation delay td1 — 4 — — 2 — td2 Note: * Cd: Delay capacitor connected with Ct1 pin Unit s ms s ms s µs s µs µs µs TC output current TC input current Watchdog timer threshold voltage Output voltage Output leakage current VCC detection voltage (1) VCC detection voltage (2) VCC detection voltage (4) RST1 ON voltage RST2 ON voltage Circuit current Symbol IWD VIH VIL IOUT IIN VTH3(H) VTH3(L) VOL Ileak VTH1(H) VTH1(L) ∆VTH1 VTH2(H) VTH2(L) ∆VTH2 VTH4(H) VTH4(L) ∆VTH4 RST1 RST2 ICC Min 60 1.5 –0.3 — — — — — — 2.13 2.10 30 2.43 2.40 30 2.23 2.20 30 — — — Symbol tWD Min Typ 140 — — — 2.5 2.4 1.2 0.2 — 2.25 2.20 50 2.55 2.50 50 2.35 2.30 50 — — 600 VIN = 3V VIN = 1.0V VOUT = 2.6V IOUT = 1mA VOUT = 3V VCCL→H VCCH→L ∆VTH1 = VTH1(H) – VTH1(L) VCCL→H VCCH→L ∆VTH2 = VTH2(H) – VTH2(L) VCCL→H VCCH→L ∆VTH4 = VTH4(H) – VTH4(L) VCC = 1.2V, RL = 4.7kΩ VCC = 1.2V, RL = 4.7kΩ AC Characteristics Test Conditions Item Watchdog timer REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 3 of 11 Pin RST1 C = 0.1µF, R1 = 10kΩ RST1 C = 0.1µF, R1 = 10kΩ RST1 C = 0.1µF, R1 = 10kΩ RST1 Cd = 0.001µF WD RST1 RST2 M62050P/FP Operating Description Timing Chart 1 (When the delay capacitor is not connected with Ct1 pin) VTH1 VTH2(H) VTH1(H) VTH2(L) VTH1(L) VCC 0V VTH3(H) TC VTH3(L) 0V WD 0V Power ON reset timer RST1 0V RST2 0V tRST(1) (1)(2)(3) tWD tRST(2) (4) (5) (6) (7) (8) (9) (10) (11) (1): The VCC rises up to 0.8 V, then RST1 and RST2 generates low output, and rising up to 2.2 V(VTH1(H)), charge of C1 begins. (2): The VCC rises up to 2.5 V(VTH2(H)), then RST2 generates high. (3), (4): The voltage at TC pin is 1.2 V(VTH3(L) = 2/5 VCC), then RST2 generates high, when 2.4 V(VTH3(H) = 4/5 VCC), C1 is discharged and RST1 generates low. (5): The voltage at TC pin falls to 1.2 V, then RST1 generates high unless normal clock signal is entered to WD pin, RST1 repeats this operation. (6), (7): Before the voltage at TC pin reaches 4 V, if normal clock signal is entered to WD pin, low RST1 is canceled. (8), (9): In the case of entrance of abnormal signal input, as the waveform of TC pin repeats charge and discharge of RST1 alternatively, the RST1 repeats high and low output operation. (10): The VCC falls to 2.5 V(VTH2(L)), then RST2 generates low, this detective voltage has a 50 mV hysteresis. (11): When VCC goes down to 2.2 V(VTH1(L)), the status of TC pin is switched to discharge. When the potentional at TC pin is detected being VTH3(H) or VTH3(L), the status of RST1 becomes "low". (This detective voltage has a 50 mV hysteresis.) Terminology tRST(1) : Time required for TC pin potential to rise from 0 V VTH3(L) when VCC is being applied. tWD : Time required for TC pin potential to rise from VTH3(L) to VTH3(H). tRST(2) : Time required for TC pin potential to go down from VTH3(H) to VTH3(L). tdRST(1) : Time required for delay of charge with TC pin when VCC is impressed by connecting capacitor with Ct1 pin between GND. Figure 1 Timing Chart 1 REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 4 of 11 M62050P/FP Timing Chart 2 (When the delay capacitor is connected with Ct1 pin) VTH1(H) VCC 0V VTH3(H) TC VTH3(L) 0V WD 0V Power ON reset timer RST1 tdRST(1) 0V (1) (2) The following delay time will enter by the time the charge of TC pin starts when the capacitor Cd is connected with Ct1 pin. tdRST(1) = 290 × 103 × Cd Figure 2 Timing Chart 2 REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 5 of 11 M62050P/FP 1. Pin(2) (TC pin) charge time and discharge time When input to WD pin is abnormal, TC pin output waveform is as shown below: 4 ⋅V CC 5 TC 2 ⋅V CC 5 0V tWD tRST(1) ∗ Please set it within the range of 10kΩ ≤ R1 ≤ 30kΩ. tRST(2) tRST(1) = 0.51 ⋅ C ⋅ R1 tWD = 1.1 ⋅ C ⋅ R1 (charge time) VCC R1 + 1 1000 tRST(2) = 1000 ⋅ C ⋅ ln 2 V ⋅ R1 CC 1000 5 ⋅ 4 ⋅ VCC – VCC 5 (discharge time) – VCC – 2 VCC 5 R1 2 C Figure 3 Please set the time of tWD and tRST(2) within the following range. 110 µs ≤ tWD ≤ 1.1 s 8.3 µs ≤ tRST(2) ≤ 83 ms 2. Pin (1) (WD pin) input frequency, input pulse width, charge time and discharge time When input to WD pin is normal, TC pin output waveform is as shown below: Pin (2) (VCC = 3V) 2.4V (= 4 ⋅ VCC) 5 xV 1.2V (= 2 ⋅ VCC) 5 t1 t2 Input tWDIN t1 = C ⋅ R1 ⋅ ln VCC – 2 VCC 5 VCC – x (charge time) R1 + 1) ⋅ x – VCC 1000 2 V ⋅ R1 – (V – 2 V ) CC 5 CC 1000 5 CC ( t2 = 1000 ⋅ C ⋅ ln Figure 4 REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 6 of 11 (discharge time) M62050P/FP • Pin (1) (WD pin) input requirements (1) Input cycle: tWD or less (discharge should start before voltage at WD pin reaches 2.4 V.) 1 <f 1.1 ⋅ C ⋅ R1 (2) Input pulse width tWDIN: t2 or less C = 104 1ms t t1 C = 103 100µs VCC = 3V R1 = 10kΩ 50µs 0.5 ms t2 1.2 1.7 2.4 Discharge Voltage x(V) Figure 5 3. VCC detection voltage adjustment The detection voltage 2 (VTH2) can be set as shown in Table 1 by connecting ADJ pin with opening or VCC. Table 1 Detection Voltage 2 (ADJ pin) Detection Voltage 2 VTH2(H) at Opening (V) 2.55 at VCC (V) 2.35 VTH2(L) 2.50 2.30 6 6.5kΩ 8 RL 35.2kΩ + – 40kΩ 1.25V 4 Figure 6 REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 7 of 11 7 M62050P/FP Application Example M62050 1 2 3 4 5 RST1 (RESET) MCU/MPU Clock 6 7 8 RST2 (HOLD) VDD Figure 7 Application Example REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 8 of 11 M62050P/FP Typical Characteristics Detection Voltage vs. Ambient Temperature 2.6 V (8 pin = open) Detection Voltage VTH (V) TH2 (H) (L) 2.5 2.4 VTH4 (8 pin = VCC) 2.3 (H) (L) VTH1 (8 pin = open) (H) (L) 2.2 2.1 2.0 –50 –25 0 25 50 75 100 125 Ambient Temperature Ta (°C) Circuit Current vs. Supply Voltage Circuit Current ICC (mA) 3 Ta = 25°C Ta = 125°C Ta = –40°C 2 1 0 0 1 2 3 4 5 6 Supply Voltage VCC (V) REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 9 of 11 7 M62050P/FP Package Dimensions RENESAS Code PRDP0008AA-A 5 1 4 MASS[Typ.] 0.5g c *1 E 8 Previous Code 8P4 e1 JEITA Package Code P-DIP8-6.3x8.84-2.54 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 D e1 D E A A1 A2 bp b2 b3 c L A1 A A2 Reference Symbol SEATING PLANE *3 b 3 *3 b 2 bp e e L JEITA Package Code P-SOP8-4.4x4.85-1.27 RENESAS Code PRSP0008DE-C *1 Previous Code — Min Nom Max 7.32 7.62 7.92 8.7 8.9 9.1 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 0.9 1.0 1.3 1.4 1.5 1.8 0.22 0.27 0.34 15° 0° 2.29 2.54 2.79 3.0 MASS[Typ.] 0.1g F D 8 Dimension in Millimeters NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 c *2 E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Z Reference Symbol 4 1 e *3 bp x M A A2 L1 A1 θ L y Detail F REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 10 of 11 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 4.65 4.85 5.05 4.2 4.4 4.6 1.85 0.00 0.1 0.20 2.03 0.34 0.4 0.46 0.15 0.20 0.25 0° 8° 5.7 6.2 6.5 1.12 1.27 1.42 0.12 0.10 0.75 0.25 0.45 0.65 0.90 M62050P/FP JEITA Package Code P-SOP8-4.4x5-1.27 RENESAS Code PRSP0008DA-A MASS[Typ.] 0.07g E 5 *1 HE 8 Previous Code 8P2S-A F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 4 Index mark c A2 *2 A1 D L A Reference Symbol *3 e bp y D E A2 A1 A bp c Detail F HE e y L REJ03D0786-0200 Rev.2.00 Jun 15, 2007 Page 11 of 11 Dimension in Millimeters Min Nom Max 4.8 5.0 5.2 4.2 4.4 4.6 1.5 0.05 1.9 0.35 0.4 0.5 0.13 0.15 0.2 0° 10° 5.9 6.2 6.5 1.12 1.27 1.42 0.1 0.2 0.4 0.6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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