AN 166: Using High-Speed I/O Standards in APEX II Devices

®
Using High-Speed
I/O Standards in
APEX II Devices
May 2003, ver. 1.8
Application Note 166
Introduction
Recent expansion in the telecommunications market and growth in
Internet use have created a demand to move more data faster than ever.
To meet this demand, system designers are relying on solutions such as
differential signaling and interface standards such as RapidIO,
POS-PHY Level 4, or UTOPIA IV.
The APEXTM II device’s high-speed interface I/O pins offer serialization
and deserialization on a single chip to move data at high speeds. They also
utilize a state-of-the-art CMOS process that consumes far less power than
GaAs devices, the other alternative for high-speed devices.
Preliminary
Information
The following documents are available and provide information on
APEX II device high speed I/O standard features and functions. These
documents also explain how system designers can take advantage of these
standards to increase system efficiencies and bandwidth.
■
■
Application Note 157 (Using CDS in APEX II Devices) describes the
most common topologies, and how the APEX II device’s unique
clock-data synchronization (CDS) feature is applied.
Application Note 167 (Using Flexible-LVDS in APEX II Devices)
describes the function, capabilities, and implementation of the
Flexible-LVDSTM buffer.
The APEX II high-speed interface includes four I/O banks. Each highspeed I/O bank is comprised of 18 channels, offering 36 differential input
and 36 differential output channels each running up to 1 gigabit per
second (Gbps). The 72 channels combine to offer 366-Gbps throughput.
See Figure 1.
APEX II devices combine serialization, deserialization, and frequency
multiplication into one package. This combination allows APEX II devices
to transmit multiple bits of data through a reduced number of differential
transmission lines spanning large distances.
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AN-166-1.8
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Figure 1. APEX II High-Speed Interface Block Diagram
I/O Bank
I/O Bank
Receiver
PLL1
Input Clock 1
Transmitter
PLL1
True-LVDS
Channels 1 to 18
Parallel-to-Serial
Converter
True-LVDS
Channels 1 to 18
Serial-to-Parallel
Converter
Serial Data
System
Logic
I/O Bank
Serial Data
Input Clock 2
APEX II HighSpeed I/O
Standards
True-LVDS
Channels 19 to 36
Serial-to-Parallel
Converter
Receiver
PLL2
Output Clock 1
Serial Data
I/O Bank
True-LVDS
Channels 19 to 36
Parallel-to-Serial
Converter
Transmitter
PLL2
Serial Data
Output Clock 2
As demand for high-speed systems grows, the interface between systems
becomes critical. The APEX II high-speed interface offers four types of
commonly applied high-speed I/O standards: LVDS, HyperTransport,
LVPECL, and PCML.
Figures 2 and 3 show receiver input and transmitter output waveforms,
respectively, for all differential I/O standards (LVDS, 3.3-V PCML,
LVPECL, and HyperTransport technology).
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Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 2. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
±VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
+VID
p−n=0V
VID (Peak-to-Peak)
− VID
Figure 3. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
±VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
+VOD
p−n=0V
VSS (1)
− VOD
Note to Figure 3:
(1)
VSS: steady-state differential output voltage.
LVDS
LVDS is a low-voltage differential signaling, general-purpose I/O
standard. This I/O standard can transmit signals at high data rates across
a variety of interconnect media such as printed circuit board (PCB) traces,
backplanes, or cables with minimal power consumption and low noise.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
APEX II device True-LVDSTM buffers (see Figure 4) meet complex design
requirements for high data rates and low power consumption by using a
low-voltage differential signal that can travel at rates up to 1 Gbps.
Two key industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS and
ANSI/TIA/EIA-644. Although both standards have similar features, the
IEEE Std. 1596.3 SCI-LVDS standard supports a maximum data transfer
rate of only 250 megabits per second (Mbps). APEX II devices are
designed to meet the ANSI/TIA/EIA-644 standard while supporting a
maximum data transfer rate of 1 Gbps. Table 1 lists the LVDS parameters.
Figure 4. LVDS Buffers
Driver
Current Source
~3.5 mA
–
Receiver
+
100
+
4
–
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Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Table 1. 3.3-V LVDS Specifications
Symbol
Parameter
Note (1)
Conditions
VCCIO
I/O supply voltage
VOD
Differential output voltage
RL = 100 Ω
∆ VOD
Change in VOD between
high and low
RL = 100 Ω
VOS
Output offset voltage
RL = 100 Ω
∆ VOS
Change in VOS between
high and low
RL = 100 Ω
VTH
Differential input threshold VCM = 1.2 V
VIN
RL
Minimum
Typical
3.135
3.3
250
1.125
1.25
Maximum
Units
3.465
V
850 (2)
mV
50
mV
1.375
V
50
mV
–100
100
mV
Receiver input voltage
range
0.0
2.4
V
Receiver differential input
resistor (external to
APEX II devices)
90
110
Ω
100
Notes to Table 1:
(1)
(2)
APEX II devices support the RapidIO and POS-PHY Level 4 interconnect standards using the LVDS I/O standard.
Maximum VOD is measured under static conditions.
HyperTransport
HyperTransport (formerly known as Lightning Data Transport, or LDT)
technology is a new high-speed, high-performance point-to-point I/O
standard for connecting integrated circuits on a motherboard. It is
primarily targeted for the IT and telecommunication industries, but any
application that requires high speed, low latency, and scalability has the
potential to take advantage of HyperTransport technology.
HyperTransport technology connections have two unidirectional pointto-point links with varied bit widths, and the clock is center-aligned with
data. The APEX II transmitter circuitry allows users to select edge-aligned
or center-aligned strobe method for each individual channel, regardless of
the I/O standard used. Table 2 lists the HyperTransport parameters.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Table 2. HyperTransport Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
I/O supply voltage
2.375
2.5
2.625
V
VOD
Differential output voltage
RL = 100 Ω
380
600
820
mV
VOCM
Output common mode
voltage
RL = 100 Ω
500
600
700
mV
VID
Differential input voltage
300
600
900
mV
VICM
Input common mode
voltage
450
600
750
mV
RL
Receiver differential input
resistor
90
100
110
Ω
LVPECL
The LVPECL I/O standard is used in telecommunications, data
communications, and clock distribution fields. It uses a positive power
supply, and has relatively small voltage swing compared to TTL I/O
standards, making LVPECL suitable for high-speed systems. Table 3
shows the LVPECL signaling characteristics.
Table 3. LVPECL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
3.135
3.3
Units
VCCIO
I/O supply voltage
3.465
V
VIL
Low-level input voltage
800
1,700
mV
VIH
High-level input voltage
2,100
VCCIO
mV
VOL
Low-level output voltage
1,450
1,650
mV
VOH
High-level output voltage
2,275
2,420
mV
VID
Differential input voltage
100
600
2,500
mV
VOD
Differential output voltage
625
800
970
mV
tR
Rise time (20 to 80%)
85
325
ps
tF
Fall time (20 to 80%)
85
325
ps
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AN 166: Using High-Speed I/O Standards in APEX II Devices
PCML
The PCML buffers provide programmable, differential current outputs
into transmission lines with 50-Ω terminations. The PCML I/O buffer
features 3.3-V operation and, similar to LVDS, consumes less power than
PECL. PCML signaling characteristics of are shown in Table 4.
Table 4. PCML Specifications
Symbol
Parameter
VCCIO
I/O supply voltage
VIL
Low-level input voltage
Conditions
Minimum
Typical
3.135
3.3
Maximum
Units
3.465
V
VCCIO –
0.3
V
VIH
High-level input voltage
VCCIO
VOL
Low-level output voltage
VCCIO –
0.6
VCCIO –
0.3
V
VOH
High-level output voltage
VCCIO –
0.3
VCCIO
V
VT
Output termination voltage
VOD
Differential output voltage
300
600
mV
V
VCCIO
450
V
tR
Rise time (20 to 80%)
85
325
ps
tF
Fall time (20 to 80%)
85
325
ps
RO
Output load
RL
Receiver differential input
resistor
APEX II HighSpeed Interface
Technology
Ω
100
45
50
55
Ω
The APEX II device’s high-speed interface combines serialization,
frequency multiplication, and deserialization all in one circuit. This allows
APEX II devices to transmit many bits of data through a reduced number
of differential transmission lines over distances greater than those that can
be achieved with a single-ended (e.g., TTL or CMOS) interface.
The designer can select the number of bits combined or multiplexed per
transmission link, resulting in a more flexible interface than with the
fixed-ratio solutions of application-specific integrated circuit (ASIC) or
application-specific standard product (ASSP) devices. A designer using
an ASIC or ASSP device must use a fixed number of high-speed channels
as well as a fixed number of serialized bits per channel. These limitations
reduce efficiency and flexibility, increase die size, and inflate the cost of
the system. In contrast, APEX II devices allow designers to select the
number of high-speed channels used and determine the best use of system
resources.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Data Stream Serialization
The APEX II high-speed interface receives parallel data from the internal
logic array. The data is latched into a parallel-in serial-out shift register in
sync with the low-frequency clock. The high-frequency clock (which is
internally generated) shifts the serial data through the shift register and
into the output driver. This is shown in Figure 5.
A phase-locked loop (PLL) generates the high-frequency clock and the
externally-driven clock. This PLL has two multiplication settings to
customize it for particular designs: W and J. The W setting governs the
relationship between the clock input and the data rate. For example, if the
clock input is 125 MHz and the data rate is 1 Gbps, then W is set to 8. The
J setting controls the width of the data bus driven into the transmitter or
out of the receiver. For example, for a 10-bit bus, J is set to 10. The W and
J factors may be independently set. For example, if 1-Gbit data is driven
into the APEX II device with a a 500-MHz clock, and the data is driven into
the logic array as a 100-MHz 10-bit bus, then W is set to 2 and J is set to 10.
Fore more details, see “PLLs & Data Manipulation” on page 10.
Figure 5. Transmitter Block Diagram in ×10 Mode
Transmitter Circuit
Parallel
Register
10
LE
Register
(1)
Serial
Register
10
txout
txclkout
APEX II
Logic Array
PLL
txclkin
×1
×W
×W/J
×1
Note to Figure 5:
(1)
8
LE: logic element.
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Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 6 illustrates the timing relationship between clock and data, when
×10 serialization is selected.
Figure 6. Transmitter Timing Diagram
Internal ×1 clock
Internal ×10 clock
Transmitter
data output
n–1
n–0
9
8
7
6
5
4
3
2
1
0
Incoming Serial Data Stream Deserialization
The system receives the serial data and clock at its input pins. The highfrequency clock (internal) shifts the serial data through the receiver’s
deserializer shift register. The data is then driven out in parallel with the
low-frequency data clock. This same low-frequency clock can drive a
global clock line to clock internal LEs. See Figure 7.
Figure 7. APEX II High-Speed Interface Deserializer in ×10 Mode
Receiver Circuit
Serial
Register
Parallel
Register
10
LE
Register
rxin
×W/J
PLL
rxclkin
×W
×W/J
×W
10
APEX II
Logic Array
×W/J
×W/J
Figure 8 illustrates the timing relationship between clock and data when
×10 deserialization is selected.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Figure 8. Receiver Timing Diagram
Internal ×1 clock
Internal ×10 clock
Receiver
data input
PLLs & Data
Manipulation
n–1
n–0
9
8
7
6
5
4
3
2
1
0
PLLs are used for clock distribution because they can perform frequency
multiplication. Designers can use PLLs to implement a high-performance
design in a system while using fewer system resources. Figure 9 illustrates
the APEX II high-speed interface PLL connections.
Figure 9. High-Speed Interface PLL Connections
VCO (1)
Clock Input
Phase
Comparator
Loop
Filter
Deserialization Factor
Controlled by J
÷J
High-Speed Interface
Circuitry and/or
Global Clock Lines (3)
Multiplication Factor
Controlled by W
TX_CLKOUT (2)
÷W
High-Speed
Interface Circuitry
Notes to Figure 9:
(1)
(2)
(3)
VCO: voltage-controlled oscillator.
The external clock output is available for TXPLL1 and TXPLL2.
The J divider output of RXPLL1 and PXPLL2 feeds global clock lines. The divider output of TXPLL1 and TXPLL2
cannot feed global clock lines.
There are four PLLs dedicated to the high-speed interface (separate from
the four general-purpose PLLs). Each is assigned to one high-speed bank,
and each PLL is programmed independently with its own multiplication
factor W and deserialization factor J, enabling interfaces such as RapidIO,
POS-PHY Level 4, or UTOPIA IV.
Each of the two receiver PLLs may be driven by their respective
differential clock input pins. The two transmitter PLLs may be driven by
one of the four global clock lines (GCLK1, GCLK2, GCLK3, and GCLK4), as
shown in Figure 10.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
While a receiver PLL output can drive the transmitter PLL input, a
general-purpose PLL output cannot drive a transmitter or receiver PLL.
This guideline is designed to limit jitter generation at the high-speed
interface. Figure 10 shows the four high-speed PLLs and their relation to
the global clock lines.
Figure 10. High-Speed Interface PLL Connection to Global Clock Lines
G6
G8
G2
G4
G3
G1
G7
G5
Transmitter PLL1
VCO
Receiver PLL1
J
RXCLK_IN1P
RXCLK_IN1N
VCO
W
W
TXCLK_OUT1P
TXCLK_OUT1N
PLL4
CLK4
PLL3
INCLK
CLK0
CLK0
CLK1
CLK1
CLK0
CLK0
CLK1
CLK1
PLL2
CLK2
INCLK
CLK3
PLL1
INCLK
INCLK
CLKLK_FBIN2
CLKLK_OUT2
CLK1
CLKLK_FBIN1
CLKLK_OUT1
Transmitter PLL2
VCO
W
Receiver PLL2
J
RXCLK_IN2P
RXCLK_IN2N
VCO
W
TXCLK_OUT2P
TXCLK_OUT2N
Several multiplication options are available, which provide for a wide
range of clock frequencies from a single clock input. The VCOs are
designed to operate within the frequency range of 200 MHz to 1 GHz,
enabling data rates from 200 Mbps to 1 Gbps.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Table 5 shows the fast PLL specifications.
Table 5. Fast PLL Specifications
Symbol
fIN
Note (1)
Parameter
CLKIN frequency
Mode
Min
Max
Units
×10
30
100
MHz
×9
33
111
MHz
×8
37.5
125
MHz
×7
42.9
143
MHz
×6
50
167
MHz
×5
60
200
MHz
×4
75
250
MHz
×2
150
500
MHz
×1
300
500
MHz
100
µs
60
%
tLOCK
Time required for PLL to acquire lock
tINDUTY
CLKIN duty cycle
tINJITTER
Cycle-to-cycle jitter for LVDS CLKIN
2% of tC
(2)
ps
(peakto-peak)
tJITTER
Cycle-to-cycle jitter for LVDS internal global or
regional CLK
0.25% of
tC (3)
ps
(RMS)
tJITTERX
Cycle-to-cycle jitter for LVDS CLKOUT pin
0.25% of
tC (3)
ps
(RMS)
60
%
40
tDUTY
Duty cycle for LVDS 1× CLKOUT pin
40
W
Multiplication factors for W counter
1, 2, 4, 5, 6, 7, 8, 9, 10 Integer
J
Multiplication factors
4
10
Integer
Notes to Table 5:
(1)
(2)
(3)
Numbers in Table 5 are preliminary.
Jitter for input frequencies of 30 to 200 MHz is 2% of tC and 100 ps for input frequencies of 200 to 500 MHz.
Jitter for output frequencies of 30 to 150 MHz is 0.25% of tC and 100 ps for output frequencies of 150 to 500 MHz.
The PLL frequency multiplier may be set individually for each one the
four high-speed interface modules, giving system designers several
options.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Clock-enable signal APEX II PLLs have a PLL_ENA pin for
enabling/disabling all of the device’s PLLs. When the PLL_ENA pin is
high, the PLL drives a clock to all its output ports. When the PLL_ENA pin
is low, the clock0 and clock1 ports are driven by the GND pin, and all
of the PLLs go out of lock. When the PLL_ENA pin goes high again, the
PLLs relock. Altera requires resetting the PLL when the dedecated
SERDES is used and the input clock signal ceases and then starts up again.
To reset the PLL, toggle the clock enable signal after the input clock has
stabilized. The individual enable port for each PLL is programmable. To
enable/disable the device PLLs with the PLL_ENA pin, connect the
inclocken port on the altclklock instance to the PLL_ENA input pin.
However, if more than one PLL is instantiated, each only one PLL’s
inclocken port must be connected to the PLL_ENA pin.
Deserialization
Factor J
APEX II devices give users many data serialization or deserialization
options in addition to a wide range of clock multiplication options. These
options are independent from the PLL multiplication. For example, users
may select frequency multiplication of 2, but select a deserialization factor
of 8.
When ×1 deserialization is selected, the high-speed interface system
directly connects the I/O registers to the logic array without using the
dedicated serializer/deserializer circuitry. When ×2 deserialization is
selected, the system uses double data rate (DDR) I/O registers to perform
deserialization.
Implementing
Half-Rate Clock
Applications
Some system designs require the relationship between data and clock to
be a 2:1 ratio. For example, the HyperTransport protocol, supports various
data rates, including 800 Mbps. This data rate requires a sourcesynchronous clock of 400 MHz.
The APEX II transmitter clock output (txclkout) frequency is always the
same as the transmitter PLL input clock frequency. Therefore, the desired
half-rate clock out frequency cannot be generated directly from the
transmitter PLL. However, an additional differential data channel may be
configured to produce the clock signal at half the data rate of the data
frequency to meet the 2:1 ratio requirement.
For example, when a system’s requirement is to transmit a total of
6.4 Gbps with a 2:1 data to clock ratio, the user may program the device
with nine high-speed channels. Eight of these channels will be used to
transmit data at 800 Mbps each (resulting in 6.4 Gbps of data
transmission). The parallel input of the ninth channel is then driven by
alternating ones and zeros, resulting in a clock signal at one half of the
data frequency, or 400 MHz.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
On the receiver side, the 400 MHz data signal is connected to the receiver
PLL’s clock input and is used to deserialize the incoming data at
800 Mbps. The multiplication factor W is set to 2, and the deserialization
factor J may be any number between 4 to 10.
Figure 11 shows the connection between the receiver and transmitter
circuits, where W = 2 and J = 8.
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Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 11. Receiver & Transmitter Circuit Connection
Transmitter Circuit
Receiver Circuit
100-MHz
8-Bit Bus
Eight 800-Mbps
Channels
8
Serial Receiver
Input at 800 Mbps
8
Clock Input
at 400 MHz
Serial-toParallel
Converter
8
8
APEX II
Logic Array
8
Data Stream
Generates
Clock (3)
PLL (1)
×W
×W/J
8
Parallelto-Serial
Converter
400-MHz
Clock
PLL (2)
×W/J
100 MHz
Notes to Figure 11:
(1)
(2)
(3)
W = 2 (800 MHz)
J = 8 (100 MHz)
W = 8 (800 MHz)
J = 8 (100 MHz)
Logic drives the ninth channel with a repeating 01010101 pattern for the external clock.
Timing Budget
Definitions &
Margin
The APEX II high-speed interface converts up to 10 bits of parallel data
lines into a single condensed serialized interface and transfers data at up
to 1 Gbps. Serializing and transferring data at high speed produces a data
period that is a fraction of the original TTL signal. Therefore, it is
important to understand the interface timing and possible constrains. This
section describes the data orientation, timing budget definitions, and
explains the margins. An example budget is provided that users can adapt
for their designs.
Data Orientation
There is a set relationship between the external clock and the incoming
data. For operation at 1 Gbps and W = 10, the external clock is multiplied
by 10 and phase-aligned by the PLL to coincide with the sampling
window of each data bit. Figure 12 shows the data bit orientation of the
×10 mode as defined in the Quartus® II software.
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Preliminary Information
Figure 12. Bit Orientation in the Quartus II Software
10 LVDS Bits
MSB
n-1
n-0
9
8
7
6
5
4
LSB
3
2
1
0
LVDS Bit Positions
Data synchronization is necessary for successful data transmission at high
frequencies. Figure 13 shows the data bit orientation for a receiver channel
operating in ×8 mode. Unlike in CDS mode, the first bit of data for the
current clock cycle is the third bit because the first two bits belong to the
previous cycle. Similar positioning exists for the most significant bits
(MSBs) and least significant bits (LSBs) after deserialization, as seen in
Table 6.
f
For more information on CDS in APEX II devices see Application Note 157
(Using CDS in APEX II Devices).
Figure 13. Bit Order for One Channel of LVDS Data
inclock/outclock
Previous Cycle
Data in/
Data out
Current Cycle
D7
MSB
D6
D5
D4
D3
Next Cycle
D2
D1
D0
LSB
Example: Sending the Data 10010110
Previous Cycle
Data in/
Data out
Current Cycle
1
MSB
16
0
0
1
0
Next Cycle
1
1
0
LSB
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Table 6 shows the conventions for LVDS bit naming.
Table 6. LVDS Bit Naming
Receiver Data Channel
Number
Altera Corporation
Internal 8-bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
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Preliminary Information
Timing Definition
Specifications are used to define the high-speed timing as described in
Table 7.
Table 7. High-Speed Timing Specifications & Terminology
High-Speed Timing Specification
Terminology
tC
High-speed receiver/transmitter input and output clock period.
fHSCLK
High-speed receiver/transmitter input and output clock frequency.
tLHT
Low-to-high transmission time.
tHLT
High-to-low transmission time.
TUI
The TUI is the timing budget allowed for skew, propagation delays, and
data sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC/w).
fHSDR
Maximum LVDS data transfer rate (fHSDR = 1/TUI).
Transmitter channel-to-channel skew TCCS is the timing difference between the fastest and slowest output
(TCCS)
edges, including tCO variation and clock skew. TCCS is measured with
respect to the clock used to generate the channel outputs.
Transmitter data-to-data skew
(TDDS)
TDDS is the timing difference between the fastest and slowest output
edges, including tCO variation and clock skew. TDDS is measured
without respect to the clock used to generate the channel outputs. Use
TDDS for applications that use a data channel for the transmit clock (e.g.,
POS-PHY Level 4).
Receiver input skew margin (RSKM)
RSKM is the timing margin between clock input and data input for user
board design, which allows for cable skew and jitter on the high-speed
PLL. RSKM = (TUI – TCCS – SW)/2.
Sampling window (SW)
This parameter defines the period of time during which the data must be
valid in order to be correctly captured. The setup and hold times
determine the ideal strobe position within the sampling window.
SW = tSU (max) – tSW (min).
Input jitter (peak-to-peak)
Peak-to-peak input jitter on high-speed PLLs.
Output jitter (RMS)
RMS output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tLOCK
Lock time for high-speed transmitter and receiver PLLs.
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AN 166: Using High-Speed I/O Standards in APEX II Devices
Table 8 shows the LVDS timing specifications as described in Figure 16
and Table 7.
Table 8. LVDS Timing Requirements
Symbol
Conditions Commercial -7 Speed Commercial -8 Speed Commercial -9 Speed
Grade (1 Gbps) (1)
Grade (840 Mbps)
Grade (640 Mbps)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Unit
Max
fLVDSCLK
(Input clock
frequency)
(2)
×10 mode
30
100
30
84
30
64
MHz
×8 mode
37.5
125
37.5
105
37.5
80
MHz
×4 mode
75
250
75
210
75
160
MHz
×2 mode
150
500
150
420
150
320
MHz
fLVDSDR
(Operation
in Mbps )
×10 mode
300
1,000
300
840
300
640
Mbps
×8 mode
300
1,000
300
840
300
640
Mbps
×4 mode
300
1,000
300
840
300
640
Mbps
×2 mode
300
1,000
300
840
300
640
Mbps
350
ps
ps
TCCS
All
TDDS
All
270
SW
300
150
200
250
400
440
440
ps
ps (peakto-peak)
Input jitter
(3)
All
2.1%
of tC
2.1%
of tC
2.1%
of tC
Output jitter
(4)
All
0.35%
of tC
0.35%
of tC
0.35% ps (RMS)
of tC
tLHT
All
350
400
450
ps
tHLT
All
350
400
450
ps
tDUTY
All
tLOCK
All
48
52
48
15
52
15
48
52
15
µs
Notes to Table 8:
(1)
(2)
(3)
(4)
For 1 Gbps operation, contact Altera Applications.
The multiplied clock divided by the J factor (× W/J) should not exceed 200 MHz.
If the input frequency is 30 to 200 MHz, jitter is 2% of tC. If the input frequency is 200 to 500 MHz, jitter is 100 ps.
If the output frequency is 30 to 150 MHz, jitter is is 0.25% of tC. If the output frequency is 150 to 500 MHz, jitter is
100 ps.
Input Timing Waveform
The functional description for serialization and deserialization is
described in previous sections. Figure 13 illustrates the essential
operations and the timing relationship between the clock cycle and the
incoming serial data.
Altera Corporation
19
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 14. Input Timing Waveform
Preliminary Information
Note (1)
Input Clock
(Differential
Signal)
Previous Cycle
bit 0
Input Data
Next
Cycle
Current Cycle
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
tsw0 (min)
MSB
tsw0 (max)
tsw1 (min)
tsw1 (max)
tsw2 (min)
tsw2 (max)
tsw3 (min)
tsw3 (max)
tsw4 (min)
tsw4 (max)
tsw5 (min)
tsw5 (max)
tsw6 (min)
tsw6 (max)
tsw7 (min)
tsw7 (max)
bit 7
LSB
Note to Figure 14:
(1)
The timing specifications are referenced at a 100-mV differential voltage.
Output Timing
The output timing waveform in Figure 15 illustrates the relationship
between the output clock and the serial output data stream.
20
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 15. Output Timing Waveform
Note (1)
Output Clock
(Differential
Signal)
Previous Cycle
Output Data
bit 0
Next
Cycle
Current Cycle
bit 1
bit 2
TPPos0 (min)
bit 3
bit 4
bit 5
bit 6
MSB
bit 7
LSB
TPPos0 (max)
TPPos1 (min)
TPPos1 (max)
TPPos2 (min)
TPPos2 (max)
TPPos3 (min)
TPPos3 (max)
TPPos4 (min)
TPPos4 (max)
TPPos5 (min)
TPPos5 (max)
TPPos6 (min)
TPPos6 (max)
TPPos7 (min)
TPPos7 (max)
Note to Figure 15:
(1)
The timing specifications are referenced at a 250-mV differential voltage.
Receiver Skew Margin
Change in a system’s environment such as temperature, media (cable,
connector, or PCB) loading effect, a receiver’s inherent setup and hold,
and internal skew all combine to reduce the sampling window for the
receiver. Timing margin between receiver’s clock input and the data input
sampling window is also known as RSKM. Figure 16 illustrates the
relationship between the parameter and the receiver’s sampling window.
Altera Corporation
21
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Figure 16. Differential High-Speed Timing Diagram & Timing Budget
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal Clock
TCCS
Receiver
Input Data
Sampling Window (SW)
RSKM
tsw (min)
TPPos (min)
Bit n
Bit n
TPPos (max)
Bit n
Internal
Clock
Falling Edge
RSKM
tsw (max)
Bit n
TCCS
TPPos (max)
Bit n+1
TPPos (min)
Bit n+1
Timing Budget
TUI
External Clock
Clock Placement
Internal Clock
Synchronization
Transmitter
Output Data
TCCS
RSKM
RSKM
TCCS/2
Receiver
Input Data
t SW(min)
SW
t SW(max)
22
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Design Example
This section describes a LVDS design example using an
APEX II-to-APEX II connection and a data transfer rate of 624 Mbps over
a 5-m cable. This design uses a 3M Corporation cable (14526-EZ5B) and
connector (10226-1A10VE). Figure 17 shows a design example of an
APEX II-to-APEX II connection with a 3M cable assembly.
Figure 17. LVDS Design Example
APEX II
Device
+
Ð
APEX II
Device
The design in Figure 17 has the following characteristics:
SW = 0.44 ns, TCCS = 0.4 ns
RSKM = (TUI – SW – TCCS) / 2 = (1.6 – 0.44 – 0.4) / 2 = 380 ps
Cable skew per meter (max) = 50 ps, connector skew (max) = 17 ps (values
obtained from 3M Corporation)
Since the True-LVDS balls are located on the outer edge of the
FineLine BGATM packages, the traces can be easily routed with a low
skew.
PCB skew = 30 ps (based on the electrical length of the PCB traces)
System skew = cable skew + connector skew + PCB skew = 50 ps/m × 5 m
+ 17 ps + 30 ps = 297 ps
Margin = RSKM – (input clock jitter + system skew) =
380 ps – (10 ps + 297 ps) = 73 ps
Because there is positive margin, the circuit will operate at the required
speed. If a longer cable is desired, there may not be sufficient margin. In
this case, the APEX II CDS circuitry can be used to increase RSKM and
assure circuit functionality.
Altera Corporation
23
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
When designing for high-speed data transfer rates, designers must
consider various factors that affect the margin for correct data sampling.
By completing the calculations described in this section, designers can
calculate the margin in high-speed designs that use APEX II devices and
calculate high-speed transfer over cables and connectors. Low-skew
cables and connectors can also improve margin and overall system
performance. The APEX II True-LVDS circuit provides low TCCS and SW
parameters that allow high-speed True-LVDS data transfers.
Switching Characteristics
Use the following timing specifications when receiving or transmitting
data at various speeds. Timing specifications for other frequencies and
serialize and deserialize factors are easily constructed.
Receiver Timing Specifications
The specifications shown in Table 9 are for fIN = 66 MHz and a
deserialization factor of 7.
Table 9. 1-to-7 Mode Receiver Window (462-Mbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tSW0
Sampling window position for bit 0
0.73
1.08
1.43
ns
tSW1
Sampling window position for bit 1
2.90
3.25
3.60
ns
tSW2
Sampling window position for bit 2
5.06
5.41
5.76
ns
tSW3
Sampling window position for bit 3
7.23
7.58
7.93
ns
tSW4
Sampling window position for bit 4
9.39
9.74
10.09
ns
tSW5
Sampling window position for bit 5
11.55
11.90
12.25
ns
tSW6
Sampling window position for bit 6
13.72
14.07
14.42
RSKM
24
0.35
ns
ns
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
The specifications shown in Table 10 are for fIN = 78 MHz and a
deserialization factor of 8.
Table 10. 1-to-8 Mode Receiver Window (622.08-Mbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tSW0
Sampling window position for bit 0
0.50
0.80
1.10
ns
tSW1
Sampling window position for bit 1
2.11
2.41
2.71
ns
tSW2
Sampling window position for bit 2
3.72
4.02
4.32
ns
tSW3
Sampling window position for bit 3
5.33
5.63
5.93
ns
tSW4
Sampling window position for bit 4
6.93
7.23
7.53
ns
tSW5
Sampling window position for bit 5
8.54
8.84
9.14
ns
tSW6
Sampling window position for bit 6
10.15
10.45
10.75
ns
tSW7
Sampling window position for bit 7
11.76
12.06
12.36
RSKM
0.30
ns
ns
The specifications shown in Table 11 are for fIN = 78 MHz and a
deserialization factor of 10.
Table 11. 1-to-10 Mode Receiver Window (840-Mbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tSW0
Sampling window position for bit 0
0.425
0.60
0.775
ns
tSW1
Sampling window position for bit 1
1.615
1.79
1.965
ns
tSW2
Sampling window position for bit 2
2.805
2.98
3.155
ns
tSW3
Sampling window position for bit 3
3.995
4.17
4.345
ns
tSW4
Sampling window position for bit 4
5.185
5.36
5.535
ns
tSW5
Sampling window position for bit 5
6.375
6.55
6.725
ns
tSW6
Sampling window position for bit 6
7.565
7.74
7.915
ns
tSW7
Sampling window position for bit 7
8.755
8.93
9.105
ns
tSW8
Sampling window position for bit 8
9.945
10.12
10.295
ns
tSW9
Sampling window position for bit 9
11.135
11.31
11.485
RSKM
Altera Corporation
0.22
ns
ns
25
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
The specifications shown in Table 12 are for fIN = 100 MHz and a
deserialization factor of 10.
Table 12. 1-to-10 Mode Receiver Window (1-Gbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tSW0
Sampling window position for bit 0
0.3
0.5
0.7
ns
tSW1
Sampling window position for bit 1
1.3
1.5
1.7
ns
tSW2
Sampling window position for bit 2
2.3
2.5
2.7
ns
tSW3
Sampling window position for bit 3
3.3
3.5
3.7
ns
tSW4
Sampling window position for bit 4
4.3
4.5
4.7
ns
tSW5
Sampling window position for bit 5
5.3
5.5
5.7
ns
tSW6
Sampling window position for bit 6
6.3
6.5
6.7
ns
tSW7
Sampling window position for bit 7
7.3
7.5
7.7
ns
tSW8
Sampling window position for bit 8
8.3
8.5
8.7
ns
tSW9
Sampling window position for bit 9
9.3
9.5
9.7
RSKM
0.4
ns
ns
Transmitter Timing Specifications
The specifications shown in Table 13 are for fIN = 66 MHz and a
serialization factor of 7.
Table 13. 1-to-7 Mode Transmitter Window (462-Mbps Transfer)
Symbol
Parameter
Minimum
TPPos0
Transmitter output pulse position for bit 0
–0.35
TPPos1
Transmitter output pulse position for bit 1
1.81
TPPos2
Transmitter output pulse position for bit 2
3.98
TPPos3
Transmitter output pulse position for bit 3
6.14
Maximum
Unit
0
0.35
ns
2.16
2.51
ns
4.33
4.68
ns
6.49
6.84
ns
TPPos4
Transmitter output pulse position for bit 4
8.31
8.66
9.01
ns
TPPos5
Transmitter output pulse position for bit 5
10.47
10.82
11.17
ns
TPPos6
Transmitter output pulse position for bit 6
12.64
12.99
13.34
TCCS
26
Typical
0.7
ns
ns
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
The specifications shown in Table 14 are for fIN = 78 MHz and a
serialization factor of 8.
Table 14. 1-to-8 Mode Transmitter Window (622.08-Mbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
TPPos0
Transmitter output pulse position for bit 0
–0.20
0.00
0.20
ns
TPPos1
Transmitter output pulse position for bit 1
1.41
1.61
1.81
ns
TPPos2
Transmitter output pulse position for bit 2
3.02
3.22
3.42
ns
TPPos3
Transmitter output pulse position for bit 3
4.62
4.82
5.02
ns
TPPos4
Transmitter output pulse position for bit 4
6.23
6.43
6.63
ns
TPPos5
Transmitter output pulse position for bit 5
7.84
8.04
8.24
ns
TPPos6
Transmitter output pulse position for bit 6
9.45
9.65
9.85
ns
TPPos7
Transmitter output pulse position for bit 7
11.05
11.25
11.45
TCCS
0.40
ns
ns
The specifications shown in Table 15 are for fIN = 78 MHz and a
serialization factor of 10.
Table 15. 1-to-10 Mode Transmitter Window (840-Mbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
TPPos0
Transmitter output pulse position for bit 0
–0.2
0.00
0.20
ns
TPPos1
Transmitter output pulse position for bit 1
0.99
1.19
1.39
ns
TPPos2
Transmitter output pulse position for bit 2
2.18
2.38
2.58
ns
TPPos3
Transmitter output pulse position for bit 3
3.37
3.57
3.77
ns
TPPos4
Transmitter output pulse position for bit 4
4.56
4.76
4.96
ns
TPPos5
Transmitter output pulse position for bit 5
5.75
5.95
6.15
ns
TPPos6
Transmitter output pulse position for bit 6
6.94
7.14
7.34
ns
TPPos7
Transmitter output pulse position for bit 7
8.13
8.33
8.53
ns
TPPos8
Transmitter output pulse position for bit 8
9.32
9.52
9.72
ns
TPPos9
Transmitter output pulse position for bit 9
10.51
10.71
10.91
TCCS
Altera Corporation
0.40
ns
ns
27
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
The specifications shown in Table 16 are for fIN = 100 MHz and a
serialization factor of 10.
Table 16. 1-to-10 Mode Transmitter Window (1-Gbps Transfer)
Symbol
Parameter
Minimum
Typical
Maximum
TPPos0
Transmitter output pulse position for bit 0
–0.175
0.00
0.175
ns
TPPos1
Transmitter output pulse position for bit 1
0.825
1.00
1.175
ns
TPPos2
Transmitter output pulse position for bit 2
1.825
2.00
2.175
ns
TPPos3
Transmitter output pulse position for bit 3
2.825
3.00
3.175
ns
TPPos4
Transmitter output pulse position for bit 4
3.825
4.00
4.175
ns
TPPos5
Transmitter output pulse position for bit 5
4.825
5.00
5.175
ns
TPPos6
Transmitter output pulse position for bit 6
5.825
6.00
6.175
ns
TPPos7
Transmitter output pulse position for bit 7
6.825
7.00
7.175
ns
TPPos8
Transmitter output pulse position for bit 8
7.825
8.00
8.175
ns
TPPos9
Transmitter output pulse position for bit 9
8.825
9.00
9.175
TCCS
High-Speed
Interface Pin
Location
28
0.35
Unit
ns
ns
APEX II high-speed interface pins are located at the edge of the die to limit
the possible mismatch between a pair of high-speed signals.
An APEX II device has eight programmable I/O banks. The four
dedicated high-speed interface blocks are incorporated into four of these
eight banks. Figure 18 shows the I/O blocks and their location relative to
the package. The True-LVDS input pins are located on the right side and
the output pins on the left side of the chip. Flexible-LVDS I/O pins are
located in I/O blocks at the top and bottom of the device.
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 18. True-LVDS & Flexible-LVDS Pins
True-LVDS
Transmitter Pins
(LVDS, LVPECL,
PCML, HyperTransport
Outputs)
Regular I/O Pins & Flexible-LVDS
Input Pins (LVDS/HyperTransport/
LVPECL Inputs)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
True-LVDS
Receiver Pins
(LVDS, LVPECL,
PCML, HyperTransport
Inputs)
21
True-LVDS
Transmitter Pins
(LVDS, LVPECL,
PCML,HyperTransport
Outputs)
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
True-LVDS
Receiver Pins
(LVDS, LVPECL,
PCML, HyperTransport
Inputs)
Regular I/O Pins & Flexible-LVDS
Output Pins (LVDS/HyperTransport
Outputs)
When using differential signaling in the receiver and/or
transmitter LVDS blocks, you cannot place non-differential
output pins within two I/O pads of the LVDS receiver or
transmitter blocks. Additionally, you cannot place single-ended
outputs on any pins within the LVDS blocks when using
differential signalling on any of the channels. Input pins placed
adjacent to LVDS transmitter pins may not use the fast input
register. Using switching outputs on LVDS block pins (except the
PLL LOCK pin) could affect the True-LVDS pins and degrade
performance. You can use switching outputs on the PLL LOCK
pin because it rarely changes. As shown in Figure 19, output pins
must be at least two pads away from the receiver and transmitter
block unless separated by a power or ground pin.
The same two-pad separation guideline also applies to the
dedicated LVDS clock pins and the global clock pins when using
differential signaling. You cannot place output pins within two
pads of the LVDS clock pins (both dedicated and non-dedicated)
unless separated by a power or ground pin. You can use unused
True-LVDS pins as input pins without compromising the
Altera Corporation
29
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
acceptable noise level on the VCCIO plane. Use the Show Pads
view in the Quartus II Floorplan Editor to see the pad order.
30
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 19. I/O Pin Placement Adjacent to True-LVDS Blocks
Other Pads May
Be Inputs or Outputs
Regular I/O Bank
Shared VCCIO Bus
Two Pads Next to
True-LVDS Block May
Only Be Inputs
Pads in True-LVDS Block
May Be Non-Differential
Inputs
True-LVDS Receiver or
Transmitter Block
True-LVDS Pads
The programmable I/O banks have individual power buses with separate
VCCIO pins for each I/O block. VCCIO supports 3.3-, 2.5-, 1.8-, and 1.5-V
levels. When using LVDS, PCML, and LVPECL I/O standards, connect
VCCIO to 3.3 V. When using the HyperTransport technology I/O standard,
connect VCCIO to 2.5 V. The four high-speed I/O blocks support all of the
standards supported by the APEX II devices.
The high-speed I/O interface blocks have their own VCCIO pins and may
be powered down when not used.
Termination
Definitions
Transmitted differential signals must be terminated at the interface of the
receiving device. The data inputs to the receiving device consist of up to
n bits of information and a transmit clock.
Because APEX II high-speed modules support a variety of I/O standards
and topologies, be sure to select the correct termination scheme. This
section lists the different termination schemes APEX II devices support.
LVDS & HyperTransport Termination
LVDS buffers send approximately 3.5 mA through a 100-Ω termination
which matches the trace impedance. The termination should be located as
close to receiver input possible. Hyper-Transport utilized identical
termination to LVDS. See Figure 20.
Altera Corporation
31
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Figure 20. LVDS Buffer Termination
Transmitting Device
Receiving Device
+
+
-
100 Ω
PCML Termination
PCML buffers also provide small swings, and must be terminated at the
output and the input terminal. See Figure 21.
Figure 21. PCML Buffer Termination
VTT
Transmitting Device
100 Ω
VTT
50 Ω
Receiving Device
+
+
-
100 Ω
VTT
50 Ω
VTT
LVPECL Termination
LVPECL is also a current switching differential buffer. The input and
output voltage levels are at higher levels than LVDS buffers, so a special
circuit is required to maintain the high speed capability. Figure 22
illustrates the APEX II transmitting LVPECL termination circuit, whereas
Figure 23 illustrates the APEX II receiving LVPECL termination circuit.
32
Altera Corporation
Preliminary Information
AN 166: Using High-Speed I/O Standards in APEX II Devices
Figure 22. APEX II Transmitting LVPECL Termination
3.3 V
GND
APEX II
LVPECL Transmitter
374 Ω
402 Ω
Third-Party
LVPECL Receiver
249 Ω
+
+
124 Ω
-
249 Ω
374 Ω
GND
402 Ω
3.3 V
Figure 23. APEX II Receiving LVPECL Termination
Third-Party
Transmitting Device
APEX II
Receiving Device
+
+
-
100 Ω
Board Design
Considerations
Altera Corporation
This section explains how to get the optimal performance from the
APEX II high-speed I/O block and ensure first time success in
implementing a functional design with optimal signal quality. The critical
issues of controlled impedance of traces and connectors, differential
routing, and termination techniques, must all be considered to get the best
performance from the IC. Use this application note together with the
device data sheet.
33
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
The APEX II high-speed module generates signals that travel over the
media at frequencies as high as 1 Gbps. Board designers should use the
following general guidelines:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Summary
34
Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Longer traces have more inductance and capacitance. These traces
should be shorter to limit signal integrity issues.
Place termination resistors as close to receiver input pins as possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HS-3 connectors for
backplane designs. High-performance connectors are provided by
Teradyne Corp (http://www.teradyne.com).
Design backplane and card traces so that trace impedance matches
the connector’s and/or the termination’s impedance.
Keep equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins as the TCCS value increases.
Limit vias because they cause discontinuities.
Use the common bypass capacitor values such as 0.001 µF, 0.01 µF,
and 0.1 µF to decouple the high-speed PLL power and ground planes.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route TTL clock signals to areas under or above the differential
signals.
Analyze system-level signals.
The APEX II device family of flexible, high-performance, high-density
programmable logic devices (PLDs) delivers the performance and
bandwidth necessary for complex system-on-a-programmable-chip
(SOPC) solutions. APEX II devices support multiple I/O protocols to
interface with other devices within the system. Processing-intensive data
path functions that must be received and transmitted at high speeds can
be easily implemented with APEX II devices. The APEX II family of
devices combines a high-performance enhanced PLD architecture with
dedicated I/O circuitry in order to provide I/O standard performances of
up to 1 Gbps.
Altera Corporation
Preliminary Information
Revision
History
AN 166: Using High-Speed I/O Standards in APEX II Devices
The information contained in Application Note 166 (Using High-Speed I/O
Standards in APEX II Devices) version 1.7 supersedes information
published in previous versions.
Version 1.7
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.7 contains the following changes:
■
■
■
Updated PLLs & Data Manipulation section.
Updated High-Speed Interface Pin Location section.
Various textual changes.
Version 1.6
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.6 contains the following changes:
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■
Updated Table 7.
Added Table 8.
Version 1.5
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.5 contains the following changes:
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■
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Updated VOD specification in Table 1.
Added Figures 2 and 3.
Updated W and J specifications in Table 5.
Version 1.4
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.4 contains the following changes:
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■
Updated Table 5.
Updated High-Speed Interface Pin Location section.
Version 1.3
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.3 contains the following changes:
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Altera Corporation
Updated text on page 29.
Updated Figure 19.
35
AN 166: Using High-Speed I/O Standards in APEX II Devices
Preliminary Information
Version 1.2
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.2 contains the following change: “Data Stream Serialization” on
page 8. has been updated.
Version 1.1
Application Note 166 (Using High-Speed I/O Standards in APEX II Devices)
version 1.1 contains the following change: Figure 10 has been updated.
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