EN2390QI

Enpirion® Power Datasheet
EN2390QI 9A PowerSoC
Voltage Mode Synchronous Buck
With Integrated Inductor
Not Recommended for New Designs
Description
Features
The EN2390QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
11x10x3mm QFN module. It offers high efficiency,
excellent line and load regulation over temperature.
The EN2390QI operates over a wide input voltage
range and is specifically designed to meet the precise
voltage and fast transient requirements of highperformance products. The EN2390QI features
frequency synchronization to an external clock, power
OK output voltage monitor, programmable soft-start
along with thermal and short circuit protection. The
device’s advanced circuit design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, nonisolated DC-DC conversion.
•
•
•
•
Integrated Inductor, MOSFETS, Controller
Total Solution Size Estimate: 235mm2
Wide Input Voltage Range: 4.5V – 14V
1% Initial Output Voltage Accuracy
•
Master/Slave Configuration for Parallel Operation
o Up to 4 Devices with 29A capability
Frequency Synchronization (External Clock)
Output Enable Pin and Power OK Signal
Programmable Soft-Start Time
Under Voltage Lockout Protection (UVLO)
Short Circuit Protection
Thermal Shutdown Protection
RoHS Compliant, MSL Level 3, 260oC Reflow
•
•
•
•
•
•
•
Applications
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
•
•
•
•
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
•
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
0.22µF
PG
VIN
BTMP VDDB
PVIN
ON
AVINO
1µF
47nF
RA
CA
REA
AVIN
RCA
VFB
SS
M/S
CGND
PGND
PGND
FQADJ AGND
90
80
2x
47µF
0805
EAIN
ENABLE
OFF
1µF
VOUT
BGND
VOUT
EN2390QI
4.75k
2x
22µF
1206
Efficiency vs. Output Current
100
RCLX
RB
EFFICIENCY (%)
47nF
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
10
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
RFS
100k
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 1. Simplified Applications Circuit (Footprint Optimized) Figure 2. Highest Efficiency in Smallest Solution Size
07515
June 2, 2015
Rev D
EN2390QI
Ordering Information
Part Number
EN2390QI
EVB-EN2390QI
Package Markings
EN2390QI
EN2390QI
TAMBIENT Rating (°C)
-40 to +85
Package Description
76-pin (11mm x 10mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
FQADJ
RCLX
SS
EAIN
VFB
66
65
64
63
62
POK
NC
67
57
CGND
68
ENABLE
NC(SW)
69
AVIN
NC(SW)
70
58
NC(SW)
71
AGND
NC
72
59
NC
73
M/S
NC
74
60
NC
75
61
NC
76
Pin Assignments (Top View)
56
S_OUT
2
55
S_IN
NC
3
54
BGND
NC
4
53
VDDB
NC
5
52
BTMP
NC
6
51
PG
NC
7
50
AVINO
NC
8
NC
9
NC
10
NC
11
NC
NC
1
NC
KEEP OUT
KEEP OUT
15
PVIN
16
41
PVIN
17
40
PVIN
18
39
PVIN
33
34
35
36
PGND
PGND
PGND
PGND
KEEP OUT
38
32
NC(SW)
PGND
31
NC(SW)
37
30
NC
PGND
29
NC
NC
28
NC
VOUT
NC
VOUT
NC
27
PVIN
42
26
43
VOUT
14
25
PVIN
NC
VOUT
44
24
13
VOUT
NC
23
PVIN
VOUT
45
22
12
VOUT
PVIN
21
46
VOUT
PVIN
20
47
VOUT
PVIN
19
PVIN
48
NC
49
77
PGND
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 16 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
www.altera.com/enpirion Page 2
07515
June 2, 2015
Rev D
EN2390QI
Pin Description
I/O Legend:
PIN
P=Power
G=Ground
NAME
I/O
1-19, 29,
30, 67,
72-76
NC
NC
20-28
VOUT
O
31, 32,
69-71
NC(SW)
NC
33-38
PGND
G
39-49
PVIN
P
50
AVINO
O
51
52
PG
BTMP
I/O
I/O
53
VDDB
O
54
BGND
G
55
S_IN
I
56
S_OUT
O
57
POK
O
58
ENABLE
I
59
AVIN
P
60
AGND
G
61
M/S
62
VFB
I/O
63
EAIN
I
64
SS
I/O
65
RCLX
I/O
66
FQADJ
I/O
68
CGND
77
PGND
NC=No Connect
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each
other or to any other electrical signal. Failure to follow this guideline may result in device
damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 33-35.
NO CONNECT – These pins are internally connected to the common switching node of
the internal MOSFETs. They are not to be electrically connected to any external signal,
ground, or voltage. Failure to follow this guideline may result in damage to the device.
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 36-38.
Internal 3.4V linear regulator output. Connect this pin to AVIN for applications where
operation from a single input voltage (PVIN) is required. If AVINO is being used, place a
1µF, X5R, capacitor between AVINO and AGND as close as possible to AVINO.
PMOS gate. Place a 47nF, X5R, capacitor between this pin and BTMP.
Bottom plate ground. See pin 51 description.
Internal regulated voltage used for the internal control circuitry. Place a 0.22µF, X5R,
capacitor between this pin and BGND.
Ground for VDDB. Do not connect BGND to any other ground. See pin 53 description.
Digital synchronization input. This pin accepts either an input clock to phase lock the
internal switching frequency or a S_OUT signal from another EN2390QI. Leave this pin
floating if not used.
Digital synchronization output. PWM signal is output on this pin. Leave this pin floating if
not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for
power system state indication. POK is logic high when VOUT is within -10% to +20% of
VOUT nominal. Leave this pin floating if not used.
Output enable. Applying a logic high to this pin enables the output and initiates a softstart. Applying a logic low disables the output. ENABLE logic cannot be higher than
AVIN (refer to Absolute Maximum Ratings). Do not leave floating. See Power Up/Down
Sequencing section for details.
3.3V Input power supply for the controller. Place a 1µF, X5R, capacitor between AVIN
and AGND
Analog ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
A logic level low configures the device as Master and a logic level high configures the
device as a Slave. Connect to ground in standalone mode.
External feedback input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB.
A phase lead network from this pin to VOUT is also required to stabilize the loop.
Optional error amplifier input. Allows for customization of the control loop for
performance optimization. Leave this pin floating if not used.
Soft-start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time. See Soft-Start Operation in the
Functional Description section for details.
Short circuit protection. Connect a 100k resistor from RCLX to ground.
Adding a resistor (RFS) to this pin will adjust the switching frequency of the EN2390QI.
See Table 1 for suggested resistor values on RFS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave this pin floating.
Test pin. For Enpirion Internal Use Only. Connect to GND plane at all times.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for
heat-sinking purposes.
www.altera.com/enpirion Page 3
07515
June 2, 2015
Rev D
EN2390QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
MIN
MAX
UNITS
Pin Voltages – PVIN, VOUT, PG
PARAMETER
SYMBOL
-0.5
15
V
Pin Voltages – ENABLE, S_IN, M/S, POK
-0.5
AVIN + 0.3
V
Pin Voltages – AVINO, AVIN, ENABLE, S_IN, S_OUT, M/S
-0.5
6.0
V
Pin Voltages – VFB, SS, EAIN, RCLX, FQADJ, VDDB, BTMP
-0.5
2.75
V
Dual Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
25
V/ms
Single Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
6
V/ms
14
A
150
°C
150
°C
260
°C
2000
V
Maximum Continuous Output Current
IOUT_CONT_MAX
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
-65
TJ-ABS Max
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
PVIN
4.5
14
V
AVIN: Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (Note 2)
VOUT
0.75
3.3
V
Output Current
IOUT
0
9
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 3)
PARAMETER
θJA
15
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
1.5
°C/W
Thermal Shutdown
TSD
160
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Note 1: PVIN rising and falling slew rates cannot be outside of specification. For accurate power up sequencing, use a
fast ENABLE logic (>3V/100µs) after both AVIN and PVIN are high.
Note 2: Dropout: Maximum VOUT ≤ VIN - 2.5V
Note 3: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
www.altera.com/enpirion Page 4
07515
June 2, 2015
Rev D
EN2390QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
Operating Input
Voltage
PVIN
Controller Input
Voltage
AVIN
TEST CONDITIONS
MIN
TYP
MAX
UNITS
4.5
14.0
V
2.5
5.5
V
AVIN Under Voltage
Lock-out rising
AVINUVLOR
Voltage above which UVLO is not
asserted
2.3
V
AVIN Under Voltage
Lock-out falling
AVINOVLOF
Voltage below which UVLO is
asserted
2.1
V
IAVIN
11
mA
AVINO
3.4
V
AVIN pin Input Current
Internal Linear
Regulator Output
Voltage
IPVINS
PVIN=12V, AVIN=3.4V, ENABLE=0V
300
µA
IAVINS
PVIN=12V, AVIN=3.4V, ENABLE=0V
50
µA
Feedback Pin Voltage
VFB
Feedback Pin Voltage
VFB
Feedback pin Input
Leakage Current
IFB
Feedback node voltage at:
VIN = 12V, ILOAD = 0, TA = 25°C Only
Feedback node voltage at:
4.5V ≤ VIN ≤ 14V
0A ≤ ILOAD ≤ 9A, TA = -40 to 85°C
VFB pin input leakage current
(Note 4)
Shut-Down Supply
Current
VOUT Rise Time
tRISE
CSS = 47nF (Note 4, Note 5, Note 6)
0.594
0.60
0.606
V
0.588
0.60
0.612
V
5
nA
-5
1.96
2.8
3.64
ms
10
47
68
nF
0
9
A
Soft Start Capacitor
Range
CSS_RANGE
Continuous Output
Current
IOUT_MAX_CONT
Subject to thermal derating
ENABLE Logic High
VENABLE_HIGH
4.5V ≤ VIN ≤ 14V;
1.25
AVIN
V
ENABLE Logic Low
VENABLE_LOW
4.5V ≤ VIN ≤ 14V;
0
0.95
V
ENABLE Lockout
Time
TENLOCKOUT
ENABLE pin Input
Current
IENABLE
8
AVIN = 5.5V
ENABLE = 1.8V;
ENABLE = 3.3V;
ENABLE = 5.5V;
5
11
23
RFS =3.01kΩ
1.0
Switching Frequency
FSW
External SYNC Clock
Frequency Lock
Range
FPLL_LOCK
Range of SYNC clock frequency (See
Table 1)
S_IN Threshold – Low
VS_IN_LO
S_IN Clock Logic Low Level (Note 3)
S_IN Threshold – High
VS_IN_HI
S_IN Clock Logic High Level (Note 3)
S_OUT Threshold –
Low
VS_OUT_LO
S_OUT Clock Logic Low Level
(Note 3)
S_OUT Threshold –
VS_OUT_HI
S_OUT Clock Logic High Level
0.8
1.8
1.8
ms
8
18
32
µA
MHz
1.8
MHz
0.8
V
2.5
V
0.8
V
2.5
V
www.altera.com/enpirion Page 5
07515
June 2, 2015
Rev D
EN2390QI
PARAMETER
SYMBOL
High
POK Lower Threshold
TEST CONDITIONS
POKLT
Percentage of Nominal Output
Voltage for POK to be Low
POK Output low
Voltage
VPOKL
With 4mA Current Sink into POK
POK Output Hi
Voltage
VPOKH
PVIN Range: 4.5V ≤ VIN ≤ 14V
POK pin VOH leakage
current
IPOKL
TYP
MAX
VT-LOW
Tie Pin to GND
M/S Pin Logic High
VT-HIGH
Pull up to AVIN Through an External
Resistor REXT
IM/S
90
POK High (Note 3)
M/S Pin Logic Low
M/S Pin Input Current
MIN
UNITS
(Note 3)
REXT = 15kΩ;
AVIN = 3.4V;
AVIN = 5.5V;
1.8
%
0.4
V
AVIN
V
1
µA
0.8
V
V
65
175
µA
Note 4: Parameter not production tested but is guaranteed by design.
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance.
www.altera.com/enpirion Page 6
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
CONDITIONS
VIN = 12.0V
Single Supply
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
0
0
0
1
5
2
3
4
6
OUTPUT CURRENT (A)
7
8
9
0
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
9
8
7
6
4
3
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 15°C/W
11x10x3mm QFN
No Air Flow
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
8
7
3
9
8
7
6
5
4
3
VOUT = 1.0V
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 12.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
9
4
8
Output Current De-rating
with Heat Sink
10
5
7
9
Output Current De-rating
with Air Flow (400fpm)
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 11°C/W
11x10x3mm QFN
Air Flow (400fpm)
2
3
4
5
6
OUTPUT CURRENT (A)
10
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
6
1
Output Current De-rating
with Air Flow (200fpm)
Output Current De-rating
10
5
VOUT = 1.0V
10
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
10
9
8
7
6
5
4
3
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 14°C/W
11x10x3mm QFN
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
www.altera.com/enpirion Page 7
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Curves
Output Current De-rating
w/ Heat Sink and Air Flow (400fpm)
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
w/ Heat Sink and Air Flow (200fpm)
10
9
8
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 11.5°C/W
11x10x3mm QFN
7
6
Air Flow (200fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
5
4
3
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
10
9
8
CONDITIONS
VIN = 12V
TJMAX = 125°C
θJA = 10°C/W
11x10x3mm QFN
7
6
5
Air Flow (400fpm)
Heat Sink - Wakefield
Thermal Solutions
P/N 651-B
4
3
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
2
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.005
1.205
1.004
VIN = 8V
1.003
VIN = 10V
1.002
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.2V
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
25 30 35 40 45 50 55 60 65 70 75 80 85
AMBIENT TEMPERATURE (°C)
1.001
1.000
0.999
0.998
0.997
1.204
VIN = 8V
1.203
VIN = 10V
1.202
VIN = 12V
1.201
1.200
1.199
1.198
1.197
CONDITIONS
VOUT_NOM = 1.0V
0.996
CONDITIONS
VOUT_NOM = 1.2V
1.196
0.995
1.195
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.505
1.805
VIN = 8V
1.804
1.803
VIN = 10V
1.802
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VOUT = 1.0V
1.801
1.800
1.799
1.798
1.797
VIN = 8V
2.503
VIN = 10V
2.502
VIN = 12V
2.501
2.500
2.499
2.498
2.497
CONDITIONS
VOUT_NOM = 1.8V
1.796
2.504
CONDITIONS
VOUT_NOM = 2.5V
2.496
2.495
1.795
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
8
9
www.altera.com/enpirion Page 8
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Curves
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
CONDITIONS
VIN = 14V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.204
1.201
1.200
LOAD = 0A
1.199
LOAD = 2A
LOAD = 4A
1.198
LOAD = 6A
1.197
CONDITIONS
VIN = 12V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 2A
LOAD = 4A
1.198
LOAD = 6A
1.197
LOAD = 9A
LOAD = 9A
1.196
1.196
-40
35
60
-15
10
AMBIENT TEMPERATURE ( C)
-40
85
85
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
1.204
CONDITIONS
VIN = 10V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
-15
10
35
60
AMBIENT TEMPERATURE ( C)
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
CONDITIONS
VIN = 8V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
LOAD = 4A
LOAD = 4A
1.196
1.196
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
INDIVIDUAL OUTPUT CURRENT (A)
Parallel Current Share Breakdown
10
9
8
MASTER
7
SLAVE
6
IDEAL
5
4
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
3
2
1
0
2
4
6
8
10
12
14
TOTAL OUTPUT CURRENT (A)
16
www.altera.com/enpirion Page 9
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Characteristics
Enable Startup/Shutdown Waveform (0A)
Enable Startup/Shutdown Waveform (3A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 3A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Enable Startup/Shutdown Waveform (6A)
Enable Startup/Shutdown Waveform (9A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Power Up Waveform (0A)
Power Up Waveform (4.5A)
PVIN
PVIN
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 4.5A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
www.altera.com/enpirion Page 10
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Characteristics
Power Up Waveform (6A)
Power Up Waveform (9A)
PVIN
PVIN
VOUT
VOUT
POK
POK
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
CONDITIONS
VIN = 12V, VOUT = 1.8V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 0A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 9A
Output Ripple at 500MHz Bandwidth
VOUT = 1V
(AC Coupled)
LOAD = 0A
VOUT = 1.8V
(AC Coupled)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
20mV / DIV
20mV / DIV
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
LOAD = 9A
CONDITIONS
VIN = 12V, CIN = 2x22µF (1206), COUT = 2x47µF + 100µF (1206)
www.altera.com/enpirion Page 11
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Characteristics
Load Transient from 0 to 3A (VOUT =1V)
Load Transient from 0 to 4.5A (VOUT =1V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
Load Transient from 0 to 6A (VOUT =1V)
Load Transient from 0 to 9A (VOUT =1V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
Load Transient from 0 to 3A (VOUT =3.3V)
Load Transient from 0 to 4.5A (VOUT =3.3V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
LOAD
www.altera.com/enpirion Page 12
07515
June 2, 2015
Rev D
EN2390QI
Typical Performance Characteristics
Load Transient from 0 to 6A (VOUT =3.3V)
Load Transient from 0 to 9A (VOUT =3.3V)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
COUT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
www.altera.com/enpirion Page 13
07515
June 2, 2015
Rev D
EN2390QI
Functional Block Diagram
M/S S_OUT S_IN
UVLO
Digital I/O
BTMP
PVIN
PG
Linear
Regulator
To PLL
AVINO
Thermal Limit
Short Circuit
Protection
NC(SW)
Gate Drive
VOUT
7.5k
BGND
(-)
PWM
Comp
(+)
PGND
PLL/Sawtooth
Generator
FADJ
VDDB
Compensation
Network
EAIN
Compensation
Network
(-)
Error
Amp
(+)
VFB
Power
Good
Logic
ENABLE
POK
300k
R
SS
Soft Start
Voltage Reference Generator
Band Gap
Reference
EN2390QI
AVIN
AGND
Figure 4: Functional Block Diagram
Functional Description
small size input and output filter capacitors, as well
as a wide loop bandwidth within a small foot print.
Synchronous Buck Converter
The EN2390QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nominal input voltage (PVIN) range is 4.5V to 14V
and can support up to 9A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utilizes a Type IV Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network.. The high switching
frequency of the EN2390QI enables the use of
Protection Features:
The power supply has the following protection
features:
• Short Circuit Protection
• Thermal Shutdown with Hysteresis.
• AVIN Under-Voltage Lockout Protection
Additional Features:
•
•
•
Switching Frequency Synchronization.
Programmable Soft-Start
Power OK Output Monitoring
www.altera.com/enpirion Page 14
07515
June 2, 2015
Rev D
EN2390QI
Power Up Sequence
The EN2390QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2390QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN):
PG
BTMP VDDB
PVIN
2.26k
1µF
2x
47µF
0805
EAIN
ENABLE
2x
22µF
1206
VOUT
BGND
VOUT
EN2390QI
10k
4.75k
Dual Input Supply Application (PVIN and AVIN):
0.22µF
47nF
VIN
AVINO
RA
47nF
PG
CA
VFB
M/S
EN2390QI
OFF
2x
22µF
1206
VAVIN
AGND
RFS
RCLX
AVIN
47nF
RB
100k
CA
RCA
VFB
SS
M/S
CGND
PGND
PGND
FADJ
Figure 5: Single Input Supply Schematic
AGND
RCLX
RB
100k
Figure 7: Dual Input Supply Schematic
The EN2390QI has an internal linear regulator that
converts PVIN to 3.4V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2390QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a
1µF, X5R/X7R capacitor between AVIN and AGND
as close as possible to AVIN. In addition, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends RVB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
12V
0V
RA
REA
RFS
PVIN
2x
47µF
0805
EAIN
ENABLE
AVINO
1µF
PGND
FADJ
VOUT
BGND
VOUT
ON
RCA
CGND
PGND
BTMP VDDB
PVIN
REA
SS
0.22µF
47nF
VIN
AVIN
1µF
the device at a programmed PVIN voltage level.
The lower resistor (2.26k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. In this operating mode the minimum PVIN is
6.8V due to the ENABLE threshold. See ENABLE
and DISABLE thresholds in the Electrical
Characteristics table.
PVIN slew rate limitations
as per datasheet
PVIN – Recommended
to be ramped down
after the Vout softshutdown occurs
In this application, place a 1µF, X5R/X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are two common acceptable turnon sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may still
be energy in the system. The device will not softshutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
12V
PVIN
0V
PVIN slew rate limitations
as per datasheet
PVIN powered
down before AVIN
3.3V
ENABLE
0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
3.3V
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
AVIN
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
AVIN powered up before PVIN
0V
3.3V
ENABLE
Figure 6: Single Supply Startup/Shutdown Sequence
If no external enable signal is used, a resister
divider (see Figure 5) from PVIN to ENABLE and
then to ground can be used to enable and disable
0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN/AVIN –
Recommended
to be ramped down
after the Vout softshutdown occurs
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
Figure 8: Dual Supply Startup/Shutdown Sequencing
www.altera.com/enpirion Page 15
07515
June 2, 2015
Rev D
EN2390QI
Enable Operation
Pre-Bias Operation
The EN2390QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2390QI is not pre-biased when the EN2390QI is
first enabled.
Rfs vs. SW Frequency
1.800
SWITCHING FREQUENCY (MHz)
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be reenabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
Do not leave ENABLE floating.
1.600
1.400
1.200
1.000
0.600
0
2
4
6
8 10 12 14 16 18 20 22
RFS RESISTOR VALUE (kΩ)
Figure 9. RFS versus Switching Frequency
The efficiency performance of the EN2390QI for
various VOUTs can be optimized by adjusting the
switching frequency. Table 1 shows recommended
RFS values for various VOUTs in order to optimize
performance of the EN2390QI.
PVIN
Frequency Synchronization
The switching frequency of the EN2390QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2390QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phaselocks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2390QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2390QI.
CONDITIONS
VIN = 6V to 12V
VOUT = 0.8V to 3.3V
0.800
12V
5V
VOUT
3.3V
2.5V
1.8V
1.5V
1.2V
<1.0V
2.5V
1.8V
1.5V
1.2V
<1.0V
RFS
22k
10k
4.87k
3.01k
1.65k
1.3k
22.1k
10k
6.65k
4.87k
3.01k
Typical fsw
1.42 MHz
1.3 MHz
1.15 MHz
1.0 MHz
0.95 MHz
0.8 MHz
1.4 MHz
1.3 MHz
1.25 MHz
1.15 MHz
1.0 MHz
Table 1: Recommended RFS Values
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin and
the AGND pin. During start-up of the converter, the
reference voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approximately 10µA. The soft-start time is
measured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold to when
VOUT reaches its programmed value. The total softstart time can be calculated by:
Soft Start Time (ms): T SS ≈ Css [nF] x 0.06
www.altera.com/enpirion Page 16
07515
June 2, 2015
Rev D
EN2390QI
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Short Circuit Protection
The short circuit protection feature will protect the
device if the output is shorted to ground. Short
circuit protection is achieved by sensing the current
flowing through a sense PFET. When the sensed
current exceeds the threshold for more than 32
cycles, both power FETs are turned off for the rest
of the switching cycle. If the short circuit condition
is removed, the device will reactivate soft-start and
resume PWM operation. In the event the short
circuit trips consistently in normal operation, the
device enters a hiccup mode. While in hiccup
mode, the device is disabled for a short while and
restarted with a normal soft-start. The hiccup time
is approximately 32ms. This cycle can continue
indefinitely as long as the short circuit condition
persists. Use a resistor value of 100k from the
RCLX pin to ground to enable this feature.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 160°C. After a thermal shutdown
event, when the junction temperature drops by
approx 35°C, the converter will re-start with a
normal soft-start.
AVIN Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leading edge blanking ensures
Master / Slave (Parallel) Operation:
Up to four EN2390QI devices may be connected in
a Master/Slave configuration to handle larger load
currents. The maximum output current for each
parallel device will need to be de-rated by 20
percent so that no devices will over current due to
current mis-match. The Master device’s switching
clock may be phase-locked to an external clock
source via the S_IN pin or left open and use its
default switching frequency. The device is placed in
Master mode by pulling the M/S pin low or in Slave
mode by pulling M/S pin high. Note that the M/S pin
is also pulled low for standalone mode. In Master
mode, the internal PWM signal is output on the
S_OUT pin. This PWM signal from the Master is
fed to the Slave device at its S_IN input. The Slave
device acts like an extension of the power FETs in
the Master. The inductor in the Slave prevents
crow-bar currents from Master to Slave due to
timing delays. Parallel operation in dual supply
mode is shown in Figure 11. Single supply mode
operation may also be implemented similarly. Note
that only critical components are shown. The red
text and red lines indicate the important parallel
operation connections and care should be taken in
layout to ensure low impedance between those
paths. The parallel current matching is illustrated in
Figure 10.
Parallel Current Share Breakdown
INDIVIDUAL OUTPUT CURRENT (A)
Typical soft-start time is approximately 2.8ms with
SS capacitor value of 47nF.
high noise immunity and prevents false UVLO
triggers.
10
9
8
MASTER
7
SLAVE
6
IDEAL
5
4
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
3
2
1
0
2
4
6
8
10
12
14
TOTAL OUTPUT CURRENT (A)
16
Figure 10. Parallel Current Matching
www.altera.com/enpirion Page 17
07515
June 2, 2015
Rev D
EN2390QI
Note 2:
The Master and Slave VOUTs should be
connected with very low iµpedance as
shown by the double red line connections
in parallel.
Note 1:
The Master and Slave VINs should be connected
with very low iµpedance as shown by the double
red line connections in parallel.
VIN
PVIN
ENA
2x
22µF
1206
AVIN
AVIN
2x
47µF
1206
EN2390QI
(MASTER)
SS
47nF
VOUT
VOUT
RA CA
VFB
R1
M/S
PGND
PGND
S_OUT AGND
RB
FQADJ
S_IN
PVIN
AVIN
2x
22µF
1206
VOUT
ENA
AVIN
15k
2x
47µF
1206
EN2390QI
(SLAVE)
VFB
M/S
open
SS
PGND
PGND
FQADJ
AGND
47nF
Slave #1
Note 4:
Up to 3 Slaves µay
be used in parallel
with the Master
Note 3:
The Master and Slave PGNDs should be
connected with very low iµpedance as shown by
the double red line connections in parallel.
Figure 11. Parallel Operation Illustration
www.altera.com/enpirion Page 18
07515
June 2, 2015
Rev D
EN2390QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2390QI uses a Type IV Voltage Mode
compensation network. Type IV Voltage Mode
control is a proprietary Altera Enpirion control
scheme that maximizes control loop bandwidth to
deliver excellent load transient responses and
maintain output regulation with pin point accuracy.
For ease of use, most of this network has been
customized and is integrated within the device
package. The EN2390QI output voltage is
programmed using a simple resistor divider network
(RA and RB). The feedback voltage at VFB is
nominally 0.6V. RA is predetermined based on
Table 4 and RB can be calculated based on Figure
12. The values recommended for COUT, CA, RCA and
REA make up the external compensation of the
EN2390QI. It will vary with each PVIN and VOUT
combination to optimize on performance. The
EN2390QI solution can be optimized for either
smallest size or highest performance. Please see
Table 4 for a list of recommended RA, CA, RCA, REA
and COUT values for each solution. Since VFB is a
sensitive node, do not touch the VFB node while
the device is in operation as doing so may
introduce parasitic capacitance into the control loop
that causes the device to behave abnormally and
damage may occur.
VOUT
VOUT
COUT
EAIN
RA
CA
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling.
Table 2 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
MFG
22µF, 16V, X5R,
10%, 1206
Murata
GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden
EMK316ABJ226ML- T
Table 2: Recommended Input Capacitors
Output Capacitor Selection
As seen from Table 4, the EN2390QI has been
optimized for use with one 100µF/1206 plus two
47µF/1206 output capacitors for best performance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 4 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not
be used as these lose too much capacitance
with frequency, temperature and bias voltage.
Table 4 contains a list of recommended output
capacitors
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
REA
RCA
VFB
VFB = 0.6V
PGND
RB =
EN2390QI
P/N
1
VFB x RA
Z Total
VOUT - VFB
Figure 12: VOUT Resistor Divider & Compensation
Components. See Table 4 for details.
Input Capacitor Selection
The EN2390QI requires two 22µF/1206 input
capacitors. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or equivalent dielectric formulations
must not be used as these lose too much
capacitance with frequency, temperature and
bias voltage. In some applications, lower value
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Recommended Output Capacitors
Description
47µF, 6.3V, X5R,
20%, 1206
47µF, 10V, X5R,
20%, 1206
22µF, 10V, X5R,
20%, 0805
22µF, 10V, X5R,
20%, 0805
100µF, 6.3V, X5R,
20%, 1206
MFG
P/N
Murata
GRM31CR60J476ME19L
Taiyo Yuden
LMK316BJ476ML- T
Panasonic
ECJ-2FB1A226M
Taiyo Yuden
LMK212BJ226MG- T
Murata
GRM31CR60J107ME39L
Taiyo Yuden
JMK316BJ107ML-T
Table 3: Recommended Output Capacitors
www.altera.com/enpirion Page 19
07515
June 2, 2015
Rev D
EN2390QI
Best Performance
Smallest Solution Size
CIN = 2x22µF/1206
CIN = 2x22µF/1206
V OUT ≤ 1.8V, COUT = 2x47µF/0805
1.8V < V OUT ≤ 3.3V, COUT = 2x47µF/1206
COUT = 2x47µF/1206 + 100µF/1206
RA = 200 kΩ
PVIN
(V)
14V
12V
10V
8V
6.6V
5V
RA = 75k
VOUT
(V)
CA
(pF)
RCA
(kΩ)
REA
(kΩ)
Ripple
(m V)
Deviation
(m V)
0.9V
15
18
0
5.83
1.2V
15
22
0
1.5V
18
22
1.8V
15
22
2.5V
27
3.3V
0.9V
1.2V
PVIN
(V)
VOUT
(V)
CA
(pF)
RCA
(kΩ)
REA
(kΩ)
Ripple
(m V)
Deviation
(m V)
44
0.9V
18
8.2
Open
15
93
7.22
48
1.2V
18
8.2
Open
21
104
0
8.63
38
1.5V
18
8.2
Open
27
110
0
10.8
50
1.8V
18
8.2
Open
35
120
5.1
33
14.6
72
2.5V
15
8.2
Open
54
150
22
8.2
33
26.1
76
3.3V
10
8.2
Open
81
215
27
18
0
5.21
40
0.9V
27
5.1
Open
15
96
22
22
0
6.7
36
1.2V
27
5.1
Open
21
104
1.5V
18
22
0
8.98
44
1.5V
27
5.1
Open
27
112
1.8V
18
22
0
10
50
1.8V
27
5.1
Open
34
130
2.5V
27
5.1
33
12.6
76
2.5V
22
5.1
Open
52
162
3.3V
22
8.2
33
23.6
72
3.3V
15
5.1
Open
77
221
0.9V
27
18
0
5.01
44
0.9V
56
2
Open
15
99
1.2V
22
22
0
6.28
40
1.2V
56
2
Open
20
107
1.5V
18
22
0
8.57
54
1.5V
39
2
Open
26
122
1.8V
18
22
0
9.44
60
1.8V
39
2
Open
33
126
2.5V
33
5.1
33
11
64
2.5V
33
2
Open
50
169
3.3V
27
8.2
33
21.6
68
3.3V
22
2
Open
71
241
0.9V
27
18
0
4.9
44
0.9V
100
0
Open
15
108
1.2V
22
22
0
5.82
48
1.2V
100
0
Open
20
113
1.5V
22
22
0
7.48
56
1.5V
82
0
Open
25
122
14V
12V
10V
8V
1.8V
22
22
0
8.01
54
1.8V
68
0
Open
31
136
2.5V
33
5.1
33
10.7
76
2.5V
47
0
Open
46
183
3.3V
27
8.2
33
20.5
84
3.3V
33
0
Open
62
253
0.9V
33
18
0
4.58
46
0.9V
100
0
Open
14
121
1.2V
27
22
0
5.28
54
1.2V
100
0
Open
19
128
1.5V
27
22
0
6.44
54
1.5V
100
0
Open
24
138
1.8V
22
22
0
7.2
58
1.8V
100
0
Open
29
149
2.5V
3.3V
0.9V
33
33
39
5.1
8.2
18
33
33
0
11.4
18.4
4.1
84
96
54
2.5V
3.3V
0.9V
68
47
100
0
0
0
Open
Open
Open
41
53
13
188
239
152
1.2V
33
22
0
5.1
62
1.2V
100
0
Open
18
161
1.5V
27
22
0
6.2
66
1.5V
100
0
Open
22
177
1.8V
2.5V
27
39
22
5.1
0
33
7.02
9.84
68
104
1.8V
2.5V
100
100
0
0
Open
Open
25
33
183
216
6.6V
5V
Table 4: RA, CA, RCA and REA Values for Various PVIN/VOUT Combinations: Best Performance vs. Smallest Solution
Size. Use the equations in Figure 12 to calculate RB. Output ripple is measured at no load and nominal deviation
is for a 9A load transient step. For a voltage in between the specified output voltages, choose compensation
values of the lower output voltage setting.
www.altera.com/enpirion Page 20
07515
June 2, 2015
Rev D
EN2390QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2390QI DC-DC converter is
packaged in a 10x11x3mm 76-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The following example and calculations illustrate
the thermal performance of the EN2390QI.
Example:
VIN = 12V
VOUT = 1.2V
PIN ≈ 10.8W / 0.8 ≈ 13.17W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 13.17W – 10.8W ≈ 2.37W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN2390QI has
a θJA value of 15 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.37W x 15°C/W = 35.56°C ≈ 36°C
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
T J ≈ 25°C + 36°C ≈ 61°C
First calculate the output power.
POUT = 1.2V x 9A = 10.8W
Next, determine the input power based on the
efficiency (η) shown in Figure 13.
Efficiency vs. Output Current
100
80
70
60
50
VOUT = 3.3V
40
VOUT = 2.5V
30
VOUT = 1.8V
20
VOUT = 1.2V
VOUT = 1.0V
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
T AMAX = T JMAX – PD x θJA
≈ 125°C – 36°C ≈ 89°C
The maximum ambient temperature the device can
reach is 89°C given the input and output conditions.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate. Check De-rating Curves for guaranteed
maximum output current over temperature.
90
EFFICIENCY (%)
PIN = POUT / η
T J = T A + ΔT
IOUT = 9A
10
η = POUT / PIN = 82% = 0.82
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
0
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
7
8
9
Figure 13: Efficiency vs. Output Current
For VIN = 12V, VOUT = 1.2V at 9A, η ≈ 82%
www.altera.com/enpirion Page 21
07515
June 2, 2015
Rev D
EN2390QI
Engineering Schematic
A single through-hole test
point connects the AGND
M/S must be tied to ground
pin to the GND plane.
for stand-alone operation.
Optional EAIN test point used for loop
optimization purposes. Do not connect
a voltage probe to this test point.
Css
47n
0402
Rclx
Rfs values
chosen for 12Vin/3.3Vout.
100k
0402
Rf s
15k
0402
Enable can also be
driven with an external
logic signal depending
on the application.
Cav in
1u
0402
EAIN
PVIN
PVIN
NC15
PVIN
NC16
PVIN
NC17
PVIN
PGND
NC14
NC18
100k
0402
57
POK
58
59
AVIN
ENABLE
AGND
60
61
M/S
62
VFB
64
65
63
EAIN
SS
FADJ
RCLX
66
67
NC67
68
CGND
70
69
NC(SW)69
72
71
NC(SW)71
NC(SW)70
NC73
NC72
74
NC13
PVIN
56
Cb
0.22u
0402
55
54
53
52
Cpg
47n
0402
51
Rv b
4.75k
0402
50
49
48
Cav ino
1u
0402
47
46
45
44
43
42
41
40
39
PVIN = 12 VDC
Cout1
47u
1206
Cout2
47u
1206
38
37
36
35
33
34
32
31
30
29
27
28
26
25
24
23
21
22
20
PVIN
19
VOUT
73
PVIN
0402
Rb
16.5k
NC74
NC76
NC12
PGND
0201
5.1k
18
PVIN
PGND
Rca
PVIN
NC11
PGND
0402
17
NC10
PGND
16
PVIN
PGND
Ra
75k
PVIN
EN2390
NC(SW)32
0402
15
U1
NC9
NC(SW)31
Ca
15p
NC8
NC29
14
AVINO
NC30
13
NC7
VOUT
12
PG
VOUT
11
NC6
VOUT
10
BTMP
VOUT
9
VDDB
NC5
VOUT
8
NC4
VOUT
7
S_IN
BGND
VOUT
6
S_OUT
NC3
VOUT
5
NC75
76
4
NC2
NC19
3
NC1
VOUT
2
75
RPOK
1
Choose RPOK so
that max sink
current is not
exceeded.
POK
AGND
Cin1
22u
1206
Cin2
22u
1206
Connect input and output
cap grounds to the GND
plane through multiple vias
(See the Gerber files).
Output capacitors & compensation
network optimized for 12Vin to
3.3Vout. See datasheet for other
Vin/Vout cases.
Figure 14: Engineering Schematic for Smallest Solution Size
www.altera.com/enpirion Page 22
07515
June 2, 2015
Rev D
EN2390QI
Layout Recommendation
Figure 15: Critical Component Layout for Minimum
Footprint (Top Layer). See Figure 14 for schematic.
This layout only shows the critical components and top
layer traces for minimum footprint in single-supply,
master mode with ENABLE tied to AVIN. Alternate circuit
configurations & other low-power pins need to be
connected and routed according to customer application.
Please see the Gerber files at www.altera.com/enpirion
for details on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2390QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN2390QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops. If vias cannot
be placed under the capacitors, then place them on
both sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. AVINO powers
AVIN in single supply mode. AVIN and AVINO
should have a decoupling capacitor close to each
of their pins. Refer to Figure 15.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure13.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 15). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND instead
of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Contact Altera
MySupport
for
detailed
support
(www.altera.com/mysupport).
www.altera.com/enpirion Page 23
07515
June 2, 2015
Rev D
EN2390QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package as shown in Figure 16.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN2390QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 16 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
EN2390QI QFN Package Soldering Guidelines for more details and recommendations.
Figure 16: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
www.altera.com/enpirion Page 24
07515
June 2, 2015
Rev D
EN2390QI
Recommended PCB Footprint
Figure 17: EN2390QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad (shown in blue) is based on Altera’s manufacturing recommendations.
www.altera.com/enpirion Page 25
07515
June 2, 2015
Rev D
EN2390QI
Package and Mechanical
Figure 18: EN2390QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion Page 26
07515
June 2, 2015
Rev D