Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF Group VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) Optional Function(s) RDN1A RUP1A Configuration Function for Stratix IV Only (1) TDI TMS TRST TCK TDO Dedicated Tx_Rx Channel (2) DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p DIFFIO_TX_L15n Pin List Emulated LVDS Output Channel (2) DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFOUT_L29n F1152 G28 H28 K26 F29 G29 G30 H29 E31 E30 J29 J28 C32 D32 K28 L27 B34 A33 L26 M25 C34 B33 N25 N24 F32 F31 K29 L28 D34 D33 H31 H30 G32 G31 K30 L29 E34 E33 N27 N26 F34 G33 K31 L30 J32 J31 M29 N28 G34 H33 P24 P23 H34 J34 P26 R25 K32 L31 N30 N29 K34 K33 P28 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ5L DQ5L DQSn5L DQS5L DQ5L DQ5L DQSn6L DQS6L DQ6L DQ6L DQ6L DQ6L DQ7L DQ7L DQSn7L DQS7L DQ7L DQ7L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQ3L DQ3L/CQn3L DQ3L DQ3L DQSn3L/DQ3L DQS3L/CQ3L DQ3L DQ3L DQ3L DQ3L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ8L DQ8L DQSn8L DQS8L DQ8L DQ8L DQSn9L DQS9L DQ9L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L/CQn8L DQ8L Page 1 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A VREF Group VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function for Stratix IV Only (1) CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p Dedicated Tx_Rx Channel (2) DIFFIO_TX_L15p DIFFIO_RX_L15n DIFFIO_RX_L15p DIFFIO_TX_L16n DIFFIO_TX_L16p DIFFIO_RX_L16n DIFFIO_RX_L16p DIFFIO_TX_L17n DIFFIO_TX_L17p DIFFIO_RX_L17n DIFFIO_RX_L17p DIFFIO_TX_L18n DIFFIO_TX_L18p DIFFIO_RX_L18n DIFFIO_RX_L18p DIFFIO_TX_L19n DIFFIO_TX_L19p DIFFIO_RX_L19n DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFIO_TX_L20p DIFFIO_RX_L20n DIFFIO_RX_L20p DIFFIO_TX_L21n DIFFIO_TX_L21p DIFFIO_RX_L21n DIFFIO_RX_L21p DIFFIO_TX_L22n DIFFIO_TX_L22p DIFFIO_RX_L22n DIFFIO_RX_L22p Emulated LVDS Output Channel (2) DIFFOUT_L29p DIFFOUT_L30n DIFFOUT_L30p DIFFOUT_L31n DIFFOUT_L31p DIFFOUT_L32n DIFFOUT_L32p DIFFOUT_L33n DIFFOUT_L33p DIFFOUT_L34n DIFFOUT_L34p DIFFOUT_L35n DIFFOUT_L35p DIFFOUT_L36n DIFFOUT_L36p DIFFOUT_L37n DIFFOUT_L37p DIFFOUT_L38n DIFFOUT_L38p DIFFOUT_L39n DIFFOUT_L39p DIFFOUT_L40n DIFFOUT_L40p DIFFOUT_L41n DIFFOUT_L41p DIFFOUT_L42n DIFFOUT_L42p DIFFOUT_L43n DIFFOUT_L43p DIFFOUT_L44n DIFFOUT_L44p nCONFIG nSTATUS CONF_DONE PORSEL nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p Pin List DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p F1152 P27 L34 L33 T25 T24 M32 M31 T23 U23 N32 N31 P29 R29 M34 N33 T29 T28 P32 P31 T27 T26 N34 P33 V25 U24 R32 R31 V23 W23 T31 T30 P34 R34 AC27 AM30 AN30 AL28 AM29 AA25 AB25 AC26 AC25 AB24 AC24 AE25 AD26 AD23 AE24 AE27 AE26 AG26 AF24 AH27 AH26 AJ27 AG25 AH25 AH24 AJ25 AK26 AG23 AF23 DQ Group for DQS X4 Mode (2) DQ9L DQ9L DQ9L DQ10L DQ10L DQSn10L DQS10L DQ10L DQ10L DQSn11L DQS11L DQ11L DQ11L DQ11L DQ11L DQ12L DQ12L DQSn12L DQS12L DQ12L DQ12L DQSn13L DQS13L DQ13L DQ13L DQ13L DQ13L DQ Group for DQS X8/X9 Mode (2) DQ8L DQ8L DQ8L DQ9L DQ9L DQ9L DQ9L/CQn9L DQ9L DQ9L DQSn9L/DQ9L DQS9L/CQ9L DQ9L DQ9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQSn10L/DQ10L DQS10L/CQ10L DQ10L DQ10L DQ10L DQ10L DQ Group for DQS X16/X18 Mode (2) DQ8L DQ8L DQ8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 2 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C VREF Group VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_RX_B14n DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_RX_B20n DIFFIO_RX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 Pin List Emulated LVDS Output Channel (2) DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p F1152 AL27 AM27 AM26 AL26 AK25 AN28 AP32 AP31 AP28 AP27 AP30 AP29 AB23 AA23 AD22 AC22 AC20 AD20 AF21 AE22 AE20 AE21 AJ24 AH23 AG22 AH21 AJ22 AH22 AL23 AM23 AM24 AL24 AK22 AK23 AP26 AN26 AM25 AP24 AP25 AN25 AM22 AP22 AP23 AN23 AP21 AN22 AM21 AL21 AJ21 AK20 AM20 AL20 AN20 AJ20 AM19 AL19 AK19 AJ19 AH19 AG19 AD19 AC18 DQ Group for DQS X4 Mode (2) DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ Group for DQS X8/X9 Mode (2) DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ Group for DQS X16/X18 Mode (2) DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ9B DQ9B DQSn9B DQS9B DQ9B DQ9B DQSn10B DQS10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQSn13B DQS13B DQ13B DQ13B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ8B DQ8B DQ8B DQ8B/CQn8B DQ8B DQ8B DQSn8B/DQ8B DQS8B/CQ8B DQ8B DQ8B DQ8B DQ8B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B Page 3 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B VREF Group VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) Optional Function(s) PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n PLL_B2_FBp/CLKOUT1 PLL_B2_FBn/CLKOUT2 PLL_B2_CLKOUT0p PLL_B2_CLKOUT0n Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_B22n DIFFIO_RX_B22p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n PLL_B2_CLKOUT3 PLL_B2_CLKOUT4 DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n DIFFIO_RX_B32p DIFFIO_RX_B32n DIFFIO_RX_B33p DIFFIO_RX_B33n DIFFIO_RX_B34p DIFFIO_RX_B34n DIFFIO_RX_B35p DIFFIO_RX_B35n DIFFIO_RX_B36p DIFFIO_RX_B36n DIFFIO_RX_B37p DIFFIO_RX_B37n Pin List Emulated LVDS Output Channel (2) DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n DIFFOUT_B65p DIFFOUT_B65n DIFFOUT_B66p DIFFOUT_B66n DIFFOUT_B67p DIFFOUT_B67n DIFFOUT_B68p DIFFOUT_B68n DIFFOUT_B69p DIFFOUT_B69n DIFFOUT_B70p DIFFOUT_B70n DIFFOUT_B71p DIFFOUT_B71n DIFFOUT_B72p DIFFOUT_B72n DIFFOUT_B73p DIFFOUT_B73n DIFFOUT_B74p DIFFOUT_B74n F1152 AG20 AF19 AE19 AE18 AM18 AL18 AP20 AP19 AP18 AP17 AP15 AP16 AM17 AN17 AK17 AL17 AC16 AD17 AE16 AF16 AE15 AD16 AG16 AH16 AJ16 AK16 AM15 AM16 AL16 AH15 AP13 AP14 AP12 AN14 AM13 AN13 AL15 AJ15 AK14 AL14 AJ14 AM14 AJ13 AK13 AG13 AH13 AH12 AJ12 AC14 AD14 AF14 AG14 AE14 AE13 AM11 AN11 AL12 AM12 AK11 AL11 AP11 AM10 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ14B DQ14B DQS14B DQSn14B DQ14B DQ14B DQ15B DQ15B DQ15B DQ15B DQS15B DQSn15B DQ16B DQ16B DQS16B DQSn16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B DQSn17B DQ18B DQ18B DQS18B DQSn18B DQ18B DQ18B DQ19B DQ19B DQ19B DQ19B DQS19B DQSn19B DQ20B DQ20B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ19B DQ19B DQ19B DQ19B DQS19B/CQ19B DQSn19B/DQ19B DQ19B DQ19B DQ19B/CQn19B DQ19B DQ19B DQ19B DQ20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B/CQn20B DQ20B DQ20B DQ20B Page 4 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C VREF Group VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_B38p DIFFIO_RX_B38n DIFFIO_RX_B39p DIFFIO_RX_B39n DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n RUP4A RDN4A DIFFIO_RX_B48p DIFFIO_RX_B48n Emulated LVDS Output Channel (2) DIFFOUT_B75p DIFFOUT_B75n DIFFOUT_B76p DIFFOUT_B76n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n DIFFOUT_B95p DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n nIO_PULLUP nCEO DCLK nCSO ASDO CLK10p CLK10n CLK11p CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n DIFFIO_RX_R23p DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p Pin List DIFFOUT_R45p DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p F1152 AN10 AP10 AP9 AM9 Y12 AA12 AC12 AD13 AP5 AP6 AN7 AP7 AP3 AP4 AP8 AL9 AM8 AN8 AL7 AL8 AJ10 AK10 AH11 AJ11 AF12 AG11 AJ9 AG10 AJ8 AK8 AH8 AH9 AD9 AE9 AE11 AE12 AD11 AE10 AB11 AB12 AB10 AC10 AA10 AA11 AM6 AE8 AM5 AD8 AN5 P1 R1 R3 R2 U12 V12 T5 T4 V11 U10 P4 P3 T9 DQ Group for DQS X4 Mode (2) DQS20B DQSn20B DQ20B DQ20B DQ Group for DQS X8/X9 Mode (2) DQ20B/CQn20B DQ20B DQ20B DQ20B DQ Group for DQS X16/X18 Mode (2) DQ20B DQ20B DQ20B DQ20B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ24B DQ24B DQ24B DQ24B DQS24B/CQ24B DQSn24B/DQ24B DQ24B DQ24B DQ24B/CQn24B DQ24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B/CQ25B DQSn25B/DQ25B DQ25B DQ25B DQ25B/CQn25B DQ25B DQ25B DQ25B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ14R DQ14R DQ14R DQ14R DQS14R DQSn14R DQ15R DQ17R DQ17R DQ17R DQ17R DQS17R/CQ17R DQSn17R/DQ17R DQ17R Page 5 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A VREF Group VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_RX_R29n DIFFIO_TX_R29p DIFFIO_TX_R29n DIFFIO_RX_R30p DIFFIO_RX_R30n DIFFIO_TX_R30p DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_RX_R31n DIFFIO_TX_R31p DIFFIO_TX_R31n DIFFIO_RX_R32p DIFFIO_RX_R32n DIFFIO_TX_R32p DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_RX_R33n DIFFIO_TX_R33p DIFFIO_TX_R33n DIFFIO_RX_R34p DIFFIO_RX_R34n DIFFIO_TX_R34p DIFFIO_TX_R34n DIFFIO_RX_R35p DIFFIO_RX_R35n DIFFIO_TX_R35p DIFFIO_TX_R35n DIFFIO_RX_R36p DIFFIO_RX_R36n DIFFIO_TX_R36p DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_RX_R38n DIFFIO_TX_R38p DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_RX_R39n DIFFIO_TX_R39p DIFFIO_TX_R39n DIFFIO_RX_R40p DIFFIO_RX_R40n DIFFIO_TX_R40p DIFFIO_TX_R40n DIFFIO_RX_R41p Pin List Emulated LVDS Output Channel (2) DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R57n DIFFOUT_R58p DIFFOUT_R58n DIFFOUT_R59p DIFFOUT_R59n DIFFOUT_R60p DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R61n DIFFOUT_R62p DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R63n DIFFOUT_R64p DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R65n DIFFOUT_R66p DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R67n DIFFOUT_R68p DIFFOUT_R68n DIFFOUT_R69p DIFFOUT_R69n DIFFOUT_R70p DIFFOUT_R70n DIFFOUT_R71p DIFFOUT_R71n DIFFOUT_R72p DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R75n DIFFOUT_R76p DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R77n DIFFOUT_R78p DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R79n DIFFOUT_R80p DIFFOUT_R80n DIFFOUT_R81p F1152 T8 N2 N1 T11 T10 M2 M1 T7 T6 N4 N3 R6 R5 K1 L1 R12 R11 K3 K2 R8 R7 L4 L3 P7 P6 M5 M4 N6 N5 J2 J1 M7 M6 J4 J3 P10 P9 G1 H1 N9 N8 G2 F1 L7 L6 H4 H3 K6 K5 F2 E1 N11 N10 G4 G3 N12 M11 D2 D1 J6 J5 C2 DQ Group for DQS X4 Mode (2) DQ15R DQS15R DQSn15R DQ15R DQ15R DQ16R DQ16R DQ16R DQ16R DQS16R DQSn16R DQ17R DQ17R DQS17R DQSn17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQS18R DQSn18R DQ19R DQ19R DQS19R DQSn19R DQ19R DQ19R DQ Group for DQS X8/X9 Mode (2) DQ17R DQ17R/CQn17R DQ17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQS18R/CQ18R DQSn18R/DQ18R DQ18R DQ18R DQ18R/CQn18R DQ18R DQ18R DQ18R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ Group for DQS X16/X18 Mode (2) DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQSn19R/DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ19R DQ20R DQ20R DQS20R DQSn20R DQ20R DQ20R DQ21R DQ21R DQ21R DQ21R DQS21R DQSn21R DQ22R DQ22R DQS22R DQSn22R DQ22R DQ22R DQ23R DQ23R DQ23R DQ23R DQS23R DQSn23R DQ24R DQ24R DQS24R DQSn24R DQ24R DQ24R DQ25R DQ24R DQ24R DQ24R DQ24R DQS24R/CQ24R DQSn24R/DQ24R DQ24R DQ24R DQ24R/CQn24R DQ24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R Page 6 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B VREF Group VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) Optional Function(s) RUP6A RDN6A RDN7A RUP7A Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_R41n DIFFIO_TX_R41p DIFFIO_TX_R41n DIFFIO_RX_R42p DIFFIO_RX_R42n DIFFIO_TX_R42p DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_RX_R43n DIFFIO_TX_R43p DIFFIO_TX_R43n DIFFIO_RX_R44p DIFFIO_RX_R44n DIFFIO_TX_R44p DIFFIO_TX_R44n DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n Pin List Emulated LVDS Output Channel (2) DIFFOUT_R81n DIFFOUT_R82p DIFFOUT_R82n DIFFOUT_R83p DIFFOUT_R83n DIFFOUT_R84p DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R85n DIFFOUT_R86p DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R87n DIFFOUT_R88p DIFFOUT_R88n DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n F1152 C1 M9 M8 E4 E3 K8 K7 D4 D3 F5 F4 A2 B1 H7 H6 J11 K11 H12 J12 K12 L12 F8 G8 H9 G9 G10 H10 F7 F6 D6 E6 E7 D7 B4 C5 A5 A4 A3 B3 G11 E10 C8 D8 E9 F10 A6 B6 A7 C6 A8 B7 L13 M13 C9 D9 M15 K13 J14 K14 K15 L15 F13 DQ Group for DQS X4 Mode (2) DQ25R DQ25R DQ25R DQS25R DQSn25R DQ26R DQ26R DQS26R DQSn26R DQ26R DQ26R DQ Group for DQS X8/X9 Mode (2) DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ Group for DQS X16/X18 Mode (2) DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T Page 7 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C VREF Group VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO(7) Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p PLL_T2_CLKOUT4 PLL_T2_CLKOUT3 DIFFIO_RX_T22n DIFFIO_RX_T22p PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_T2_FBn/CLKOUT2 PLL_T2_FBp/CLKOUT1 CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T23n DIFFIO_RX_T23p DIFFIO_RX_T24n DIFFIO_RX_T24p DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T28p Pin List Emulated LVDS Output Channel (2) DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33n DIFFOUT_T33p DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T43n DIFFOUT_T43p DIFFOUT_T44n DIFFOUT_T44p DIFFOUT_T45n DIFFOUT_T45p DIFFOUT_T46n DIFFOUT_T46p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p F1152 G13 G12 H13 F14 G14 D11 C11 D12 E12 F11 E13 A9 B9 A11 C10 A10 B10 A13 A12 B13 C13 C12 B12 C14 D14 C15 A14 A15 B15 C16 D15 E15 F15 F16 E16 G16 H15 M17 L16 H16 J16 K16 K17 C17 D17 A16 B16 A17 A18 C18 B18 A20 A19 E18 D18 M19 L18 H19 G19 L19 K20 K19 DQ Group for DQS X4 Mode (2) DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQSn10T DQS10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQ Group for DQS X8/X9 Mode (2) DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ8T DQ8T DQ8T DQ8T/CQn8T DQ8T DQ8T DQSn8T/DQ8T DQS8T/CQ8T DQ8T DQ8T DQ8T DQ8T DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQ Group for DQS X16/X18 Mode (2) DQ7T/CQn7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T Page 8 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF Group VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO(7) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_RX_T34p DIFFIO_RX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_RX_T36p DIFFIO_RX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_RX_T38p DIFFIO_RX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_RX_T42p DIFFIO_RX_T42n DIFFIO_RX_T43p DIFFIO_RX_T43n Pin List Emulated LVDS Output Channel (2) DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p F1152 J19 F20 G20 E19 D19 F19 C19 A23 A22 B21 A21 C22 B22 F21 C20 E21 D21 D20 C21 A26 A25 A24 B24 C26 B25 E24 C25 D24 C24 D23 C23 J21 H21 L21 M21 K22 K21 E22 F22 H22 G22 F23 G23 M23 L22 L24 K25 B28 A29 A27 A28 C27 B27 E25 F24 D26 D27 F25 E27 A31 A32 A30 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) DQ14T DQ14T DQS14T DQSn14T DQ14T DQ14T DQ15T DQ15T DQ15T DQ15T DQS15T DQSn15T DQ16T DQ16T DQS16T DQSn16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T DQSn17T DQ18T DQ18T DQS18T DQSn18T DQ18T DQ18T DQ19T DQ19T DQ19T DQ19T DQS19T DQSn19T DQ20T DQ20T DQS20T DQSn20T DQ20T DQ20T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ19T DQ19T DQ19T DQ19T DQS19T/CQ19T DQSn19T/DQ19T DQ19T DQ19T DQ19T/CQn19T DQ19T DQ19T DQ19T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ23T DQ23T DQ23T DQ24T DQ24T DQ24T DQ24T DQS24T/CQ24T DQSn24T/DQ24T DQ24T DQ24T DQ24T/CQn24T DQ24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T Page 9 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QR0 VREF Group VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name Optional /Function Function(s) IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO RUP8A IO RDN8A IO IO GXB_TX_L7p GXB_TX_L7n GXB_RX_L7p GXB_RX_L7n GXB_TX_L6p GXB_TX_L6n GXB_RX_L6p GXB_RX_L6n REFCLK_L3p, GXB_CMURX_L3p REFCLK_L3n, GXB_CMURX_L3n REFCLK_L2p, GXB_CMURX_L2p REFCLK_L2n, GXB_CMURX_L2n GXB_TX_L5p GXB_TX_L5n GXB_RX_L5p GXB_RX_L5n GXB_TX_L4p GXB_TX_L4n GXB_RX_L4p GXB_RX_L4n GXB_TX_L3p GXB_TX_L3n GXB_RX_L3p GXB_RX_L3n GXB_TX_L2p GXB_TX_L2n GXB_RX_L2p GXB_RX_L2n REFCLK_L1p, GXB_CMURX_L1p REFCLK_L1n, GXB_CMURX_L1n REFCLK_L0p, GXB_CMURX_L0p REFCLK_L0n, GXB_CMURX_L0n GXB_TX_L1p GXB_TX_L1n GXB_RX_L1p GXB_RX_L1n GXB_TX_L0p GXB_TX_L0n GXB_RX_L0p GXB_RX_L0n GXB_RX_R0n Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n DIFFIO_RX_T48p DIFFIO_RX_T48n Pin List Emulated LVDS Output Channel (2) DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n F1152 B30 C31 B31 E28 D28 D29 C29 D30 C30 G26 F26 G25 H25 G27 F27 J23 K23 J24 H24 J25 K24 V31 V32 U33 U34 Y31 Y32 W33 W34 AC29 AC30 AE29 AE30 AB31 AB32 AA33 AA34 AD31 AD32 AC33 AC34 AF31 AF32 AE33 AE34 AH31 AH32 AG33 AG34 AG29 AG30 AJ29 AJ30 AK31 AK32 AJ33 AJ34 AM31 AM32 AL33 AL34 AL1 DQ Group for DQS X4 Mode (2) DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ26T DQ26T DQS26T DQSn26T DQ26T DQ26T DQ Group for DQS X8/X9 Mode (2) DQ25T DQS25T/CQ25T DQSn25T/DQ25T DQ25T DQ25T DQ25T/CQn25T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQ Group for DQS X16/X18 Mode (2) DQ26T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T Page 10 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name Optional /Function Function(s) GXB_RX_R0p GXB_TX_R0n GXB_TX_R0p GXB_RX_R1n GXB_RX_R1p GXB_TX_R1n GXB_TX_R1p REFCLK_R0n, GXB_CMURX_R0n REFCLK_R0p, GXB_CMURX_R0p REFCLK_R1n, GXB_CMURX_R1n REFCLK_R1p, GXB_CMURX_R1p GXB_RX_R2n GXB_RX_R2p GXB_TX_R2n GXB_TX_R2p GXB_RX_R3n GXB_RX_R3p GXB_TX_R3n GXB_TX_R3p GXB_RX_R4n GXB_RX_R4p GXB_TX_R4n GXB_TX_R4p GXB_RX_R5n GXB_RX_R5p GXB_TX_R5n GXB_TX_R5p REFCLK_R2n, GXB_CMURX_R2n REFCLK_R2p, GXB_CMURX_R2p REFCLK_R3n, GXB_CMURX_R3n REFCLK_R3p, GXB_CMURX_R3p GXB_RX_R6n GXB_RX_R6p GXB_TX_R6n GXB_TX_R6p GXB_RX_R7n GXB_RX_R7p GXB_TX_R7n GXB_TX_R7p GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) AL2 AM3 AM4 AJ1 AJ2 AK3 AK4 AJ5 AJ6 AG5 AG6 AG1 AG2 AH3 AH4 AE1 AE2 AF3 AF4 AC1 AC2 AD3 AD4 AA1 AA2 AB3 AB4 AE5 AE6 AC5 AC6 W1 W2 Y3 Y4 U1 U2 V3 V4 P21 AC8 U18 B32 AN6 AN9 AN12 AN15 AN18 AN21 AN24 AN27 AN29 AK9 AK12 AK15 AK18 AK21 AK24 AK27 AG9 AG12 AG15 Pin List Page 11 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) AG18 AG21 AG24 AG27 AF8 AD12 AD15 AD18 AD21 AD24 AD27 AC9 AC11 AB13 AB15 AB17 AB19 AB21 AA14 AA16 AA18 AA20 AA22 AA24 Y11 Y13 Y15 Y17 Y19 Y21 W14 W16 W18 W20 W22 V13 V15 V19 V21 V24 U11 U14 U16 U20 U22 T13 T15 T17 T19 T21 R14 R16 R18 R20 R22 R24 R27 R30 R33 P2 P5 P8 Pin List Page 12 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) P11 P13 P15 P17 P19 N14 N16 N18 N20 N22 M24 M27 M30 M33 L2 L5 L8 L11 L14 L17 L20 L23 J27 J30 J33 H2 H5 H8 H11 H14 H17 H20 H23 H26 F30 F33 E2 E5 E8 E11 E14 E17 E20 E23 E26 E29 C33 B2 B5 B8 B11 B14 B17 B20 B23 B26 B29 T34 T33 T32 U32 U31 Pin List Page 13 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) U29 U27 V34 V33 V30 V28 W32 W31 W29 W27 Y34 Y33 Y30 Y28 AA32 AA31 AA29 AA27 AB34 AB33 AB30 AB28 AC32 AC31 AD34 AD33 AD30 AD29 AE32 AE31 AF34 AF33 AF30 AF29 AG32 AG31 AP33 AN31 AN32 AN33 AM33 AM34 AL31 AL32 AK29 AK30 AK33 AK34 AJ31 AJ32 AH29 AH30 AH33 AH34 T3 T2 T1 U8 U6 U4 U3 V7 Pin List Page 14 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) V5 V2 V1 W8 W6 W4 W3 Y7 Y5 Y2 Y1 AA8 AA6 AA4 AA3 AB7 AB5 AB2 AB1 AC4 AC3 AD6 AD5 AD2 AD1 AE4 AE3 AF6 AF5 AF2 AF1 AG4 AG3 AH6 AH5 AH2 AH1 AJ4 AJ3 AK6 AK5 AK2 AK1 AL4 AL3 AM2 AM1 AN4 AN3 AN2 AP2 U17 N19 AB14 AB16 AB18 AB20 AB22 AA13 AA15 AA17 AA19 Pin List Page 15 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCA_PLL_B1 VCCA_PLL_B2(7) VCCA_PLL_L2 VCCA_PLL_R2 VCCA_PLL_T1 VCCA_PLL_T2(7) VCCD_PLL_B1 Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) AA21 Y14 Y16 Y18 Y20 Y22 W13 W15 W17 W19 W21 V14 V16 V18 V20 V22 U13 U15 U19 U21 T14 T16 T18 T20 T22 R13 R15 R17 R19 R21 P14 P16 P18 P20 P22 N13 N15 N17 N21 AB26 AB27 V26 U26 AB8 AB9 V9 U9 AD25 AD10 C3 D5 AF18 AE17 J17 K18 AJ18 AH17 W25 W10 G18 F17 AH18 Pin List Page 16 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function VCCD_PLL_B2(7) VCCD_PLL_L2 VCCD_PLL_R2 VCCD_PLL_T1 VCCD_PLL_T2(7) VCCIO1A VCCIO1A VCCIO1A VCCIO1A(7) VCCIO1A(7) VCCIO1C VCCIO1C VCCIO1C(7) VCCIO1C(7) VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B(7) VCCIO3B(7) VCCIO3C VCCIO3C VCCIO3C(7) VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B(7) VCCIO4B(7) VCCIO4C VCCIO4C VCCIO4C(7) VCCIO6A VCCIO6A VCCIO6A VCCIO6A(7) VCCIO6A(7) VCCIO6C VCCIO6C VCCIO6C(7) VCCIO6C(7) VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B(7) VCCIO7B(7) VCCIO7C VCCIO7C VCCIO7C(7) VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8B(7) VCCIO8B(7) VCCIO8C VCCIO8C VCCIO8C(7) VCCPD1A VCCPD1C VCCPD3A Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) AG17 W24 V10 H18 G17 P25 M28 K27 H32 E32 L32 U25 R28 P30 AF25 AM28 AJ26 AE23 AJ23 AL25 AH20 AN19 AL22 AF9 AM7 AH10 AF11 AL13 AL10 AJ17 AN16 AH14 F3 L9 K4 J7 G5 N7 R4 R9 M3 C7 K10 F9 C4 F12 D10 D16 G15 D13 C28 L25 G24 F28 D25 D22 B19 G21 F18 N23 R23 AC23 Pin List Page 17 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number 1A 1C 3A 3B 3C 4A 4B 4C 6A 6C 7A 7B 7C 8A 8B 8C VREF Group VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Name /Function VCCPD3B(7) VCCPD3C VCCPD4A VCCPD4B(7) VCCPD4C VCCPD6A VCCPD6C VCCPD7A VCCPD7B(7) VCCPD7C VCCPD8A VCCPD8B(7) VCCPD8C VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3BN0(7) VREFB3CN0 VREFB4AN0 VREFB4BN0(7) VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0(7) VREFB7CN0 VREFB8AN0 VREFB8BN0(7) VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC(6) NC(4) NC(3) NC(3) NC(3) NC(5) NC(5) NC(5) NC(5) NC(5) NC(5) Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) AC21 AC19 AC13 AC15 AC17 P12 T12 M12 M14 M16 M22 M20 M18 M26 R26 AF26 AF22 AF20 AF10 AF13 AF15 M10 R10 J10 J13 J15 J26 J22 J20 D31 AK28 AK7 G7 AL29 AL30 AL5 AL6 AJ7 AJ28 AH7 AH28 AG7 AG28 AF7 AF28 AE7 AE28 AD7 AD28 AC7 AC28 V17 G6 K9 L10 J9 Y23 Y24 AF17 W11 W12 J18 VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 MSEL2 MSEL1 MSEL0 Pin List Page 18 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Bank Number VREF Group Pin Name /Function VCCAUX VCCAUX VCCAUX VCCAUX VCCA_L VCCA_L VCCA_R VCCA_R VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBR0 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCR_R VCCR_R VCCR_L VCCR_L VCCT_R VCCT_R VCCT_L VCCT_L VCCHIP_R VCCHIP_R VCCHIP_R VCCHIP_L VCCHIP_L VCCHIP_L RREF_L0 RREF_R0 Optional Function(s) Configuration Function for Stratix IV Only (1) Dedicated Tx_Rx Channel (2) Emulated LVDS Output Channel (2) F1152 DQ Group for DQS X4 Mode (2) DQ Group for DQS X8/X9 Mode (2) DQ Group for DQS X16/X18 Mode (2) H27 AF27 AG8 J8 Y29 V29 Y6 V6 AA28 U28 AA7 U7 AA26 Y27 W28 V27 Y8 AA9 W7 V8 U5 AA5 U30 AA30 AB6 W5 AB29 W30 W9 Y10 Y9 W26 Y26 Y25 AN34 AN1 Notes on Pin Table: (1) These pins should be connected on the board to properly configure the FPGA prototype. See Stratix IV device pin table for details. (2) The individual index number of the pin in this column may not be the same as its companion Stratix IV device, but the functionality of the pin is fully migratable. (3) These NO CONNECT (NC) pins are MSEL configuration input pins in the Stratix IV device and should be connected on the board to configure the FPGA prototype. (4) This NC pin is a VCCBAT pin in the Stratix IV device and should be connected for the FPGA prototype. (5) This NC pin is a VCCPT pin in the Stratix IV device and should be connected for the FPGA prototype. (6) This NC pin is a DNU pin in the Stratix IV device and must be left floating. (7) These pins are NC in FPGA companion device EP4SGX110FF35 only. PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin List Page 19 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Notes (1), (2) Pin Type (1st and 2nd Function) Pin Description Clock, Input Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. CLK[1,3,8,10]n Clock, Input Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. CLK[0,2,9,11]p CLK[0,2,9,11]n CLK[4:7,12:15]p I/O, Clock I/O, Clock I/O, Clock These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. CLK[4:7,12:15]n PLL_[L1,L4,R1,R4]_CLKp PLL_[L1,L4,R1,R4]_CLKn PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, ,L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n Dedicated Configuration/JTAG Pins nIO_PULLUP I/O, Clock Clock, Input Clock, Input I/O, Clock These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. TEMPDIODEp TEMPDIODEn nCE nCONFIG CONF_DONE Pin Name Clock and PLL Pins CLK[1,3,8,10]p I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. Input Input Dedicated input that chooses whether the internal pull-up resistors on the user I/O pins are on or off during power up. A logic high turns off the weak pull-ups, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the HardCopy IV device. Input Pin used in conjunction with the temperature sensing diode (bias-low input) inside the HardCopy IV device. Input Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated power up block control input. Pulling this pin low during user-mode will cause the HardCopy IV to enter a reset state & tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin. Bidirectional (open-drain) Output Bidirectional (open-drain) This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. Driven this pin high indicates that the device is entering user mode. Output that drives low when device initialization is complete. This is a dedicated power up block status pin. The HardCopy IV drives nSTATUS low indicates that the device is being initialized. As a status output, the nSTATUS is pulled low if an error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external source during initialization. It is not available as a user I/O pin. PORSEL Input nCSO ASDO DCLK Output Output Input (PS, FPP) Output (AS) Input Input Input Output Input Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons. Dedicated control signal from Stratix IV devices, but kept in HardCopy IV for compatibility reasons. Dedicated configuration clock pin on Stratix IV devices, but kept in HardCopy IV for compatibility reasons. It's not required to clock this pin for HardCopy IV. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. nCEO nSTATUS TCK TMS TDI TDO TRST PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. Pin Definitions Page 20 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Notes (1), (2) Pin Name Differential I/O Pins DIFFIO_RX[##]p, DIFFIO_RX[##]n Pin Type (1st and 2nd Function) I/O, RX channel Pin Description These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFIO_TX[##]p, DIFFIO_TX[##]n I/O, TX channel DIFFOUT_[##]p, DIFFOUT_[##]n I/O, TX channel These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. I/O,DQS Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. DQSn[1:38][T,B], DQSn[1:34][L,R] I/O,DQSn Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. DQ[1:38][T,B], DQ[1:34][L,R] I/O,DQ Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Optional data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. External Memory Interface Pins DQS[1:38][T,B], DQS[1:34][L,R] CQ[1:38][T,B], CQ[1:34][L,R] DQS CQn[1:38][T,B], CQn[1:34][L,R] Optional complementary data strobe signal for use in QDRII SRAM. These are the pins for echo clocks. DQS Reference Pins RUP[1:8]A, RUP[3,8]C I/O, Input Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. RDN[1:8]A, RDN[3,8]C I/O, Input Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. DNU NC Supply Pins VCC VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,C], VCCIO[2,3,4,5,7,8]B Do Not Use No Connect Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Power Power VCCPGM VCCPD[1:8][A,C], VCCPD[2,3,4,5,7,8]B VCC_CLKIN[3,4,7,8]C Power Power VCC supplies power to the core and periphery. Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2V, 1.5V, 1.8V, 2.5V, 3.3V), HSTL(12,15,18),SSTL(15,18,2),3.0V PCI/PCI-X I/O as well as LVTTL 3.3V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2V, 1.5V, 1.8V, 2.5V, 3.3V), 3.0V PCI/PCI-X and LVTTL 3.3V I/O standards. Configuration pins power supply. Dedicated power pins. This supply is used to power the I/O pre-drivers. Power Differential clock input power supply for top and bottom I/O banks. PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Power Power Power Pin Definitions Page 21 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Notes (1), (2) Pin Name GND VREFB[1:8][A,C]N0, VREFB[2,3,4,5,7,8]BN0 Transceiver (I/O Banks) Pins VCCHIP_[L,R] VCCR_[L,R] VCCT_[L,R] VCCL_GXB[L,R][0:3] VCCH_GXB[L,R][0:3] VCCA_[L,R] GXB_RX_[L,R][0:15]p GXB_RX_[L,R][0:15]n GXB_TX_[L,R][0:15]p GXB_TX_[L,R][0:15]n REFCLK_[L,R][0:7]p GXB_CMURX_[L,R][0:7]p Pin Type (1st and 2nd Function) Ground Power Pin Description Device ground pins. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. Power Power Power Power Power Power Input Input Output Output Input PCIe Hard IP digital power supply, specific to the left (L) side or right (R) side of the device. Analog power, receiver, specific to the left (L) side or right (R) side of the device. Analog power, transmitter, specific to the left (L) side or right (R) side of the device. Analog power, block level clock distribution. Analog power, block level TX buffers. Analog power, TX driver, RX receiver, CDR, specific to the left (L) side or right (R) side of the device. High speed positive differential receiver channels. Specific to the left (L) side or right (R) side of the device. High speed negative differential receiver channels. Specific to the left (L) side or right (R) side of the device. High speed positive differential transmitter channels. Specific to the left (L) side or right (R) side of the device. High speed negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device. High speed differential reference clock positive, or CMU receiver channels, specific to the left (L) side or right (R) side of the device. REFCLK_[L,R][0:7]n GXB_CMURX_[L,R][0:7]n Input High speed differential reference clock complement, or CMU complementary receiver channel, specific to the left (L) side or right (R) side of the device. GXB_CMUTX_[L,R][0:7]p GXB_CMUTX_[L,R][0:7]n RREF_[L,R][0:1] Output CMU transmitter channels, specific to the left (L) side or right (R) side of the device. Input Reference resistor for transceiver, specific to the left (L) side or right (R) side of the device. Notes: (1) These pin definitions are prepared based on the device with the largest density, HC4GX35. Refer to the pin list for the availability of pins in each density. (2) Refer to HardCopy IV Pin Connections Guidelines and Datasheet for the recommended operating voltage. PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Pin Definitions Page 22 of 24 VREFB8CN0 7C 7B 7A VREFB7CN0 VREFB7BN0 VREFB7AN0 Transceiver Block (QR1) VREFB8BN0 PLL_T2 VREFB6AN0 VREFB8AN0 PLL_T1 VREFB6CN0 8C 6A 8B 6C 1A 8A 1C VREFB1CN0 VREFB1AN0 Transceiver Block (QL1) Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 PLL_R2 Transceiver Block (QL0) Transceiver Block (QR0) PLL_L2 3A 3B 3C VREFB3AN0 VREFB3BN0 VREFB3CN0 PLL_B1 PLL_B2 4C 4B 4A VREFB4CN0 VREFB4BN0 VREFB4AN0 Notes: 1. This is a top view of the silicon die. For flip chip packages, the die is mounted upside down in the package; therefore, to obtain the top package view, flip this diagram on its vertical axis. 2. This is a pictorial representation only to get an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations. PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Bank & PLL Diagram Page 23 of 24 Pin Information for HardCopy® IV HC4GX25LF1152 Version 1.0 Version Number 1.0 Date 02/05/2010 PT-HC4GX25LF1152-1.0 Copyright © 2010 Altera Corp. Changes Made Initial release. Revision History Page 24 of 24