® Configuration Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. VCCD_PLL7 VCCA_PLL7 GNDA_PLL7 GNDA_PLL7 FPLL7CLKp FPLL7CLKn VREFB2N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 K25 J26 K26 J25 C34 C33 R30 F30 G31 D33 D32 H29 G30 E32 E31 J28 K27 E34 D34 J30 J29 F32 F31 K30 K29 INPUT INPUT VREFB2N0 DIFFIO_TX51p DIFFIO_TX51n DIFFIO_RX50p DIFFIO_RX50n DIFFIO_TX50p DIFFIO_TX50n DIFFIO_RX49p DIFFIO_RX49n DIFFIO_TX49p DIFFIO_TX49n DIFFIO_RX48p DIFFIO_RX48n DIFFIO_TX48p DIFFIO_TX48n DIFFIO_RX47p DIFFIO_RX47n DIFFIO_TX47p DIFFIO_TX47n Pin List Page 1 of 55 ® Configuration Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO VREFB2N1 IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_RX46p DIFFIO_RX46n DIFFIO_TX46p DIFFIO_TX46n DIFFIO_RX45p DIFFIO_RX45n DIFFIO_TX45p DIFFIO_TX45n DIFFIO_RX44p DIFFIO_RX44n DIFFIO_TX44p DIFFIO_TX44n VREFB2N1 DIFFIO_RX43p DIFFIO_RX43n DIFFIO_TX43p DIFFIO_TX43n DIFFIO_RX42p DIFFIO_RX42n DIFFIO_TX42p DIFFIO_TX42n DIFFIO_RX41p DIFFIO_RX41n DIFFIO_TX41p DIFFIO_TX41n x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 F34 F33 L26 L25 G33 G32 M26 M25 H32 H31 K28 L28 M30 G34 H34 L29 M29 J32 J31 M28 M27 J34 J33 N27 N26 Pin List Page 2 of 55 ® Configuration Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_RX40p DIFFIO_RX40n DIFFIO_TX40p DIFFIO_TX40n DIFFIO_RX39p DIFFIO_RX39n DIFFIO_TX39p DIFFIO_TX39n DIFFIO_RX38p DIFFIO_RX38n DIFFIO_TX38p DIFFIO_TX38n DIFFIO_RX37p DIFFIO_RX37n DIFFIO_TX37p DIFFIO_TX37n DIFFIO_RX36p DIFFIO_RX36n DIFFIO_TX36p DIFFIO_TX36n DIFFIO_RX35p DIFFIO_RX35n DIFFIO_TX35p DIFFIO_TX35n DIFFIO_RX34p x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 K33 K32 N25 N24 L32 L31 N23 P23 L34 K34 N29 N28 M32 M31 P29 P28 M34 M33 R29 R28 N31 N30 R23 T23 N33 Pin List Page 3 of 55 ® Configuration Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 VREFB2N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO VREFB2N2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_RX34n DIFFIO_TX34p DIFFIO_TX34n VREFB2N2 DIFFIO_RX33p DIFFIO_RX33n DIFFIO_TX33p DIFFIO_TX33n DIFFIO_RX32p DIFFIO_RX32n DIFFIO_TX32p DIFFIO_TX32n DIFFIO_RX31p DIFFIO_RX31n DIFFIO_TX31p DIFFIO_TX31n DIFFIO_RX30p DIFFIO_RX30n DIFFIO_TX30p DIFFIO_TX30n DIFFIO_RX29p DIFFIO_RX29n DIFFIO_TX29p DIFFIO_TX29n CLK0n/DIFFIO_RX_C0n Pin List x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 N32 T29 T28 K31 P32 P31 U24 U23 N34 P34 U31 U30 R32 R31 U29 U28 R34 R33 W29 V29 T32 T31 U27 V28 T34 Page 4 of 55 ® Configuration Function B2 B2 B2 VREFB2N2 VREFB2N2 VREFB2N2 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO CLK1n CLK1p VCCD_PLL1 VCCA_PLL1 GNDA_PLL1 GNDA_PLL1 GNDA_PLL2 GNDA_PLL2 VCCA_PLL2 VCCD_PLL2 IO IO CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO CLK0p/DIFFIO_RX_C0p INPUT INPUT CLK2p/DIFFIO_RX_C1p CLK2n/DIFFIO_RX_C1n INPUT INPUT DIFFIO_RX28p DIFFIO_RX28n DIFFIO_TX28p DIFFIO_TX28n DIFFIO_RX27p DIFFIO_RX27n DIFFIO_TX27p DIFFIO_TX27n DIFFIO_RX26p DIFFIO_RX26n Pin List x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 U34 U32 U33 R27 T25 T26 R26 W26 V26 V25 W27 W34 V34 V32 V31 W31 W30 V23 W23 W33 W32 Y24 Y23 Y32 Y31 Page 5 of 55 ® Configuration Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO VREFB1N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_TX26p DIFFIO_TX26n DIFFIO_RX25p DIFFIO_RX25n DIFFIO_TX25p DIFFIO_TX25n VREFB1N0 DIFFIO_RX24p DIFFIO_RX24n DIFFIO_TX24p DIFFIO_TX24n DIFFIO_RX23p DIFFIO_RX23n DIFFIO_TX23p DIFFIO_TX23n DIFFIO_RX22p DIFFIO_RX22n DIFFIO_TX22p DIFFIO_TX22n DIFFIO_RX21p DIFFIO_RX21n DIFFIO_TX21p DIFFIO_TX21n DIFFIO_RX20p DIFFIO_RX20n x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 W28 Y29 Y34 Y33 Y28 Y27 AE31 AA32 AA31 AA29 AA28 AB31 AB30 AA23 AB23 AB33 AB32 AA26 AA25 AA34 AB34 AB29 AB28 AC32 AC31 Pin List Page 6 of 55 ® Configuration Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB1N1 IO IO DIFFIO_TX20p DIFFIO_TX20n DIFFIO_RX19p DIFFIO_RX19n DIFFIO_TX19p DIFFIO_TX19n DIFFIO_RX18p DIFFIO_RX18n DIFFIO_TX18p DIFFIO_TX18n DIFFIO_RX17p DIFFIO_RX17n DIFFIO_TX17p DIFFIO_TX17n DIFFIO_RX16p DIFFIO_RX16n DIFFIO_TX16p DIFFIO_TX16n DIFFIO_RX15p DIFFIO_RX15n DIFFIO_TX15p DIFFIO_TX15n VREFB1N1 DIFFIO_RX14p DIFFIO_RX14n x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AB24 AC24 AC34 AC33 AB26 AB25 AD32 AD31 AC27 AB27 AE33 AE32 AD26 AD25 AD34 AE34 AC29 AC28 AF32 AF31 AD29 AD28 AC30 AF34 AF33 Pin List Page 7 of 55 ® Configuration Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DIFFIO_TX14p DIFFIO_TX14n DIFFIO_RX13p DIFFIO_RX13n DIFFIO_TX13p DIFFIO_TX13n DIFFIO_RX12p DIFFIO_RX12n DIFFIO_TX12p DIFFIO_TX12n DIFFIO_RX11p DIFFIO_RX11n DIFFIO_TX11p DIFFIO_TX11n DIFFIO_RX10p DIFFIO_RX10n DIFFIO_TX10p DIFFIO_TX10n DIFFIO_RX9p DIFFIO_RX9n DIFFIO_TX9p DIFFIO_TX9n DIFFIO_RX8p DIFFIO_RX8n DIFFIO_TX8p x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AE30 AE29 AG32 AG31 AE28 AE27 AG34 AH34 AF30 AF29 AH33 AH32 AF28 AF27 AJ34 AJ33 AG29 AG28 AJ32 AJ31 AH31 AH30 AL34 AK34 AH29 Pin List Page 8 of 55 ® Configuration Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 VREFB1N2 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO VREFB1N2 FPLL8CLKn FPLL8CLKp GNDA_PLL8 GNDA_PLL8 VCCA_PLL8 VCCD_PLL8 TDI TMS TCK TRST nCONFIG VCCSEL IO IO IO IO IO DIFFIO_TX8n DIFFIO_RX7p DIFFIO_RX7n DIFFIO_TX7p DIFFIO_TX7n DIFFIO_RX6p DIFFIO_RX6n VREFB1N2 INPUT INPUT TDI TMS TCK TRST nCONFIG VCCSEL CS CLKUSR nWS nRS Pin List x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AH28 AK32 AK31 AJ30 AJ29 AL33 AL32 Y30 AM33 AM34 AE26 AF25 AF26 AE25 AL31 AM32 AE24 AM31 AL30 AF24 AH27 AH26 AG26 AG25 AC23 Page 9 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO VREFB8N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO AH25 AL29 AK28 AB22 AM30 AN31 AN32 AP32 AP30 AP31 AG23 AD23 AP29 AN29 AM29 AP28 AM28 AN28 AJ27 AL28 AJ28 AM27 AP27 AL27 AE23 VREFB8N0 DQ17B DQ17B DQ17B DQ17B DQS17B DQ16B DQ16B DQ16B DQ16B DQS16B DQ15B DQ15B DQ15B DQ15B DQS15B Pin List DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQ8B DQS8B DQ7B DQ7B DQ7B DQ7B DQ7B x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ3B DQ3B DQ3B DQ3B DQ1B DQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ3B DQ3B DQ3B DQS3B DQ1B DQ1B Page 10 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 VREFB8N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO VREFB8N1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DQ14B AN26 AL26 AJ26 AK26 AP26 AM26 AC22 AD22 AK25 AF22 AJ24 AL25 AJ25 AN25 AP25 AM25 AE22 AM24 AL24 AJ23 AK23 AP24 AL23 AB21 AC21 DQ14B DQ14B DQ14B DQS14B VREFB8N1 DQ13B DQ13B DQ13B DQ13B DQS13B DQ12B DQ12B DQ12B DQ12B DQS12B Pin List DQ7B DQ7B DQ7B DQ7B DQS7B DQ6B DQ6B DQ6B DQ6B DQ6B DQ6B DQ6B DQ6B DQ6B DQS6B x16/x18 Mode DQ3B DQ3B DQ3B DQ3B DQ3B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B DQ2B x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQS1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 11 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B12 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB8N2 IO IO IO IO IO IO IO DQ11B DQ11B DQ11B DQ11B DQS11B DQ10B DQ10B DQ10B DQ10B DQS10B VREFB8N2 RUnLU DEV_OE DEV_CLRn nCS PLL12_FBn/OUT2n Pin List AB20 AM23 AN23 AP23 AM22 AP22 AN22 AC20 AH21 AH22 AC19 AJ22 AL22 AM21 AP21 AJ21 AL21 AK22 AC18 AH23 AH18 AG20 AH20 AJ18 AJ20 x16/x18 Mode DQ5B DQ5B DQ5B DQ5B DQ5B DQ2B DQ5B DQ2B DQ2B DQ2B DQ2B DQ2B DQ5B DQ5B DQ5B DQS5B DQ2B DQ2B DQ2B DQS2B x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B Page 12 of 55 ® Configuration Function B12 B8 B12 B12 B12 B12 B8 B8 B8 B8 B12 B10 B7 B7 B7 B7 B10 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB8N2 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO VCC_PLL12_OUT VCCD_PLL12 VCCA_PLL12 GNDA_PLL12 GNDA_PLL12 GNDA_PLL6 VCCA_PLL6 VCCD_PLL6 GNDA_PLL6 VCC_PLL6_OUT IO IO IO IO IO PLL12_FBp/OUT2p x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AK20 AB17 AL20 AM20 AN20 AP20 AH19 AJ19 AM19 AN19 AE20 AF20 AE18 AF18 AF19 AF17 AE16 AF16 AE17 AG16 AL19 AK19 AP18 AP19 AM18 PLL12_OUT1n PLL12_OUT1p PLL12_OUT0n PLL12_OUT0p CLK5n CLK5p CLK4n CLK4p CLK7p CLK7n CLK6p CLK6n PLL6_OUT1p Pin List Page 13 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B10 B10 B10 B10 B10 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO VREFB7N0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PLL6_OUT1n PLL6_OUT0p PLL6_OUT0n PLL6_FBp/OUT2p PLL6_FBn/OUT2n AL18 AP17 AN17 AM17 AL17 AC17 AC16 AJ16 AL16 AK17 AK16 AN16 AP16 AM16 AB16 AJ17 AH16 AM15 AH15 AJ15 AP15 AL15 AC15 AP14 AM14 DQ9B VREFB7N0 DQ9B DQ9B DQ9B DQS9B DQ8B DQ8B DQ8B DQ8B DQS8B DQ7B Pin List x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ4B DQ4B DQ1B DQ0B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ0B DQ0B DQ4B DQ1B DQ1B DQ1B DQ1B DQ1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ1B DQ0B DQ0B DQ4B DQ4B DQ4B DQS4B DQ3B DQ3B Page 14 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N1 IO IO IO IO IO IO IO IO IO IO DQ7B DQ7B DQ7B DQS7B AK14 AJ14 AN14 AL14 AD14 AP13 AM13 AH13 AJ13 AN13 AL13 AE14 AP12 AM12 AK13 AH11 AH12 AJ12 AL12 AC14 AP11 AM11 AJ11 AK11 AN11 DQ6B DQ6B DQ6B DQ6B DQS6B DQ5B VREFB7N1 DQ5B DQ5B DQ5B DQS5B DQ4B DQ4B DQ4B DQ4B Pin List x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQS1B DQ0B DQ0B DQ0B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ3B DQ3B DQ3B DQS3B DQ2B DQ2B DQ0B DQ2B DQ2B DQ2B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQS0B DQ2B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ2B DQ2B DQ2B Page 15 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N1 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB7N2 IO DQS4B AL11 AE13 AP10 AM10 AH10 AJ10 AN10 AL10 AD13 AH14 AP9 AM9 AH9 AH8 AJ9 AL9 AC13 AP8 AM8 AJ8 AK8 AN8 AL8 AK10 AG13 DQ3B DQ3B DQ3B DQ3B DQS3B DQ2B DQ2B DQ2B DQ2B DQS2B DQ1B DQ1B DQ1B DQ1B DQS1B VREFB7N2 Pin List x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQS2B DQ1B DQ1B DQ1B DQ1B DQ1B DQ0B DQ1B DQ0B DQ0B DQ0B DQ0B DQ0B DQ1B DQ1B DQ1B DQS1B DQ0B DQ0B DQ0B DQS0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B DQ0B Page 16 of 55 ® Configuration Function B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 VREFB7N2 B7 B15 B15 B15 B15 B15 B15 B15 B15 VREFB7N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO PORSEL nIO_PULLUP PLL_ENA GND nCEO GXB_RX11n GXB_RX11p GXB_TX11n GXB_TX11p GXB_RX10n GXB_RX10p GXB_TX10n GXB_TX10p DQ0B DQ0B DQ0B DQ0B DQS0B PORSEL nIO_PULLUP PLL_ENA nCEO Pin List AP7 AM7 AG8 AH7 AJ7 AL7 AF11 AG11 AG10 AE10 AE9 AF10 AE8 AE7 AF8 AF7 AF9 AM2 AM1 AP5 AP4 AK2 AK1 AM5 AM4 x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 DQ0B DQ0B DQ0B DQ0B DQS0B Page 17 of 55 ® Configuration Function B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 B15 NC NC B14 B14 B14 B14 B14 B14 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. RREFB15 REFCLK0_B15n REFCLK0_B15p REFCLK1_B15n REFCLK1_B15p VCCA VCCA VCCA GXB_RX8n GXB_RX8p GXB_TX8n GXB_TX8p GXB_RX9n GXB_RX9p GXB_TX9n GXB_TX9p NC NC VCCA GXB_RX7n GXB_RX7p GXB_TX7n GXB_TX7p GXB_RX6n GXB_RX6p x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AH4 AK5 AK4 AH2 AH1 AC11 AA8 AC9 AF2 AF1 AF5 AF4 AD2 AD1 AD5 AD4 W7 W8 W12 AB2 AB1 AB5 AB4 Y2 Y1 Pin List Page 18 of 55 ® Configuration Function B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B14 B13 B13 B13 B13 B13 B13 B13 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. GXB_TX6n GXB_TX6p RREFB14 REFCLK0_B14n REFCLK0_B14p REFCLK1_B14n REFCLK1_B14p VCCA VCCA VCCA GXB_RX4n GXB_RX4p GXB_TX4n GXB_TX4p GXB_RX5n GXB_RX5p GXB_TX5n GXB_TX5p GXB_RX3n GXB_RX3p GXB_TX3n GXB_TX3p GXB_RX2n GXB_RX2p GXB_TX2n x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 Y5 Y4 V4 V2 V1 U7 U6 W11 U8 W9 R2 R1 R5 R4 N2 N1 N5 N4 L2 L1 L5 L4 J2 J1 J5 Pin List Page 19 of 55 ® Configuration Function B13 B13 B13 B13 B13 B13 B13 B13 B13 B13 B13 B13 B13 B13 B4 B4 B4 B4 B4 B4 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. GXB_TX2p RREFB13 REFCLK0_B13n REFCLK0_B13p REFCLK1_B13n REFCLK1_B13p VCCA VCCA VCCA GXB_RX0n GXB_RX0p GXB_TX0n GXB_TX0p GXB_RX1n GXB_RX1p GXB_TX1n GXB_TX1p GND GND TDO MSEL3 MSEL2 MSEL1 MSEL0 IO TDO MSEL3 MSEL2 MSEL1 MSEL0 Pin List x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 J4 G4 G2 G1 E5 E4 R11 N8 R9 E2 E1 C5 C4 C2 C1 A5 A4 J8 J7 H10 H11 J10 J9 K10 M13 Page 20 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO VREFB4N0 IO IO IO IO IO IO IO IO IO IO IO IO L13 J11 K11 H13 H14 D7 F7 G7 H8 C7 A7 M15 E10 D8 B8 E8 F8 C8 A8 L14 D9 F9 G8 G9 C9 DQS0T DQ0T DQ0T DQ0T DQ0T VREFB4N0 DQS1T DQ1T DQ1T DQ1T DQ1T DQS2T DQ2T DQ2T DQ2T Pin List x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQS0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQS1T DQ1T DQ1T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T Page 21 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N0 VREFB4N0 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB4N1 IO IO IO DQ2T A9 J13 D10 B10 F10 G10 C10 A10 N17 M16 D11 B11 E11 F11 C11 A11 J14 D12 F12 G12 G11 E13 C12 A12 N18 DQS3T DQ3T DQ3T DQ3T DQ3T DQS4T DQ4T DQ4T DQ4T DQ4T DQS5T DQ5T DQ5T DQ5T VREFB4N1 DQ5T Pin List DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T x16/x18 Mode DQ0T DQS0T DQ0T DQ0T DQ0T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ2T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ0T DQ2T DQ2T DQ2T DQ0T DQ0T DQ0T DQS0T DQ0T DQ0T DQ0T DQ2T DQ2T DQ0T DQS2T DQ2T DQ2T DQ2T Page 22 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DQS6T DQ6T DQ6T DQ6T D13 B13 F13 G13 C13 A13 M17 N19 D14 B14 F14 E14 C14 A14 M19 D15 A15 F15 G15 C15 G14 F19 C16 A16 B16 DQ6T DQS7T DQ7T DQ7T DQ7T DQ7T DQS8T DQ8T DQ8T DQ8T DQ8T DQS9T DQ9T DQ9T Pin List DQS3T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T DQ3T x16/x18 Mode DQ1T DQ1T DQ1T DQ1T DQ1T DQS1T DQ1T DQ1T DQ1T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ0T DQ0T DQ0T DQ0T DQ0T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQ4T DQ1T DQ1T DQ1T DQ1T DQ1T DQ0T DQ0T DQ0T DQ0T DQ0T DQ4T DQ4T DQ1T DQ1T DQ0T DQ0T DQS4T DQ4T DQ4T DQ4T Page 23 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B4 B4 B4 B4 B4 B4 B9 B9 B9 B9 B9 B9 B4 B4 B4 B4 B9 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 VREFB4N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO VREFB4N2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCC_PLL5_OUT VCCD_PLL5 VCCA_PLL5 GNDA_PLL5 GNDA_PLL5 GNDA_PLL11 GNDA_PLL11 VCCA_PLL11 VCCD_PLL11 DQ9T VREFB4N2 F16 E16 D16 G16 G18 F18 F17 E17 B17 A17 D17 C17 A19 A18 D18 C18 H16 H17 K16 J16 J17 J18 K18 K17 J19 DQ9T PLL5_FBn/OUT2n PLL5_FBp/OUT2p PLL5_OUT0n PLL5_OUT0p PLL5_OUT1n PLL5_OUT1p CLK12n CLK12p CLK13n CLK13p Pin List x16/x18 Mode DQ4T DQ1T DQ4T DQ4T DQ1T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ0T Page 24 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B11 B3 B3 B3 B3 B11 B11 B11 B11 B11 B11 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. VCC_PLL11_OUT IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VREFB3N0 IO IO IO IO IO CLK14p CLK14n CLK15p CLK15n PLL11_OUT0p PLL11_OUT0n PLL11_OUT1p PLL11_OUT1n PLL11_FBp/OUT2p PLL11_FBn/OUT2n PGM2 PGM1 PGM0 ASDO nCSO CRC_ERROR DATA0 DATA1 VREFB3N0 DQS10T DQ10T DQ10T DQ10T Pin List K20 B19 C19 D19 E19 A20 B20 C20 D20 E20 F20 G20 H20 H22 N21 G21 G22 J20 J22 E22 D22 C21 A21 F21 D21 DQS5T DQ5T DQ5T DQ5T x16/x18 Mode DQ2T DQ2T DQ2T DQ2T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ1T DQ1T DQ1T DQ1T Page 25 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO DQ10T F22 M21 G23 M22 C22 A22 B22 F23 D23 E23 L22 G24 K22 C23 B23 A23 D24 C24 F24 M23 L23 B25 A24 A25 F25 DQS11T DQ11T DQ11T DQ11T DQ11T DQS12T DQ12T DQ12T DQ12T DQ12T DQS13T DQ13T DQ13T DQ13T Pin List DQ5T DQ5T DQ5T DQ5T DQ5T DQ5T x16/x18 Mode DQ2T DQS2T DQ2T DQ2T DQ2T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ1T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ6T DQ2T DQ2T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ6T DQ6T DQ6T DQ2T DQ2T DQ2T DQS1T DQ1T DQ1T DQ1T DQS6T DQ6T DQ6T DQ6T Page 26 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO VREFB3N1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO C25 D25 E25 H23 K23 C26 B26 E26 F26 D26 A26 B28 A27 A28 C27 C28 D27 F29 C29 A29 D28 E29 D29 B29 K24 DQ13T VREFB3N1 DQS14T DQ14T DQ14T DQ14T DQ14T DQS15T DQ15T DQ15T DQ15T DQ15T DQS16T DQ16T DQ16T DQ16T DQ16T Pin List DQ6T DQ6T DQS7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQS8T DQ8T DQ8T DQ8T DQ8T x16/x18 Mode x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ2T DQ3T DQ3T DQ3T DQ3T DQ3T DQS3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T DQ3T DQ3T DQ3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T DQ1T Page 27 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 x8/x9 Mode B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 VREFB3N2 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO VREFB3N2 IO IO IO IO IO IO IO IO IO IO nSTATUS nCE DCLK CONF_DONE VCCIO2 VCCIO2 VCCIO2 DQS17T DQ17T DQ17T DQ17T DQ17T VREFB3N2 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 RDYnBSY INIT_DONE nSTATUS nCE DCLK CONF_DONE Pin List A31 A30 A32 B32 B31 C30 J27 E28 G29 H28 G25 F27 H25 G27 G26 H26 F28 G28 D31 D30 C32 C31 P25 P26 U25 DQ8T DQ8T DQ8T DQ8T DQ8T x16/x18 Mode DQ3T DQ3T DQ3T DQ3T x32/x36 Mode DQ group for DQS mode Configuration Function DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ1T DQ1T DQ1T Page 28 of 55 ® Configuration Function VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO8 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCT_B15 VCCT_B15 VCCH_B15 VCCH_B15 VCCR VCCR VCCA VCCL_B15 VCCT_B13 VCCT_B13 VCCH_B13 VCCH_B13 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 U26 AC25 AC26 Y25 Y26 AE19 AE21 AF21 AG19 AE12 AE15 AF12 AF15 AA10 Y10 AA11 Y11 AA9 Y9 Y8 AB8 M10 N10 M11 N11 Pin List Page 29 of 55 ® Configuration Function VCCR VCCR VCCA VCCL_B13 VCCT_B14 VCCT_B14 VCCH_B14 VCCH_B14 VCCR VCCR VCCA VCCL_B14 VCCP VCCP VCCP VCCP VCCP VCCP VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 M9 N9 M8 P8 T10 U10 T11 U11 T9 U9 T8 V8 AA12 Y12 M12 N12 T12 U12 J12 J15 K12 K15 H19 J21 K19 Pin List Page 30 of 55 ® Configuration Function VCCIO3 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 K21 AA14 AA16 AA18 AA20 AA22 P15 P17 P19 P21 R14 R16 R18 R20 R22 T13 T15 T17 T19 T21 U14 U16 U18 U20 U22 Pin List Page 31 of 55 ® Configuration Function VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 V13 V15 V17 V19 V21 W14 W16 W18 W20 W22 Y15 Y17 Y19 Y21 A33 T24 T27 T30 T33 V24 AA24 AA27 AA30 AA33 V27 Pin List Page 32 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 V30 V33 AB19 AC12 AD7 AD8 AD9 AD10 AD11 AD12 AD15 AD18 AD21 AD24 AD27 AD30 AD33 AG7 AG9 AG12 AG15 AG17 AG18 AG21 AG24 Pin List Page 33 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AG27 AG30 P33 AG33 AK7 AK9 AK12 AK15 AK18 AK21 AK24 AK27 AK30 AK33 AN7 AN9 AN12 AN15 AN18 AN21 AN24 AN27 AN30 AN33 AN34 Pin List Page 34 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AP33 B7 B9 B12 B15 B18 B21 B24 B27 B30 B33 B34 E7 E9 E12 E15 A2 A3 A6 AA1 AA2 AA3 AA4 AA5 AA6 Pin List Page 35 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AA7 AB3 AB6 AB7 AB9 AB10 AB11 AB12 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AD3 AD6 AE1 AE2 AE3 AE4 AE5 AE6 AF3 Pin List Page 36 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AF6 AG1 AG2 AG3 AG4 AG5 AG6 AH3 AH5 AH6 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AK3 AK6 AL1 AL2 AL3 AL4 AL5 AL6 AM3 Pin List Page 37 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AM6 AN1 AN2 AN3 AN4 AN5 AN6 AP2 AP3 AP6 B1 B2 B3 B4 B5 B6 C3 C6 D1 D2 D3 D4 D5 D6 E3 Pin List Page 38 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 E6 F1 F2 F3 F4 F5 F6 G3 G5 G6 H1 H2 H3 H4 H5 H6 J3 J6 K1 K2 K3 K4 K5 K6 L3 Pin List Page 39 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 L6 M1 M2 M3 M4 M5 M6 M7 N3 N6 N7 P1 P2 P3 P4 P5 P6 P7 P9 P10 P11 P12 R3 R6 R7 Pin List Page 40 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 R8 T1 T2 T3 T4 T5 T6 T7 U1 U2 U3 U4 U5 V3 V5 V6 V7 V9 V10 V11 V12 W1 W2 W3 W4 Pin List Page 41 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 W5 W6 Y3 Y6 Y7 AC10 W10 R10 E18 E21 E24 E27 E30 E33 G17 H7 H9 H12 H15 H18 H21 H24 H27 H30 H33 Pin List Page 42 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 K7 K8 K9 L10 L11 L12 L15 L18 L21 L24 L27 L30 L33 N13 N14 N15 N16 N20 P24 P27 P30 AA13 AA15 AA17 AA19 Pin List Page 43 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 AA21 P14 P16 P18 P20 R13 R15 R17 R19 R21 T14 T16 T18 T20 T22 U13 U15 U17 U19 U21 V14 V16 V18 V20 W13 Pin List Page 44 of 55 ® Configuration Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCPD2 VCCPD2 VCCPD1 VCCPD1 VCCPD8 VCCPD8 VCCPD7 VCCPD7 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 W15 W17 W19 W21 Y14 Y16 Y18 Y20 Y22 AB13 AB14 AB15 P13 P22 R12 V22 Y13 R24 R25 W24 W25 AD19 AD20 AD16 AD17 Pin List Page 45 of 55 ® Configuration Function VCCPD4 VCCPD4 VCCPD3 VCCPD3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 L16 L17 L19 L20 L7 L8 L9 AK29 AF23 AG22 AH24 AB18 AH17 AG14 AF14 AF13 AE11 M14 K13 K14 M18 G19 M20 N22 M24 Pin List Page 46 of 55 ® Configuration Function NC NC PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. x8/x9 Mode x16/x18 Mode x32/x36 Mode DQ group for DQS mode Optional Function(s) DQ group for DQS mode VREF Group Pin Name/Function EP1AGX90EF1152 Bank Number DQ group for DQS mode Pin Information for the Arria GX EP1AGX90E Device Version 1.3 J23 J24 Pin List Page 47 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 Pin Name Pin Type (1st, 2nd, and 3rd Functions) Pin Description VCCINT Power VCCIO[1..4,7,8] Power VCCPD[1..4,7,8] Power GND VREFB[1..4,7,8]N[2..0] Ground Input Device ground pins. Input reference voltage for each I/O bank. If a bank is used for a voltage-referenced I/O standard, then these pins are used as the voltage-referenced pins for that bank. All the VREF pins within a bank are shorted together. VCC_PLL5_OUT Power External clock output VCCIO power for PLL5 clock outputs PLL5_OUT[1..0]p, PLL5_OUT[1..0]n, PLL5_FBp/OUT2p, and PLL5_FBn/OUT2n. This pin should be connected to the voltage level of the target device that PLL5 in bank 9 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. VCC_PLL6_OUT Power External clock output VCCIO power for PLL6 clock outputs PLL6_OUT[1..0]p, PLL6_OUT[1..0]n, PLL6_FBp/OUT2p, and PLL6_FBn/OUT2n. This pin should be connected to the voltage level of the target device that PLL6 in bank 10 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. VCC_PLL11_OUT Power External clock output VCCIO power for PLL11 clock outputs PLL11_OUT[1..0]p, PLL11_OUT[1..0]n, PLL11_FBp/OUT2p, and PLL11_FBn/OUT2n. This pin should be connected to the voltage level of the target device that PLL11 in bank 11 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. VCC_PLL12_OUT Power External clock output VCCIO power for PLL12 clock outputs PLL12_OUT[1..0]p, PLL12_OUT[1..0]n, PLL12_FBp/OUT2p, and PLL12_FBn/OUT2n. This pin should be connected to the voltage level of the target device that PLL12 in bank 12 is driving. Refer to the data sheet for absolute maximum voltage rating on this pin. VCCA_PLL[1,2,5..8,11,12] VCCD_PLL[1,2,5..8,11,12] GNDA_PLL[1,2,5..8,11,12] NC Power Power Ground No Connect 1.2-V analog power for PLL[1,2,5..8,11,12]. 1.2-V digital power for PLL[1,2,5..8,11,12]. Analog ground for PLL[1,2,5..8,11,12]. Do not drive any signals into this pin. PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Supply and Reference Pins 1.2-V internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS, LVPECL, HSTL, SSTL, differential HSTL, and differential SSTL I/O standards. I/O supply voltage pins for banks 1-4, 7, and 8. Each bank can support a different voltage level. Supported voltages are 1.5V, 1.8V, 2.5V, and 3.3V. VCCIO[4,7,8] also support 1.2V for 1.2V HSTL operation.For specific I/O standards supported by Arria GX FPGA refer to the Arria GX Handbook. Dedicated power pins. This 3.3-V supply is used to power the I/O pre-drivers and the 3.3-V/2.5-V buffers of the configuration input pins and the JTAG pins. VCCPD powers the JTAG pins (TCK, TMS, TDI, and TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_Pullup, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. Pin Definitions Page 48 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 nIO_PULLUP Pin Type (1st, 2nd, and 3rd Functions) Pin Description Dedicated Configuration/JTAG Pins Input Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high (1.5 V, 1.8 V, 2.5 V, or 3.3 V) turns off the weak pull-up, while a logic low turns it on. VCCSEL Input Dedicated input that selects which input buffer is used on configuration input pins: nCONFIG, DCLK (when used as an input), DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The 3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. A logic high (VCCPD) selects the 1.8-V/1.5-V input buffer, while a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX II device/microprocessor with flash memory. DCLK Input (PS, FPP) Output (AS) MSEL[3..0] nCE Input Input nCONFIG Input CONF_DONE Bidirectional (open-drain) Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the Arria GX device. In AS mode, DCLK is an output from the Arria GX device that provides timing for the configuration interface. Configuration input pins that set the Arria GX device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic-high level initiates reconfiguration. This is a dedicated configuration Done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. nCEO nSTATUS Output Bidirectional (open-drain) Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. PORSEL Input nCSO I/O, Output Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V) selects a POR time of about 12 ms and a logic low selects a POR time of about 100 ms. Optional/Dual-Purpose Configuration Pins Output control signal from the Arria GX FPGA to the serial configuration device in AS mode that enables the configuration device. Pin Name PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Pin Definitions Page 49 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 Pin Name ASDO Pin Type (1st, 2nd, and 3rd Functions) Pin Description I/O, Output Control signal from the Arria GX FPGA to the serial configuration device in AS mode used to read out configuration data. CRC_ERROR I/O, Output Active-high signal that indicates that the error-detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error-detection circuit is enabled. DEV_CLRn I/O, Input Optional pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. DEV_OE I/O, Input DATA0 I/O, Input Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tristated; when this pin is driven high, all I/O pins behave as defined in the design. Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. DATA[6..1] I/O, Input Dual-purpose configuration input data pins. The DATA[7..0] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. DATA7 I/O, Bidirectional In the PPA configuration scheme, the DATA7 pin presents the RDYnBSY signal after the nRS signal is strobed low. INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. nCS, CS I/O, Input These are chip-select inputs that enable the Arria GX device in the passive parallel asynchronous configuration mode. Drive nCS low and CS high to target a device for configuration. If a design requires an active-high enable, use the CS pin and drive the nCS pin low. If a design requires an active-low enable, use the nCS pin and drive the CS pin high. Configuration will be paused when either signal is inactive. Hold the nCS and CS pins active during configuration and initialization. The design can use these pins as user I/O pins after configuration. nRS I/O, Input Read strobe input pin. A low input directs the device to drive the RDYnBSY signal on the DATA7 pin. In non-PPA schemes, it functions as a user I/O during configuration, which means it is tri-stated. This pin can be used as a user I/O pin after configuration. nWS I/O, Input CLKUSR I/O, Input Active-low write strobe input to latch a byte of data on the DATA pins. This pin can be used as a user I/O pin after configuration. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. RDYnBSY I/O, Output PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Ready not busy output. A high output indicates that the target device is ready to accept another data byte. A low output indicates that the target device is not ready to receive another data byte. This pin can be used as a user I/O pin after configuration. Pin Definitions Page 50 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 Pin Name PGM[2..0] Pin Type (1st, 2nd, and 3rd Functions) Pin Description I/O, Output These output pins control one of eight pages in the memory (either flash or enhanced configuration device) when using a remote system update mode. When not using remote update or local update configuration modes, these pins are user I/O pins. RUnLU I/O, Input Input that selects between remote update and local update. A logic high (1.5 V, 1.8 V, 2.5 V, 3.3 V) selects remote update and a logic low selects local update. When not using remote update or local update configuration modes, this pin is available as general-purpose user I/O pin. TCK TMS TDI TDO TRST Input Input Input Output Input Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active-low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. CLK[1,3]p Clock, Input Clock and PLL Pins Dedicated clock input pins 1 and 3 that can also be used for data inputs. These pins do not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported on these pins. CLK[1,3]n Clock, Input CLK[2,0]p/DIFFIO_RX_C[1,0]p I/O, Clock CLK[2,0]n/DIFFIO_RX_C[1,0]n I/O, Clock CLK[4-7,12-15]p CLK[4-7,12-15]n PLL_ENA FPLL[8..7]CLKp I/O, Clock I/O, Clock Input Clock, Input FPLL[8..7]CLKn Clock, Input PLL5_OUT[1,0]p Output PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. These pins do not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported on these pins. These pins can be used as I/O pins, clock input pins, or positive terminal data pins of differential receiver channels. These pins can be used as I/O pins, negative clock input pins for differential clock input, or negative data pins of differential receiver channels. These pins can be used as I/O pins or clock input pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. Dedicated input pin that drives the optional pllena port of all or a set of PLLs. Dedicated positive clock inputs for fast PLLs (PLLs 7 and 8), which can also be used for data inputs. These pins do not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported on these pins. Dedicated negative clock inputs associated with the FPLL[7,8]CLKp pins, which can also be used for data inputs. These pins do not support OCT Rd and cannot be used as output pins. The programmable weak pull up resistor is not supported on these pins. Optional positive external clock outputs [1,0] from enhanced PLL5. These pins can be differential (two output pin pairs) or single-ended (four clock outputs from PLL5). Pin Definitions Page 51 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 PLL[6..5]_FBp/OUT2p Pin Type (1st, 2nd, and 3rd Functions) Pin Description Output Optional negative external clock outputs [1,0] from enhanced PLL5. If the clock outputs are single-ended, then each pair of pins (i.e., PLL5_OUT0p and PLL5_OUT0n are considered one pair) can be either in-phase or 180° out-ofphase. Output Optional positive external clock outputs [1,0] from enhanced PLL6. These pins can be differential (two output pin pairs) or single-ended (four clock outputs from PLL6). Output Optional negative external clock outputs [1,0] from enhanced PLL6. If the clock outputs are single-ended, then each pair of pins (i.e., PLL6_OUT0p and PLL6_OUT0n are considered one pair) can be either in-phase or 180° out-ofphase. Output Optional positive external clock outputs [1,0] from enhanced PLL11. These pins can be differential (two output pin pairs) or single-ended (four clock outputs from PLL11). Output Optional negative external clock outputs [1,0] from enhanced PLL11. If the clock outputs are single-ended, then each pair of pins (i.e., PLL11_OUT0p and PLL11_OUT0n are considered one pair) can be either in-phase or 180° out-of-phase. Output Optional positive external clock outputs [1,0] from enhanced PLL12. These pins can be differential (two output pin pairs) or single-ended (four clock outputs from PLL12). Output Optional negative external clock outputs [1,0] from enhanced PLL12. If the clock outputs are single-ended, then each pair of pins (i.e., PLL12_OUT0p and PLL12_OUT0n are considered one pair) can be either in-phase or 180° out-of-phase. I/O, Input, Output These pins can be used as I/O pins, positive external feedback input pins, or external clock outputs for PLL[6,5]. PLL[6..5]_FBn/OUT2n I/O, Input, Output PLL[12..11]_FBp/OUT2p I/O, Input, Output PLL[12..11]_FBn/OUT2n I/O, Input, Output DIFFIO_RX[50..1]p IO, Input DIFFIO_RX[50..1]n IO, Input Pin Name PLL5_OUT[1,0]n PLL6_OUT[1,0]p PLL6_OUT[1,0]n PLL11_OUT[1,0]p PLL11_OUT[1,0]n PLL12_OUT[1,0]p PLL12_OUT[1,0]n PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. These pins can be used as I/O pins, negative external feedback input PLL[6,5]_FBp, or negative terminal clock output pins for differential clock output. These pins can be used as I/O pins, positive external feedback input pins, or positive external clock outputs for PLL[12..11]. These pins can be used as I/O pins, negative external feedback input PLL[12..11]_FBp, or negative external clock output pins for differential clock output. Dual-Purpose Differential and External Memory Interface Pins Dual-purpose differential receiver channels. These channels can be used for receiving LVDS-compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Dual-purpose differential receiver channels. These channels can be used for receiving LVDS-compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. Pin Definitions Page 52 of 55 ® Pin Information for the Arria GX EP1AGX90E Device Version 1.3 Pin Name DIFFIO_TX[51..0]p DIFFIO_TX[51..0]n DQS[17..0][T,B] DQ[17..0][T,B] VCCP VCCR VCCT_B[15..13] VCCA VCCH_B[15..13] VCCL_B[15..13] GXB_RX[11..0]p GXB_RX[11..0]n GXB_TX[11..0]p GXB_TX[11..0]n REFCLK[0,1]_B[15..13]p REFCLK[0,1]_B[15..13]n RREFB[15..13] Pin Type (1st, 2nd, and 3rd Functions) Pin Description IO, Output Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS-compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. IO, Output Dual-purpose differential transmitter channels. These channels can be used for transmitting LVDS-compatible signals. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry. The shifted DQS signal can also drive to internal logic. DQ Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Power Power Power Power Power Power I, Input I, Input O, Output O, Output I, Input I, Input I, Input Transceiver (I/O Banks) Pins GX bank [15..13] PCS power. This power is connected to 1.2 V. GX bank [15..13] receiver analog power. This power is connected to 1.2 V. GX bank [15..13] transmitter analog power. This power is connected to 1.2 V. GX bank [15..13] analog power. This power is connected to 3.3 V. GX bank [15..13] transmitter driver analog power. This power is connected to 1.2 V or 1.5 V. GX bank [15..13] VCO analog power. This power is connected to 1.2 V. High-speed positive differential receiver channels. High-speed negative differential receiver channels. High-speed positive differential transmitter channel. High-speed negative differential transmitter channels. High-speed differential I/O reference clock positive. This pin is powered by 1.2-V VCCT_B[15..13]. High-speed differential I/O reference clock negative. This pin is powered by 1.2-V VCCT_B[15..13]. Reference resistor for GX side banks. Note: 1) These descriptions are created based on the Arria GX device with the largest density, EP1AGX90E. PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Pin Definitions Page 53 of 55 Pin Information for the Arria® GX EP1AGX90E Device Version 1.3 FPLL VREFB3N0 VREFB3N1 VREFB3N2 EPLL EPLL VREFB4N0 VREFB4N1 VREFB4N2 PLL11 PLL5 B3 B4 B2 B13 Bank11 Bank9 VREFB2N0 VREFB2N VREFB2N2 PLL7 EP1AGX90EF1152 B14 FPLL PLL1 FPLL B1 B15 VREFB1N0 VREFB1N VREFB1N2 PLL2 B8 FPLL EPLL PLL8 VREFB8N0 VREFB8N1 B7 Bank12 Bank10 VREFB8N2 EPLL PLL12 PLL6 VREFB7N0 VREFB7N1 VREFB7N2 Notes: 1. This is a top view of the silicon die. For flip-chip packages, the die is mounted upside-down in the package; therefore, to obtain the top package view, flip this diagram on its vertical axis. 2. This is only a pictorial representation to get an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations. PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Bank & PLL Diagram Page 54 of 55 Pin Information for the Arria® GX EP1AGX90E Device Version 1.3 Version 1.0 1.1 Date 5/4/2007 12/21/2007 1.2 1.3 9/8/2008 5/21/2009 PT-EP1AGX90E-1.3 Copyright © 2009 Altera Corp. Changes Made Initial release Updated pin descriptions for VCCINT, VCCIO, TEMPDIODEp, and TEMPDIODEn Removed Bank 7 reference for GND pin AF7 (F1152) in Pin List Removed RUP4,RUP7,RDN4,RDN7 from Pin List and Pin Definitions Removed TEMPDIODEp and TEMPDIODEn from Pin List and Pin Definitions Revision History Page 55 of 55