ESD7421, SZESD7421 ESD Protection Diodes Micro−Packaged Diodes for ESD Protection The ESD7421 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, automotive sensors, infotainment, MP3 players, digital cameras and many other applications where board space comes at a premium. http://onsemi.com Pin 1 Pin 2 Specification Features • • • • • • • Low Capacitance 0.3 pF Low Clamping Voltage Low Leakage 100 nA Response Time is < 1 ns IEC61000−4−2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM 5M G XDFN2 (SOD−882) CASE 711AM 5 M G = Specific Device Code = Date Code = Pb−Free Package ORDERING INFORMATION MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Air Value Unit ±12 ±15 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 300 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) Package Shipping† ESD7421N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel SZESD7421N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 1 1 Publication Order Number: ESD7421/D ESD7421, SZESD7421 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR IR VRWM VBR1 VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM VBR1 Breakdown Voltage @ IT VBR2 Breakdown Voltage @ IT IT IT VC VBR2 VRWM IR IPP Bi−Directional TVS Test Current *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Symbol Conditions Reverse Working Voltage VRWM Pin 1 to GND Pin 2 to GND Breakdown Voltage VBR1 IT = 1 mA, Pin 1 to GND 16.5 Breakdown Voltage VBR2 IT = 1 mA, Pin 2 to GND 10.5 Reverse Leakage Current IR VRWM = 5 V, I/O Pin to GND 100 Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact See Figures 2 and 3 Clamping Voltage TLP (Note 3) VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 35 38.1 −21 −29.5 Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 Parameter Min Typ Max Unit 5 5 16 10 V V 14 V 500 nA V 0.6 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. For test procedure see Figure 5 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. http://onsemi.com 2 ESD7421, SZESD7421 1.0 0.9 CAPACITANCE (pF) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −5 −4 −3 −2 −1 0 1 2 3 4 5 VBias (V) 120 20 100 0 80 −20 VOLTAGE (V) VOLTAGE (V) Figure 1. Typical CV Characteristic Curve Pin1 to GND (GND connected to Pin2) 60 40 −40 −60 20 −80 0 −100 −20 −25 0 25 50 75 TIME (ns) 100 125 150 −120 −25 Figure 2. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Pin1 to GND (GND connected to Pin2) 0 25 50 75 TIME (ns) 100 125 Figure 3. IEC61000−4−2 −8 kV Contact ESD Clamping Voltage Pin1 to GND (GND connected to Pin2) http://onsemi.com 3 150 ESD7421, SZESD7421 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 4. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 5. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger http://onsemi.com 4 20 −20 18 −18 16 −16 14 −14 CURRENT (A) CURRENT (A) ESD7421, SZESD7421 12 10 8 −12 −10 −8 6 −6 4 −4 2 −2 0 0 0 NOTE: 5 10 15 20 25 30 35 40 0 45 −5 −10 −15 −20 −25 −30 VOLTAGE (V) VOLTAGE (V) Figure 6. Positive TLP IV Curve Figure 7. Negative TLP IV Curve −35 TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 8. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 9 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. S Attenuator ÷ 50 W Coax Cable 10 MW IM 50 W Coax Cable VM DUT VC Oscilloscope Figure 8. Simplified Schematic of a Typical TLP System Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms http://onsemi.com 5 ESD7421, SZESD7421 PACKAGE DIMENSIONS XDFN2 1.0x0.6, 0.65P (SOD−882) CASE 711AM ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C A B D ÉÉ PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW NOTE 3 0.10 C A MILLIMETERS MIN MAX 0.34 0.44 −−− 0.05 0.43 0.53 1.00 BSC 0.60 BSC 0.65 BSC 0.20 0.30 0.10 C A1 C SIDE VIEW RECOMMENDED SOLDER FOOTPRINT* SEATING PLANE 1.20 e 2X b e/2 0.05 M C A B 2X 0.47 0.60 PIN 1 1 2X L 0.05 DIMENSIONS: MILLIMETERS M *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. C A B BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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