MAXIM MAX31782

19-5327; Rev 0; 6/10
系统管理微控制器
杂系统的监测和控制提供完整的解决方案。
I/O 资源包括温度和电压的高精度测量单元、PWM 输出、定
时器输入和 GPIO，支持系统关键参数 (例如：温度、电压、
风扇速度和机箱介入等) 的监测和控制。器件能够直接检测
连接成二极管的晶体管远端温度传感器，通过片上I2 C 主机
接口扩展外部数字温度传感器IC 的数量。独立的I2 C从机接
口除了提供片上闪存的在系统编程加密保护外，还可以方便
地与主处理器通信。
高度 通 用 的 C 编 译 器 和 开发软件能 够对闪存 编 程和 通 过
JTAG 口及相应的硬件进行在电路调试，简化了开发过程。
所有这些功能组合使得器件成为一个高度灵活的设计平台，
设计人员可以简便地创建一个定制的复杂系统管理方案。
应用
特性
♦♦MAXQ20高性能16位 µC
♦♦高效 C 语言编程
♦♦36K字程序存储器
32K字闪存程序存储器
4K字ROM 程序存储器
♦♦1K字数据 RAM
♦♦具有 7 输入复用器的12位 ADC，用于温度和电压监测
♦♦温度测量模拟前端
0.125°C分辨率
二极管串联电阻抵消电路
♦♦6 路定时器 /风扇转速计输入
♦♦6 路16位PWM 输出，用于风扇速度控制或D/A 转换器
♦♦5位GPIO 端口
♦♦SMBus™/I2C兼容从机接口，用于带闪存编程加密保护的
主机通信
网络交换机 / 路由器
♦♦I2C兼容主机接口，用于从机扩展
基站
♦♦上电复位和低电压监测
服务器
♦♦JTAG端口支持在系统调试和闪存编程
智能电网系统
♦♦内部振荡器无需晶体
♦♦2.7V至5.5V工作电压范围
定购信息
典型工作电路在数据资料的最后给出。
TEMP RANGE
PIN-PACKAGE
MAX31782ETL+
PART
-40NC to +85NC
40 TQFN-EP*
MAX31782ETL+T
-40NC to +85NC
40 TQFN-EP*
+表示无铅(Pb)/ 符合 RoHS 标准的封装。
T= 卷带包装。
*EP= 裸焊盘。
SMBus 是IntelCorp. 的商标。
注意：该器件某些版本的规格可能与发布的规格不同，会以勘误表的形式给出。通过不同销售渠道可能同时获得器件的多个版本。欲了解器件勘误
表信息，请点击：china.maxim-ic.com/errata。
________________________________________________________________ Maxim Integrated Products 1
本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，
或访问Maxim的中文网站：china.maxim-ic.com。
MAX31782
概述
MAX31782 基于高性能 MAXQ2016 位微控制器核，具有
超大容量的程序/ 数据闪存存储器和 RAM 数据存储器，为复
MAX31782
系统管理微控制器
ABSOLUTE MAXIMUM RATINGS
P6.0–P6.4 Continuous Source Current....20mA each, 50mA total
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+260NC
Soldering Temperature (reflow).......................................+260NC
VDD to VSS............................................................-0.5V to +5.5V
All Other Pins to VSS except
REG18 and REG25............................... -0.5V to (VDD + 0.5V)*
SCL, SDA, MSDA, MSCL, P6.0–P6.4
Continuous Sink Current..................... 20mA each, 50mA total
*Subject to not exceeding +5.5V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +85NC, unless otherwise noted.)
PARAMETER
SYMBOL
MAX
UNITS
2.7
5.5
V
VIH
0.7 x
VDD
VDD +
0.3
V
VIL
-0.3
+0.3 x
VDD
V
VDD Operating Voltage Range
VDD
Input Logic 1
Input Logic 0
CONDITIONS
(Note 1)
MIN
TYP
Input Logic-High: SCL, SDA,
MSDA
VI2C_IH
2.7V P VDD P 3.6V (Note 1)
2.1
VDD +
0.3
V
Input Logic-Low: SCL, SDA,
MSDA
VI2C_IL
2.7V P VDD P 3.6V (Note 1)
-0.5
+0.8
V
0.7 x
VDD
Input Logic-High: GPIO
(Including SCL, SDA, MSCL, and
MSDA Under Full VDD Range)
VIH1
(Note 1)
Input Logic-Low: GPIO
(Including SCL, SDA, MSCL, and
MSDA Under Full VDD Range)
VIL1
(Note 1)
V
0.3 x
VDD
V
DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
Supply Current
SYMBOL
TYP
MAX
UNITS
ICPU
Assuming 100% CPU duty cycle (Note 2)
CONDITIONS
MIN
1.73
2.34
mA
ISTOP
(Note 2)
830
1250
µA
7
IPROGRAM
VBO
Monitors VDD (Note 1)
Brownout Hysteresis
VBOH
Monitors VDD (Note 1)
Internal System Clock
fMOSC
Brownout Voltage
Initial tolerance, TA = +25NC, VDD = 5.5V
System Clock Error (Note 3)
fERR:MOSC +25NC P TA P +85NC
-40NC P TA P +25NC
2
2.40
-1
2.46
mA
2.55
V
30
mV
4.0
MHz
+1
-2
+1
-5.5
+0.6
%
系统管理微控制器
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
System Clock Startup
SYMBOL
tSU:MOSC
CONDITIONS
From POR, MOSC inactive
Output Logic-Low: SDA, MSCL,
MSDA, P6.0–P6.4, PWM.0–PWM.5
VOL1
IOL = 4mA (Note 1)
Output Logic-High: P6.0–P6.4,
PWM.0–PWM.5
VOH1
IOH = -2mA (Note 1)
GPIO Mode Pullup Current
IPU
MIN
VPIN = VSS, VDD = 3.3V
ADC Voltage Conversion Time
tCONV_V
(Note 4)
ADC Temperature Conversion
Time
tCONV_T
(Note 4)
0.4
VDD 0.5
38
ADC Internal Reference Initial
Accuracy (+25NC)
ADC External Reference Buffer
Accuracy
IADC
VFS
ADC Measurement Resolution
VLSB
AD0P–AD5P Input Resistance
V
55
107
FA
150
µs
7
ms
-1
+1
%
-0.5
+0.5
%
-1
+1
mV
V
%
Q0.25
This current is in addition to ICPU
2.2
ADGAIN = 0, factory set, internal reference
1.213
1.225
1.237
ADGAIN = 1, factory set, internal reference
5.445
5.5
5.555
ADGAIN = 0
300
ADGAIN = 1
1343
ADC Bit Resolution
RIN
12
Bits
MI
INL
Q4
DNL
Q1
Remote Temperature
Measurement Error
(MAX31782 Error Only)
VOFFSET
LSB
LSB
LSB
Q2
-3
+3
TA = 0NC to +60NC,
TDIODE = +60NC to +120NC
-1.5
+1.5
TA = 0NC to +60NC,
TDIODE = -45NC to +120NC
-1.75
+1.75
TA = -40NC to +85NC,
TDIODE = +60 to +120NC
-2.75
+2.75
TA = -40NC to +85NC,
TDIODE = -45NC to +120NC
-3.0
+3.0
TA = -40NC to +85NC
V
15
ADC Differential Nonlinearity
Internal Temperature
Measurement Error
mA
FV
ADC Integral Nonlinearity
ADC Offset
V
128
(Note 5)
ADC Full-Scale Input Voltage
(Note 6)
UNITS
MOSC
Cycles
1.225
VERR
ADC Internal Reference
Temperature Drift
ADC Operating Current
MAX
1000
ADC Internal Reference
ADC Voltage Measurement Error
TYP
NC
NC
3
MAX31782
DC ELECTRICAL CHARACTERISTICS (continued)
MAX31782
系统管理微控制器
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
Flash Erase Time
Flash Programming Time per
Word
Flash Endurance
SYMBOL
CONDITIONS
MIN
TYP
MAX
tME
Mass erase
20
40
tPE
Page erase
20
40
20
40
tPROG
NFLASH
Data Retention
UNITS
ms
Fs
TA = +50NC
20,000
Write
Cycles
TA = +50NC
100
Years
ELECTRICAL CHARACTERISTICS: I2C-COMPATIBLE INTERFACE
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 1)
PARAMETER
SYMBOL
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and START Condition
tBUF
Hold Time (Repeated)
START Condition
tHD:STA
CONDITIONS
Timeout not enabled (Note 7)
(Note 8)
MIN
TYP
10
MAX
UNITS
400
kHz
1.3
Fs
0.6
Fs
Low Period of SCL Clock
tLOW
1.3
Fs
High Period of SCL Clock
tHIGH
0.6
Fs
Setup Time for a (Repeated)
START Condition
tSU:STA
0.6
Fs
Data Hold Time (Note 9)
tHD:DAT
Data Setup Time
Receive
0
Transmit
300
ns
tSU:DAT
100
Rise Time of Both SDA and
SCL Signals
tR
(Note 10)
20 +
0.1CB
300
ns
Fall Time of Both SDA and
SCL Signals
tF
(Note 10)
20 +
0.1CB
300
ns
Setup Time for STOP
Condition
tSU:STO
Spike Pulse Width That Can Be
Suppressed by Input Filter
tSP
SCL, SDA Capacitive Loading
CB
SMBus Timeout
4
ns
0.6
(Note 11)
Fs
0
25
50
30
ns
400
pF
35
ms
系统管理微控制器
MAX31782
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 2)
PARAMETER
JTAG Logic Reference
SYMBOL
CONDITIONS
MIN
TYP
MAX
VDD/2
VREF
UNITS
V
TCK High Time
tTH
1
Fs
TCK Low Time
tTL
1
Fs
TCK Low to TDO Output
0.125
tTLQ
Fs
TMS, TDI Input Setup to TCK
High
tDVTH
0.30
Fs
TMS, TDI Input Hold after TCK
High
tTHDX
0.25
Fs
ll voltages are referenced to ground (VSS). Currents entering the IC are specified positive and currents exiting the IC are
Note 1: A
negative.
Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.
Note 3: Guaranteed by design.
Note 4: ADCCLK = SYSCLK/16. This is following an initial conversion time of approximately 80µs.
Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.
Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.
Note 7: Minimum SCL frequency applies only when in I2C master mode.
Note 8: After this period, the first clock pulse can be generated.
Note 9: This device internally provides a hold time of at least 25ns for the SDA signal (referenced to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 10: CB—Total capacitance of one bus line in pF.
Note 11: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
5
MAX31782
系统管理微控制器
SDA
tBUF
tF
tLOW
tSP
tHD:STA
SCL
tHD:STA
tHIGH
tR
tHD:DAT
STOP
tSU:STA
tSU:STO
tSU:DAT
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
图1.I2C 兼容总线时序图
tTL
TCK
VREF
tTH
TMS/TDI
tDVTH
tTHDX
TDO
tTLQ
图2.JTAG 时序图
6
系统管理微控制器
VSS
26 25
TACH.3
PWM.2
TACH.2
PWM.1
TACH.1
28 27
REG18
30 29
PWM.0
REG25
TACH.0
TOP VIEW
24 23 22
21
SDA 31
20 PWM.3
SCL 32
19 TACH.4
P6.4/TBA 33
18 PWM.4
P6.3/TDO 34
17 TACH.5
16 PWM.5
P6.2/TMS/TBB 35
MAX31782
VSS 36
15 MSCL
14 MSDA
P6.1/TDI 37
P6.0/TCK 38
13 RST
EP
+
AD5N 39
12 AD2N
11 AD2P
VSS
AD4P
AD3N
AD3P
6
7
8
9
10
AD1N
5
VDD
4
AD1P
3
AD0P
2
AD0N
1
AD4N
AD5P 40
TQFN
(6mm × 6mm × 0.75mm)
引脚说明
引脚
名称
1
AD4N
2, 21, 36
VSS
3
AD4P
4
AD3N
5
AD3P
6
AD0P
7
AD0N
8
AD1P
9
VDD
10
AD1N
11
AD2P
12
AD2N
13
RST
MSDA
14
15
MSCL
16
PWM.5
17
TACH.5
18
PWM.4
19
TACH.4
功能
ADC.4电压测量的参考地。
电源回路节点。
ADC电压检测输入，相对于AD4N 测量。
ADC.3电压测量的参考地。使能时连接至外部参考端。
ADC电压检测输入，相对于AD3N 测量。
ADC电压检测输入，相对于AD0N 测量。
ADC.0电压测量的参考地。
ADC电压检测输入，相对于AD1N 测量。
输入电源，+2.7V 至+5.5V 输入范围。通过一个 0.1µF电容将VDD 旁路至 VSS。
ADC.1电压测量的参考地。
ADC电压检测输入，相对于AD2N 测量。
ADC.2电压测量的参考地。
低电平有效复位，该引脚的低电平电压将复位IC。
主控制器的I2C兼容双向数据线，禁止时该引脚可以用作 GPIOP2.7。
主控制器的I2C兼容时钟，禁止时该引脚可以用作 GPIOP2.6。
第 5路 PWM 输出，禁止时该引脚可以用作 GPIO。
第 5路转速计输入，禁止时该引脚可以用作 GPIO。
第 4 路 PWM 输出，禁止时该引脚可以用作 GPIO。
第 4 路转速计输入，禁止时该引脚可以用作 GPIO。
7
MAX31782
引脚配置
MAX31782
系统管理微控制器
引脚说明(续)
引脚
功能
PWM.3
第3 路 PWM 输出，禁止时该引脚可以用作 GPIO。
22
REG18
23
TACH.3
通过一个1µF电容和一个10nF 高频电容将 REG18 旁路至 VSS，请勿用于外部电路。
第3 路转速计输入，禁止时该引脚可以用作 GPIO。
24
PWM.2
第2 路 PWM 输出，禁止时该引脚可以用作 GPIO。
25
TACH.2
第2 路转速计输入，禁止时该引脚可以用作 GPIO。
26
PWM.1
第1路 PWM 输出，禁止时该引脚可以用作 GPIO。
27
TACH.1
第1路转速计输入，禁止时该引脚可以用作 GPIO。
28
PWM.0
第 0 路 PWM 输出，禁止时该引脚可以用作 GPIO。
29
REG25
通过一个1µF电容和一个10nF 高频电容将 REG25 旁路至 VSS，请勿用于外部电路。
第 0 路转速计输入，禁止时该引脚可以用作 GPIO。
20
8
名称
30
TACH.0
31
SDA
从机I2C兼容双向数据线，禁止时该引脚可以用作 GPIO。
32
SCL
从机I2C兼容时钟，禁止时该引脚可以用作 GPIO。
33
P6.4/TBA
可编程I/O引脚，可替代功能：定时器 /计数器TBA。
34
P6.3/TDO
可编程I/O引脚，可替代功能：JTAGTDO。
35
P6.2/TMS/TBB
37
P6.1/TDI
可编程I/O引脚，可替代功能：JTAGTDI。
38
P6.0/TCK
可编程I/O引脚，可替代功能：JTAGTCK。
39
AD5N
40
AD5P
—
EP
可编程I/O引脚，可替代功能：定时器 /计数器TBB、JTAGTMS。
ADC.5电压测量的参考地。
ADC电压检测输入，相对于AD5N 测量。
裸焊盘。与IC之间无电气连接，连接至 VSS。
系统管理微控制器
PROGRAM
MEMORY SPACE
FFFFh
8FFFh
4K x 16 UTILITY ROM
8000h
7FFFh
32K x 16 USER
PROGRAM MEMORY
0000h
MAX31782
CLOCK CONTROL,
WATCHDOG TIMER, AND
POWER MONITOR
RST
CKCN
P6.n
n = 0−4
IC
03FFh
0000h
ADDRESS
GENERATION
IC
IP
IMR
LOOP COUNTERS
IIR
DATA POINTERS
DP[0], DP[1],
FP = (BP+OFFS)
LC[n]
DPC
BOOLEAN
VARIABLE
MANIPULATION
ACCUMULATORS
(16)
I2C
SLAVE
MAXQ20 CORE
SYSTEM MODULES/
REGISTERS
INSTRUCTION
DECODE
(src, dst TRANSPORT
DETERMINATION)
AP
APC
PSF
CURRENT
SOURCES
ADCH
6-CHANNEL PULSE-WIDTH
MODULATOR
6-CHANNEL TACHOMETER
TACH.5
12-BIT
ADC
PWM.5
CPU CLOCK
MULTIPLY
ACCUMULATE
UNIT
(MAC)
VDD
TACH.1
TACH.2
TACH.3
TACH.4
PWM.0
PWM.1
PWM.2
PWM.3
PWM.4
AD0P
AD1P
AD2P
AD3P
AD4P
MUX
AD5P
INTERNAL TEMP
SCL
SDA
1K x 16 SRAM
MEMORY MANAGEMENT
UNIT (MMU)
INTERRUPT
LOGIC
GPIO
4K x 16 UTILITY ROM
SP
WDCN
I2C
MASTER
8000h
TACH.0
MSDA
MSCL
STACK MEMORY
16 x 16
FFFFh
8FFFh
DATA
MEMORY SPACE
9
MAX31782
方框图
MAX31782
系统管理微控制器
详细说明
MAX31782 采用16 位 MAXQ20 微控制器核，带有16 个累
加器和16 级硬件堆栈。三个存储区提供闪存应用程序存储
空间、固定用途 ROM 程序存储空间和 RAM 存储器。集成专
用外设用于风扇速度的 PWM 控制、读取风扇转速计并通
过连接成二极管的晶体管进行温度监测。该器件还具有 2个
I2C 兼容通信外设。I2C 兼容的从机外设用于实现主机与器件
之间的通信 ；此外，I2 C 兼容的主控制器接口用于支持与远
端I2 C 数字温度传感器或其它I2 C 器件的通信。器件还提供
通用I/O 引脚 (GPIO)，利用系统管理微处理器实现中断功能
及其它电路的控制。MAXQ20 核以及这些专用外设为系统
和热管理提供灵活的解决方案。由于可通过I2 C 兼容接口升
级程序和数据闪存内容，使得该方案设计更为灵活。程序闪
存的更新受256 位用户密码保护，防止非法写操作。
以下章节简要介绍了 MAX31782 系统管理微控制器的主要
特性，器件特性的详细说明请参考其它文档 部分列出的用户
指南。
MAXQ20 核架构
器 件 包 含 一 个 带 有 闪 存 的 MAXQ20 低 成 本、 高 性 能、
CMOS、全静态、16 位 RISC 微控制器，采用先进的、基于
16 个累加器的16位 RISC架构。由于指令包含操作码和数据，
可以在一个周期内完成指令读取和操作，无需流水线操作。
高效的系统内核由16 个累加器和16 级硬件堆栈支持，可实
现快速子程序调用和任务切换。通过 3个内部数据指针快速、
高效地处理数据。多数据指针允许多个函数操作数据存储
器，不必每次保存和恢复数据指针。数据指针可以在操作中
自动递增或递减，无需软件干预。
指令集由对寄存器和存储器进行操作的固定长度、16 位指
令组成。指令集高度正交，算术和逻辑操作可以使用累加器
和任何寄存器。特殊功能寄存器控制外围设备，并细分成寄
存器模块。采用模块化产品架构，能够重复使用现有产品的
开发程序设计新器件、新模块。
器件架构基于传送触发，这意味着对某一寄存器的写或读
操作还会引发其它效应。这些效应构成了由汇编定义的高级
操作码的基础，如 ADDC、OR 和 JUMP 等。这些操作码实
际上是通过某些寄存器间的 MOVE 指令实现的，而由编译
器进行编码处理，编程人员无需要关心这些。16 位指令字
为高效运行而设计。
第15 位指示指令源的格式，指令的第 0 位至第 7位代表需要
传送的源。根据格式字段的不同数值，源可能是立即数或源
寄存器。如果这个字段代表一个寄存器，则其中的低四位包
含模块标识符，而高四位包含模块中的寄存器索引值。
第 8 位至第14 位代表传送的目的，该值始终代表一个目的寄
存器，其中低四位包含模块标识符，而高三位包含模块中的
寄存器子索引值。任何情况下，当从前面的 24 个寄存器中直
接选择一个作为目的寄存器时，需要前缀寄存器 PFX提供
附加的目的标识位。写前缀寄存器操作由编译器自动插入，
并且只需一个额外的指令执行周期。完整的指令集信息请参
考MAXQ 系列用户指南 (Englishonly)。
存储器结构
器件包括几个存储区域：
•
•
•
•
10
指令集
32K字闪存存储器，用于存储应用程序
用于存储临时变量的1K字 SRAM
4K字应用程序 ROM，包含调试器和程序加载器
用于存储程序返回地址和常规数据的16 级堆栈存储器
系统管理微控制器
8h
AP
9h
A
Bh
PFX
Ch
IP
Dh
SP
Eh
DPC
PROGRAM
MEMORY SPACE
00h
DATA MEMORY
(WORD MODE)
FFFFh
FFFFh
FFFFh
8FFFh
9FFFh
8FFFh
4K x 16
UTILITY ROM
DP
Fh
DATA MEMORY
(BYTE MODE)
0Fh
8000h
7FFFh
8K x 8
UTILITY ROM
8000h
MAX31782
SYSTEM
REGISTERS
4K x 16
UTILITY ROM
8000h
PERIPHERAL
REGISTERS
0h
M0
1h
M1
2h
M2
3h
M3
4h
M4
32K x 16
USER PROGRAM
MEMORY
M5
5h
00h
0Fh
00h
1Fh
16 x 16
STACK
07FFh
001Fh
0010h
0000h
PASSWORD
0000h
2K x 8
SRAM DATA
03FFh
0000h
1K x 16
SRAM DATA
图3. 存储器映射
该存储器采用哈佛架构，程序和数据存储器具有独立的地
址 空间。另外， 还 采用伪冯•诺 依 曼 架构 存储 器映 射， 将
ROM、应用程序和数据存储器放置到连续的存储区。通过
伪冯•诺依曼存储器映射，数据存储器可以映射至程序空间，
允许执行来自数据存储器的代码。另外，程序存储器也可以
映射至数据空间，允许将代码常数作为数据存储器进行访
问。图 3 给出了从程序存储空间执行操作时的存储器映射。
请参考MAXQ 系列用户指南：MAX31782 补充资料 (English
only)，了解从数据或 ROM 空间执行操作时的存储器映射
信息。
利用闪存存储器可以在现场升级固件，闪存可以通过16 字
密钥进行加密保护，从而防止未经授权的程序存储器访问。
固定用途ROM
固定用途 ROM 是一个 4K字的内部 ROM 存储器块，默认起
始地址为 8000h。固定用途 ROM 由可以在应用软件中进行
调用的子程序组成，其中包括：
• 通过JTAG或I2C兼容接口进行在系统编程(引导加载程序)
• 在电路调试程序
• 在应用闪存编程的调用程序
任何复位操作后，都从固定用途 ROM 开始运行程序。ROM
软件决定程序是否立刻跳转到 0000h 地址、用户应用程序
的起始地址或者是上述某个特定程序。用户可通过固件访问
固定用途 ROM 中的程序，并可通过应用程序调用这些子程
序。有关固定用途 ROM 内容的详细信息，请参考MAXQ 系
列用户指南：MAX31782 补充资料 (Englishonly)。
11
MAX31782
系统管理微控制器
密码
器件在出厂之前，会设置一个默认密码，该密码定义为物
理地址 0010h 至 001Fh 程序存储器的16 个字，在 SC 寄存器
采用了单个密码锁存位 (PWL)。一旦对新器件进行编程，即
定义了密码 (密码不能全为 0 或1)且 PWL置位。如果 PWL为
0，则器件视为尚未编程。擦除后密码被自动设为全1。
堆栈存储器
16 位、16 级内部堆栈为程序返回地址和常规数据提供存储。
当执行 CALL、RET 和 RETI指令以及进行中断服务时，处
理器自动使用堆栈。也可以通过使用 PUSH、POP 和 POPI
指令直接使用堆栈，进行数据存储和恢复。
复位 后， 堆 栈 指 针 SP 初 始 化 至 栈 顶(0Fh)。执 行 CALL、
PUSH 和中断向量操作时递增 SP，然后在 SP 指向的地址存
储一个数值。执行 RET、RETI、POP以及POPI操作时取回
SP 指向的数值并递减 SP。
编程
可以通过三种不同方法对微控制器闪存编程：在系统编程、
在应用编程和生产编程。这三种方法都为系统设计提供了极
大灵活性，并降低了嵌入式系统在有效使用期限内的成本。
在系统编程
内部引导加载程序允许器件通过 JTAG 或I2 C 兼容接口进行
编程。因此，可以在系统升级系统程序，节省了软件升级所
需的昂贵的硬件更改花费。
ICDF 寄存器的编程源选择 (PSS) 位决定使用哪个接口进行
引导装载操作，器件支持 JTAG 和I2 C作为装载接口，分别
对应于 PSS 的 00 和 01。
在应用编程
在应用编程允许微控制器更改自身的闪存程序存储器，以
便在线升级软件，满足一些重要操作中的不停机要求。同时，
它还允许开发在应用软件控制下的定制加载软件。固定用途
12
ROM 包含固件可访问的闪存编程函数，可以擦除闪存并对
闪存编程。关于这些函数的详细说明请参考MAXQ 系列用
户指南：MAX31782 补充资料 (Englishonly)。
系统定时
器 件 在 内 部 利 用 一 个 环 形 振 荡 器 产 生 4MHz 指 令 时 钟
(MOSC)。上电时，在 VDD 升至 VBO 之前，振荡器输出(不可
由外部访问) 被禁用。一旦电压达到该门限，计数1000 个周
期 (约 250 μs)后使能输出，为器件提供时钟。
系统复位
可通过多个复位源对器件进行复位。
上电复位
内部上电复位 (POR)电路提高了系统的可靠性，一旦VDD 电
压上升至 VPOR 以上，电路强制器件执行上电复位功能，此
时将发生以下操作：
• 所有寄存器和电路进入复位状态
•
•
POR 标志(WDCN.7)置位，指明复位源
解除复位后，从8000h重新开始执行程序
低电压检测 / 复位
器件具有低电压检测 / 复位功能。当电源监测器检测到低电
压状态 (VDD<VBO) 时，会立即产生一次复位，并在 VDD
低于VBO 时始终保持该状态。一旦VDD 电压上升到 VBO 以
上，器件将等待 tSU:MOSC，然后恢复到正常工作状态，也
称为 CPU 状态。如果在 tSU:MOSC 期间再次发生低电压情况，
则再次返回低电压状态。否则，则进入CPU 状态。CPU 状
态下，低电压检测器保持使能。上电时，器件总是首先进入
低电压状态，然后执行上面列出的过程。低电压引起的复位
操作与 POR 相同，低电压复位需要经历 POR 的所有动作。
POR 过程中将清除所有寄存器，低电压复位同样也将清除所
有寄存器。
系统管理微控制器
POWER
LDO
MODE
(2.5V)
On/Off
CPU Mode
On
On/Off
CPU Mode
On
On
Off
Stop Mode
On
Off
On
Off
Stop Mode
On
On
On
Off
Stop Mode
On
LDO
INTERNAL
BROWNOUT
SVM
LDO (1.8V)
(1.8V)
OSCILLATOR
DETECT
MONITOR
MONITOR
On
On
On
On
Off
On
On
On
On
On
On
On
X
Off
On
On
On
Off
1
0
Off
On
On
On
1
1
Off
On
On
On
CKCN.
SVM.
SVM.
STOP
SVMEN
SVMSTOP
0
0
X
0
1
X
1
0
1
1
CPU
看门狗定时器复位
看门狗定时器提供了一个在程序运行失效时复位处理器的机
制。看门狗定时器是一个可通过应用软件周期性复位的硬件
定时器。如果程序正常运行，定时器将在达到最大计数值之
前被复位。但是，如果程序运行过程发生失效，不能复位看
门狗定时器，定时器将达到其最大计数值并复位处理器。
看门 狗 定 时 器 通 过 WDCN 寄 存 器 中的 2 位 (WDCN[5:4]:
WD[1:0]) 控制。超时周期可以设置为 212 至 221 个系统时钟
(MOSC)周期 (1.024ms 至 0.524s)内的 4 个可编程间隔之一。
在超时周期 (512 个 MOSC 时钟周期或128 μs) 结束、发生复
位之前，看门狗产生中断。由看门狗定时器产生的复位持续
4 个系统时钟周期，即1μs。软件可通过检查 WDCN 寄存器
的看门狗定时器复位标识(WTRF)，确定复位是否由看门狗
超时产生。发生看门狗定时器复位后，从8000h 重新开始执
行程序。
外部复位
拉低 RST 引脚将使器件进入复位状态，MAXQ 系列用户指
南 (Englishonly) 介绍了外部复位功能。释放 RST 引脚后，从
8000h重新开始执行程序。
内部系统复位
I2 C 程序装载模式下，主控制器可通过I2 C从机地址 34h 发
出一条 BBh 命令，复位与之通信的器件。这种复位与外部复
ADC
供电模式
器件支持两种工作模式 ：CPU 模式和停止模式。器件在执行
CPUSTOP(CKCN.STOP) 命令后进入停止模式。进入停止
模式时，由于数字核电路的时钟被关闭，因此处于无效状
态。除了ADC(包括 SVM、LDO及监控电路)以外，所有模
拟电路均保持有效。发生以下任何状况时，器件将退出停止
模式：端口 6发生外部中断、I2 CSTART中断、SVM 中断或
外部复位。上述中断只有使能后才能使器件退出停止模式。
退出停止模式时，系统在10 个系统时钟周期内返回 CPU 模
式。若某个中断引起系统退出停止模式，程序则从进入停止
模式时的位置开始执行。但是，如果是某个外部中断引起系
统退出停止模式，程序则从ORG( 启动点 ) 开始执行。表1介
绍了不同模式下的模拟 / 数字电路状态。
寄存器组
器件的大多数功能由寄存器组控制，这些寄存器为存储器
操作提供工作空间，并配置、寻址器件的外设寄存器。寄存
器分成两大类 ：系统寄存器 (SPR) 和外设寄存器 (SFR)。公
共寄存器组也称作系统寄存器，包括 ALU、累加器寄存器、
数据指针、中断向量和控制、以及堆栈指针。外设寄存器定
义更多的功能，功能被划分为独立模块。关于系统寄存器
和外设寄存器的详细信息，请参考MAXQ 系列用户指南 ：
MAX31782 补充资料 (Englishonly)。
位具有相同效果，对所有寄存器复位值具有相同影响。此外，
完成在系统编程时 (ROD=1)，也会发生内部系统复位。
13
MAX31782
表1. 供电模式
MAX31782
系统管理微控制器
硬件乘法器
硬件乘法器 (乘法累加器或 MAC 模块 ) 是一种功能非常强大
的工具，尤其对于需要大量计算的应用。该乘法器可在单个
机器周期内(有些情况下运行速度更快 )对有符号或无符号操
作数执行乘、乘反、乘加、乘减运算。MAC 模块使用了8 个
SFR，映射为模块 M5中的寄存器 0h 至 07h。
系统中断
器件提供多个中断源以响应内部和外部事件。MAXQ20 结
构采用单一中断向量 (IV)、单一中断服务程序(ISR) 设计。为
提高灵活性，中断可以按照全局、独立或模块级使能。发生
中断条件时，即使中断源以本地、模块或全局形式被禁止，
其自身对应的标志位都将置位。必须在固件中断程序内清除
中断标志，以避免同一中断源重复产生中断。应用程序必须
确保在写中断标志和 RETI指令间有一个延时，使中断硬件
有时间清除内部中断条件。异步中断标志要求单指令延时，
而同步中断标志需要双指令延时。检测到使能中断时，软件
跳转到一个用户可编程中断向量的位置。IV 寄存器在复位或
上电后的缺省值为 0000h，如果没有改成其它地址，应用
固件必须判断向 0000h 跳转是由复位引起的，还是由中断
源引起的。
一旦软件控制权转移到ISR，可以使用中断识别寄存器 (IIR)
判定中断源为系统寄存器，还是外设寄存器。除IIR 外，还
通过 MIIR 寄存器指示外设模块中的哪个功能引起了中断。器
件含有 6 个外设模块，M0 至 M5，每个模块下都配有 MIIR
寄存器。MIIR 寄存器为16 位只读寄存器，系统复位时的默
认值为全 0。一旦产生中断的模块输出信号，即可查询具体
的中断源，软件即可采取相应措施。由于中断通过应用软件
鉴别，可以为每种应用确立一个独特的中断优先级方案。中
断源可来自于看门狗定时器、ADC、TACH.n 引脚、可编程
定时器 /计数器、I2 C 兼容主机和从机接口、SVM 及端口 6 的
I/O引脚。
14
可编程定时器/ 计数器
器件具有一个通用的可编程定时器 /计数器，通常称为定时
器 B 模块。该定时器 /计数器的技术指标等同于定时器 B 模
块。与该定时器 /计数器相关的有4 个寄存器：TB0CN(控
制 寄 存 器)、TB0V( 数 值 寄 存 器)、TB0C(比 较 寄 存 器)
和 TB0R(捕获 / 重载数值寄存器)。该定时器 /计数器有两
个引脚 ：TBA 和 TBB， 分别与 P6.4 和 P6.2 引脚 复用。使
能 TBA 或TBB 时， 对 应 的 引 脚 功 能 为 定 时 器 /计 数 器 引
脚，而非 GPIO，详细信息请参考I/O 端口 部分。有关定时
器 /计数器模块的详细信息，请参考MAXQ 系列用户指南 ：
MAX31782 补充资料 (Englishonly)。
I/O 端口
器件有一个简单的输入 / 输出(I/O) 数据端口：端口 6。引脚
P6.0至 P6.4主要用作 GPIO引脚以及复用功能。每个引脚至
少与一项特殊功能复用，例如 ：中断、定时器 /计数器I/O 引
脚或 JTAG 引脚。表 2 汇总了I/O 引脚的功能，图 4 所示为I/O
端口方框图。
端口 6 的引脚带有施密特触发接收器和 CMOS 输出驱动器，
并可支持复用功能。该端口可通过模块1的 6 个SFR(PO6、
PI6、PD6、EIE6、EIF6 和 EIES6) 操作，每个引脚可单独配
置。当定义为输入时，引脚为高阻态或弱上拉，具体取决于
输出寄存器中相应的位状态。此外，当编程为输入端时，每
个引脚均可作为外部中断，具有独立的使能、标识和有效沿
选择。
上电时，P6.0至 P6.3引脚默认为 JTAG。将 SC.TAP 清 0( 上
电状态为1)，即可将其配置为 GPIO。将 EIE6.n(n=0至4、
6、7)置1，即可将 P6.n 配置为中断。
引脚 P6.2 和 P6.4 有 特 殊 功 能， 分 别 是 定 时 器 /计 数器 的
TBB 和 TBA引脚。当TBB 或TBA，或两者均使能时，P6.2
或 P6.4，或两者均被用作相应的特殊功能。P6.2 和 P6.4 作
为定时器 /计数器引脚时彼此相互独立，即其中一个作为定
时器 /计数器引脚时，如果没有使能另外一个的特殊功能，
则仍可作为 GPIO。
系统管理微控制器
PORT INDEX
PRIMARY
FUNCTION
ALTERNATE
FUNCTION
INTERRUPTS
TAP (JTAG)
RESET STATE
P6.0
GPIO, P6.0
—
INT0
TCK
TCK
P6.1
GPIO, P6.1
—
INT1
TDI
TDI
P6.2
GPIO, P6.2
Timer B TBB Pin
INT2
TMS
TMS
P6.3
GPIO, P6.3
—
INT3
TDO
TDO
P6.4
GPIO, P6.4
Timer B TBA Pin
INT4
—
GPIO input with
weak pullup
MAX31782
表 2. I/O端口引脚
VDD
I/O PAD
WEAK
MUX
PD6.n
SF DIRECTION
MAX31782
VDD
SF ENABLE
MUX
PO6.n
SF OUTPUT
P6.n
PI6.n OR SF INPUT
FLAG
INTERRUPT
FLAG
DETECT
CIRCUIT
EIE6.n
EIES6.n
n = 0−4
图4. 端口6 的I/O 方框图
PWM 输出
器件提供 6 路独立的 PWM 输出。每路 PWM 输出与 4 个SFR
相关联 ：PWMCNn、PWMVn、PWMRn 和 PWMCn，其
中 n=0 至 5，为通道号。PWM 时钟来自于系统时钟，采用
PWMCNn 定义的分频比进行分频。PWMCNn 寄存器还使
能 / 禁用 PWM 输出、选择 PWM 优先级。用户可通过配置相
应的 PWMRn 和 PWMCn 寄存器，分别设定每路 PWM 输出
的频率和占空比。
PWM.n引脚 的 PWM 输出 功 能 被 禁 用 时， 该引脚 可作为
GPIO。作为 GPIO引脚时，可通过 3 个SFR 将 PWM.n引脚作
为端口1进行操作：PO1、PI1和 PD1。每个 PWM.n 引脚可独
立配置，定义为弱上拉输入、不带上拉的输入或输出。
15
MAX31782
系统管理微控制器
转速计输入
器件提供 6 个引脚用于读取风扇转速计脉冲。每个TACH.n
引脚功能独立，与 3 个SFR 相关联：TACHCNn(控制寄存
器)、TACHVn( 定时器数值寄存器) 和 TACHRn( 定时器捕
获寄存器)，其中 n=0至 5，为通道号。
每个TACH.n 引脚有一个内部定时器。TACH.n 定时器的时
钟来自系统时钟，按照 TACHCNn 定义的分频比进行分频。
TACH.n 定时器在最初使能时从TACHVn 值开始递增计数，
并在溢出后继续从0000h 开始计数，直到 FFFFh 溢出，即
如果保持使能和运行状态，则从 FFFFh 返回至 0000h 重新
开始。如果通过配置TACHCNn 寄存器使能了捕获功能，预
标定转速计脉冲从1跳变到 0 时，将使 TACHVn 寄存器的数
值传递到 TACHRn 寄存器，并置位外部触发标识。捕获之
后，TACHVn 重新装载 0000h 并继续计数。用户可通过读
取 TACHRn 寄存器计算转速计脉冲周期和风扇速度。
禁 用 TACH.n 引脚 的 转 速 计 输 入 功 能 时， 该 引脚 可作为
GPIO。作为 GPIO引脚时，可通过 3 个SFR 将TACH.n引脚作
为端口2 进行操作 ：PO2、PI2 和 PD2。每个TACH.n 引脚可
独立配置，定义为弱上拉输入、不带上拉的输入或输出。
I2C兼容接口模块
器件提供了两个独立的I2 C 兼容接口 ：一个为主控制器，一
个为从机。
I 2C兼容主控制器接口
器件有一个内部I2 C 兼容主控制器接口，与各种外部I2 C 器
件通信。I2 C 兼容主控制器总线为双向总线，采用两条信号
线 ：串行数据线 (MSDA) 和串行时钟线 (MSCL)。对于I2 C 兼
容主控制器，器件主导I2 C总线，驱动时钟并产生 START 和
STOP信号。从而使器件根据需要向某个从机发送数据，或
者从从机接收数据。MSDA 和 MSCL 必须驱动为开漏输出，
需要外部上拉电阻将其拉至逻辑高电平。
禁用I2 C 兼容主控制器接口时，MSDA、MSCL可作为 GPIO
引脚。作为 GPIO 引脚时，可通过 3 个SFR 将 MSDA 和 MSCL
16
分别用作 P2.7 和 P2.6 ：PO2、PI2 和 PD2。由于这三个引脚
为开漏输出，需要外部上拉实现逻辑高电平。
I 2C兼容从机接口
器件提供一个内部I2 C 兼容从机接口，与主控制器通信。不
仅如此，器件还可通过I2 C 兼容从机接口进行在系统编程 (引
导载入 )。对于I2 C 兼容从机接口，器件依赖于外部产生的时
钟驱动 SCL，并且只有在 I2 C 主控制器请求时响应数据和
命令。
SMBus 超时
I2 C 兼容主控制器和从机接口均可工作于SMBus兼容模式，
与其它 SMBus 器件通信。为了实现这一功能，I2 C 兼容从机
接口配备了一个30ms定时器，使接口兼容于SMBus 总线。
该定时器用于在 SCL保持低电平的时间超过 30ms 时产生一
个超时中断，使固件复位 I2 C 兼容从机接口。只有以下条件
均不存在时，定时器才启动：
• I2C 兼容从机接口处于空闲状态，且总线上没有数据通信。
• I2C 兼容从机接口在 SMBus兼容模式下没有工作。
•
•
SCL 逻辑电平为高。
禁用I2C 兼容从机接口。
发生超时后，超时位被置位并产生一次中断 ( 如果使能)。如
果发生超时中断，则禁止执行固件并重新使能I2 C 兼容从机
接口。该过程之后，SCL 和 SDA引脚置为高阻，所有I2 C从
机相关的 SFR 都由固件重新加载。
模 / 数转换器(ADC)
器件含有一个带 7 路输入复用器的12 位模 / 数转换器 (ADC)
(图 5)。复用器从6 路外部通道和1路内部通道选择 ADC 输
入。6 路外部通道可工作于全差分电压模式或单端电压模式。
此外，6 路通道中的任一通道可以配置为测量外部二极管
温 度，内部通道专用于测量管芯温度。ADC 由 SFR 寄存器
控制。
系统管理微控制器
六个外部通道可分别配置为工作在外部温度模式。外部温度
模式下，电流强制进入连接在用户指定通道引脚之间的外
部二极管。通过测量二极管在各种偏置电流下的电压获得二
极管温度。器件采用 3点串联电阻抵消算法，以提高温度测
量精度。ADC 测量的外部二极管温度不受环路电阻影响。在
外部和内部温度测量模式下可自动选择内部基准，满量程
值(FS)固定为1.225V，温度测量分辨率为 0.125°C。
外部通 道配置为工作在电压模式时，作用到相应 通 道 (差
分或单端 ) 的电压将被转换为数字读数。电压模式下，可以
采用内部或外部基准。如果采用内部基准，FS 可以设置为
1.225V 或 5.5V。通过调整相关寄存器 (ADCG1和 ADCG5)，
可微调 FS。
电压模式下，完成一次ADC 转换需要 34 个ADCCLK 周期。
ADCCLK 来自系统时钟，按照 ADC 控制寄存器定义的分频
比进行分频。ADC最高采样率为 SYSCLK/544。采用 4MHz
系统时钟时，该采样率理论值为7.35ksps。如果实际应用
中需要延长采集时间，可以根据 ADC 控制寄存器确定的延
长周期进行采样。
ADC 有 8 个配置寄存器。每个通道均可独立配置，例如：差
分模 式 选 择、 数 据排列选 择、 延长 采样 使能、ADC 基准
选择和外部温 度模式选择等。ADC还具有16 个13 位循环
数据缓冲器，用于保存转换结果。ADC 数据提供中断标识
(ADDAI)，配置为按照预先确定的采样次数触发一次中断。
ADDAI置位后，可通过软件清零或在转换开始时清零。
当器件处于停止模 式时，任 何正在 进行的 ADC 转换均被
中止，ADC启 动 转 换 位 (ADCONV) 复位 为 0，ADC 完 全
关 断以节省功耗。退出停止模 式时，ADC 等 待ADCONV
=1。当ADCONV置1时，器件在开始采样之前计数 20 个
ADCCLK 周期。
ADCG1
INTERNAL
ADCG5 REFERENCE
EXTERNAL
REFERENCE
AD0P
AD0N
VOLTAGE
OFFSET
AD5P
MUX
AD5N
SCALER FOR
TEMPERATURE
SENSING CHANNELS
INTERNAL
CHANNEL
12-BIT ADC CORE
TEMPERATURE
OFFSET
ADC DATA
MAX31782
图5.ADC 方框图
17
MAX31782
ADC 可以设置为连续轮询输入通道(连续模式)或完成转换
后进入关断模式，以节省功耗 (单次模式)。
MAX31782
系统管理微控制器
在电路调试
通过JTAG 兼容测试访问端口(TAP) 实现嵌入式调试功能。
嵌入式调试硬件和嵌入式 ROM 固件为用户应用程序提供在
电路调试功能，无需昂贵的在电路仿真器。图 6 所示为在电
路调试器的框图。在电路调试器具有以下特性：
• 硬件调试引擎
• 寄 存 器 组， 能 够 在 寄 存 器、 程 序 或 数 据 操 作 (ICDA、
ICDB、ICDC、ICDD、ICDF、ICDT0 和ICDT1)中设置
断点
• 调试服务程序组保存在固定用途 ROM 中
嵌入式硬件调试引擎是微控制器的一个独立硬件模块。调试
引擎在 CPU 执行用户程序时可以监测内部操作，并与所选
择的内部寄存器进行交互。硬件和软件功能相结合，能够实
现两种基本的在电路调试模式：后台和调试。
后台模式允许主控制器配置、设置在电路调试器，而 CPU 继
续全速执行应用软件。调试模式可从后台模式激活。
调试模式允许调试引擎控制 CPU，提供对内部寄存器和存
储器的读 / 写操作以及单步执行。
电源去耦
使 用器 件时， 为了获得 最 佳 结果需要 在 V DD 端 增加一 个
0.1µF 去耦电容，尽可能采用高质量表贴陶瓷电容。表贴元
件将引线电感降至最小，有助于改善性能，另外，采用陶瓷
电容去耦能够满足高频响应的要求。
通过1µ F 和10nF电容对 REG25 和 REG18 去耦 (每个输出端
一组 )。注：请勿将这些引脚用于外部电路供电。
其它文档
设计人员在使用该器件的所有功能时必须具有四个文档。数
据资料包含引脚说明、特性概述和电气规格。勘误表列出了
与已公布指标的差异。用户指南提供了器件特性和工作过程
的详细信息。以下文档可从china.maxim-ic.com下载。
•
•
•
MAX31782 数据资料，包含电气 / 时序规格和引脚说明。
MAX31782 相关 版本的勘误表(china.maxim-ic.com/
errata)。
MAXQ 系列用户指南 (English only)，提供有关内核电路
的功能和操作的详细信息，包括编程等内容。
•
MAX31782
应用信息
MAXQ系列用户指南：MAX31782补充资料 (English only)，
提供有关 MAX31782特殊功能的详细信息。
开发和技术支持
Maxim 和第三方供应商为这款微控制器提供各种高度通用、
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
低成本的开发工具，包括：
• 编译器 (C 和汇编)
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
图 6. 在电路调试器
18
CONTROL
BREAKPOINT
ADDRESS
DATA
• 在电路调试器
• 集成开发环境 (IDE)
• 用于编程和调试的串口至JTAG 转换器
• 用于编程和调试的 USB至JTAG 转换器
如 需 技 术 支 持， 请 发 送电子 邮 件至mixedsignal.apps@
maxim-ic.com。
系统管理微控制器
VIN
IN
OUT
TO LOAD
POWER SUPPLY
TRIM
EN
MSDA
MSCL
DS75
I2C TEMP SENSOR
MAX31782
3.3V
VDD
VSS (3)
SDA
SCL
PWM.5
PWM.4
PWM.3
PWM.2
PWM.1
PWM.0
PWM
FOR D/A;
OTHER
3.3V
V4-WIRE FAN
3.3V
TO HOST µP
RST
REG18
REG25
TACH.5
TACH.4
TACH.3
TACH.2
TACH.1
TACH.0
PWM
TACH
TACH/TIMER
INPUTS OR GPIO
AD5P
AD5N
REMOTE TEMPERATURE
SENSOR
AD4P
GPIO/SPECIAL FUNCTIONS
P6.4/TBA
P6.3/TDO
P6.2/TMS/TBB
P6.1/TDI
P6.0/TCK
AD4N
AD3P
AD3N
AD2P
AD2N
AD1P
AD1N
AD0P
AD0N
ADDITIONAL ADC
CHANNELS FOR MONITORING
封装信息
如需最近的封装外形信息和焊盘布局，请查询china.maxim-ic.com/packages。请注意，封装编码中的“+”、
“#”或“-”仅表示 RoHS 状态。
封装图中可能包含不同的尾缀字符，但封装图只与封装有关，与 RoHS 状态无关。
封装类型
封装编码
外形编号
焊盘布局编号
40 TQFN-EP
T4066+2
21-0141
90-0053
19
MAX31782
典型工作电路
MAX31782
系统管理微控制器
修订历史
修订号
修订日期
0
6/10
说明
最初版本。
修改页
—
Maxim北京办事处
北京8328信箱 邮政编码 100083
免费电话：800 810 0310
电话：010-6211 5199
传真：010-6211 5299
Maxim 不对 Maxim 产品以外的任何电路使用负责，也不提供其专利许可。Maxim 保留在任何时间、没有任何通报的前提下修改产品资料和规格的权利。
20 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2010MaximIntegratedProducts
Maxim 是 MaximIntegratedProducts,Inc.的注册商标。
19-5327; Rev 2; 1/12
System Management Microcontroller
The MAX31782 provides a complete solution for the
monitoring and controlling of complex system physical
health characteristics based on a high-performance,
MAXQ20, 16-bit microcontroller core with generous
amounts of flash program/data and RAM data memory.
I/O resources include an accurate measurement system for temperature and voltage, PWM outputs, timer
inputs, and GPIO to support monitoring and controlling
critical system parameters such as temperature, voltage, fan speed, and chassis intrusion. Direct connection
of diode-connected transistors used as remote temperature sensors is supported as well as expansion to a
virtually unlimited number of external digital temperature
sensor ICs using the on-chip master I2C interface. An
independent slave I2C interface facilitates communication to a host microprocessor in addition to passwordprotected in-system reprogramming of the on-chip flash.
Ease of development is supported with highly versatile
C-compilers and development software that programs
flash and performs in-circuit debug through the integrated JTAG interface and associated hardware.
All these features combined make the device a highly
flexible platform, allowing the designer to easily create a
customized complex system management solution.
Applications
Features
SMAXQ20, High-Performance, 16-Bit µC
SEfficient C-Language Programming
S36KWords Total Program Memory
32KWords Flash Program Memory
4KWords ROM Program Memory
S1KWords Data RAM
S12-Bit ADC with 7-Input Mux for Temperature and
Voltage Monitoring
STemperature Measurement Analog Front-End
0.125NC Resolution
Diode Series Resistance Cancellation
SSix Timer/Fan Tachometer Inputs
SSix 16-Bit PWM Outputs for Fan Speed or D/A
Applications
S5-Bit GPIO Ports
SSMBus/I2C-Compatible Slave Interface for Host
Communication with Password-Protected Flash
Programming
SI2C-Compatible Master Interface for Slave
Expansion
SPower-On Reset and Brownout Monitors
SJTAG Port Supports In-System Debug and Flash
Programming
Network Switches/Routers
SInternal Oscillator Requires No Crystal
Base Stations
S2.7V to 5.5V Operating Voltage Range
Servers
Smart Grid Network Systems
Typical Operating Circuit appears at end of data sheet.
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX31782ETL+
PART
-40NC to +85NC
40 TQFN-EP*
MAX31782ETL+T
-40NC to +85NC
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX31782
General Description
MAX31782
System Management Microcontroller
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 35.7mW/NC above +70NC)...............2857.1mW
VDD to VSS............................................................-0.5V to +5.5V
ADxN to VSS..........................................................-0.3V to +0.3V
All Other Pins to VSS except
REG18 and REG25............................... -0.5V to (VDD + 0.5V)*
SCL, SDA, MSDA, MSCL, P6.0–P6.4
Continuous Sink Current..................... 20mA each, 50mA total
P6.0–P6.4 Continuous Source Current....20mA each, 50mA total
*Subject to not exceeding +5.5V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40NC to +85NC, unless otherwise noted.)
PARAMETER
VDD Operating Voltage Range
SYMBOL
VDD
CONDITIONS
(Note 1)
MIN
TYP
MAX
UNITS
2.7
5.5
V
VDD +
0.3
V
V
Input Logic 1
VIH
0.7 x
VDD
Input Logic 0
VIL
0
0.3 x
VDD
2.1
VDD +
0.3
0.7 x
VDD
VDD +
0.3
2.7V P VDD P 3.6V (Note 1)
0
0.8
3.6V P VDD P 5.5V
0
0.3 x
VDD
2.7V P VDD P 3.6V (Note 1)
Input Logic-High: SCL, SDA,
MSDA, MSCL
VI2C_IH
Input Logic-Low: SCL, SDA,
MSDA, MSCL
VI2C_IL
3.6V P VDD P 5.5V
V
V
DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
Supply Current
SYMBOL
TYP
MAX
UNITS
ICPU
Assuming 100% CPU duty cycle (Note 2)
CONDITIONS
MIN
1.73
2.34
mA
ISTOP
(Note 2)
830
1250
7
IPROGRAM
VBO
Monitors VDD (Note 1)
Brownout Hysteresis
VBOH
Monitors VDD (Note 1)
Internal System Clock
fMOSC
Brownout Voltage
fERR:MOSC +25NC P TA P +85NC
-40NC P TA P +25NC
2
2.46
2.55
30
-1
V
mV
4.0
Initial tolerance, TA = +25NC, VDD = 5.5V
System Clock Error (Note 3)
2.40
µA
mA
MHz
+1
-2
+1
-5.5
+0.6
%
System Management Microcontroller
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
System Clock Startup
SYMBOL
tSU:MOSC
CONDITIONS
From POR, MOSC inactive
Output Logic-Low
VOL
IOL = 4mA (Note 1)
Output Logic-High (all pins
except SDA, SLL, MSDA, MSCL)
VOH
IOH = -2mA (Note 1)
IPU
VPIN = VSS, VDD = 3.3V
GPIO Mode Pullup Current
MIN
ADC Voltage Conversion Time
tCONV_V
(Note 4)
ADC Temperature Conversion
Time
tCONV_T
(Note 4)
0.4
VDD 0.5
38
ADC Internal Reference Initial
Accuracy (+25NC)
ADC External Reference Buffer
Accuracy
IADC
VFS
ADC Measurement Resolution
VLSB
AD0P–AD5P Input Resistance
ADC Integral Nonlinearity
ADC Offset
Internal Temperature
Measurement Error
Remote Temperature
Measurement Error
(MAX31782 Error Only)
V
55
107
FA
150
µs
7
ms
-1
+1
%
-0.5
+0.5
%
-1
+1
mV
%
2.2
ADGAIN = 0, factory set, internal reference
1.213
1.225
1.237
ADGAIN = 1, factory set, internal reference
5.445
5.5
5.555
ADGAIN = 0
300
ADGAIN = 1
1343
RIN
INL
V
Q0.25
This current is in addition to ICPU
ADC Bit Resolution
mA
V
FV
12
Bits
15
MI
(Note 7)
Q8
VOFFSET
LSB
LSB
Q2
-3
+3
TA = 0NC to +60NC,
TDIODE = +60NC to +120NC
-1.5
+1.5
TA = 0NC to +60NC,
TDIODE = -45NC to +120NC
-1.75
+1.75
TA = -40NC to +85NC,
TDIODE = +60 to +120NC
-2.75
+2.75
TA = -40NC to +85NC,
TDIODE = -45NC to +120NC
-3.0
+3.0
TA = -40NC to +85NC
V
137
(Note 5)
ADC Full-Scale Input Voltage
(Note 6)
UNITS
MOSC
Cycles
1.225
VERR
ADC Internal Reference
Temperature Drift
ADC Operating Current
MAX
1000
ADC Internal Reference
ADC Voltage Measurement Error
TYP
NC
NC
3
MAX31782
DC ELECTRICAL CHARACTERISTICS (continued)
MAX31782
System Management Microcontroller
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25NC, unless otherwise
noted.)
PARAMETER
Flash Erase Time
Flash Programming Time per
Word
Flash Endurance
SYMBOL
CONDITIONS
MIN
TYP
MAX
tME
Mass erase
20
40
tPE
Page erase
20
40
20
40
tPROG
NFLASH
Data Retention
UNITS
ms
Fs
TA = +50NC
20,000
Write
Cycles
TA = +50NC
100
Years
ELECTRICAL CHARACTERISTICS: I2C-COMPATIBLE INTERFACE
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 1)
PARAMETER
SYMBOL
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and START Condition
tBUF
Hold Time (Repeated)
START Condition
tHD:STA
CONDITIONS
Timeout not enabled (Note 8)
(Note 9)
MIN
TYP
10
MAX
UNITS
400
kHz
1.3
Fs
0.6
Fs
Low Period of SCL Clock
tLOW
1.3
Fs
High Period of SCL Clock
tHIGH
0.6
Fs
Setup Time for a (Repeated)
START Condition
tSU:STA
0.6
Fs
Data Hold Time (Note 10)
tHD:DAT
Data Setup Time
Receive
0
Transmit
300
ns
tSU:DAT
100
Rise Time of Both SDA and
SCL Signals
tR
(Note 11)
20 +
0.1CB
300
ns
Fall Time of Both SDA and
SCL Signals
tF
(Note 11)
20 +
0.1CB
300
ns
Setup Time for STOP
Condition
tSU:STO
Spike Pulse Width That Can Be
Suppressed by Input Filter
tSP
SCL, SDA Capacitive Loading
CB
SMBus Timeout
4
ns
0.6
(Note 12)
Fs
0
25
50
30
ns
400
pF
35
ms
System Management Microcontroller
MAX31782
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(VDD = 2.7V to 5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 2)
PARAMETER
SYMBOL
JTAG Logic Reference
CONDITIONS
MIN
TYP
MAX
VDD/2
VREF
UNITS
V
TCK High Time
tTH
1
Fs
TCK Low Time
tTL
1
Fs
TCK Low to TDO Output
tTLQ
0.125
Fs
TMS, TDI Input Setup to TCK
High
tDVTH
0.30
Fs
TMS, TDI Input Hold after TCK
High
tTHDX
0.25
Fs
Note 1: A
ll voltages are referenced to ground (VSS). Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2: This value does not include current in SDA, SCL, and P6.0–P6.4.
Note 3: Guaranteed by design.
Note 4: ADCCLK = SYSCLK/16. This is following an initial startup time of approximately 80µs.
Note 5: Base line accuracy of reference source + 0.25% introduced by the MAX31782.
Note 6: The voltage applied to the pins must not exceed their corresponding absolute maximum voltages.
Note 7: ADC has no missing codes.
Note 8: Minimum SCL frequency applies only when in I2C master mode.
Note 9: After this period, the first clock pulse can be generated.
Note 10: T
his device internally provides a hold time of at least 25ns for the SDA signal (referenced to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 11: CB—Total capacitance of one bus line in pF.
Note 12: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
SDA
tBUF
tF
tLOW
tHD:STA
tSP
SCL
tHD:STA
tHIGH
tR
tHD:DAT
STOP
START
tSU:STA
tSU:STO
tSU:DAT
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
Figure 1. I2C-Compatible Bus Timing Diagram
5
MAX31782
System Management Microcontroller
tTL
TCK
VREF
tTH
TMS/TDI
tDVTH
tTHDX
TDO
tTLQ
Figure 2. JTAG Timing Diagram
Typical Operating Characteristics
(VDD = 3.3V, TA = +25°C, unless otherwise noted.)
ADC DNL
MAX31782 toc01
1.5
ADC DNL (LSB)
1.0
0.5
0
-0.5
NO MISSING CODES OBSERVED
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
ADC CODE
6
System Management Microcontroller
VSS
26 25
TACH.3
PWM.2
TACH.2
PWM.1
TACH.1
28 27
REG18
30 29
PWM.0
REG25
TACH.0
TOP VIEW
24 23 22
21
SDA 31
20 PWM.3
SCL 32
19 TACH.4
P6.4/TBA 33
18 PWM.4
P6.3/TDO 34
17 TACH.5
16 PWM.5
P6.2/TMS/TBB 35
MAX31782
VSS 36
15 MSCL
14 MSDA
P6.1/TDI 37
P6.0/TCK 38
13 RST
EP
+
AD5N 39
12 AD2N
11 AD2P
VSS
AD4P
AD3N
AD3P
6
7
8
9
10
AD1N
5
VDD
4
AD1P
3
AD0P
2
AD0N
1
AD4N
AD5P 40
TQFN
(6mm × 6mm × 0.75mm)
Pin Description
PIN
NAME
1
AD4N
FUNCTION
Ground Reference for ADC.4 Voltage Measurement
Supply Return Node
2, 21, 36
VSS
3
AD4P
ADC Voltage-Sense Input, Measurement Relative to AD4N
4
AD3N
Ground Reference for ADC.3 Voltage Measurement. Connected to external reference pin when
enabled.
5
AD3P
ADC Voltage-Sense Input, Measurement Relative to AD3N
6
AD0P
ADC Voltage-Sense Input, Measurement Relative to AD0N
7
AD0N
Ground Reference for ADC.0 Voltage Measurement
8
AD1P
ADC Voltage-Sense Input, Measurement Relative to AD1N
9
VDD
10
AD1N
Input Supply. +2.7V to +5.5V input range. Bypass VDD to VSS with a 0.1FF capacitor.
Ground Reference for ADC.1 Voltage Measurement
11
AD2P
ADC Voltage-Sense Input, Measurement Relative to AD2N
12
AD2N
Ground Reference for ADC.2 Voltage Measurement
13
RST
MSDA
Active-Low Reset. A low-level voltage at this pin resets the IC.
14
15
MSCL
Master I2C-Compatible Clock. When disabled, this pin can be used as GPIO P2.6.
16
PWM.5
PWM Output No. 5. When disabled, this pin can be used as GPIO.
17
TACH.5
Tachometer Input No. 5. When disabled, this pin can be used as GPIO.
Master I2C-Compatible Bidirectional Data Line. When disabled, this pin can be used as GPIO P2.7.
18
PWM.4
PWM Output No. 4. When disabled, this pin can be used as GPIO.
19
TACH.4
Tachometer Input No. 4. When disabled, this pin can be used as GPIO.
7
MAX31782
Pin Configuration
MAX31782
System Management Microcontroller
Pin Description (continued)
8
PIN
NAME
FUNCTION
20
PWM.3
PWM Output No. 3. When disabled, this pin can be used as GPIO.
22
REG18
Bypass REG18 to VSS with 1FF and high-frequency 10nF capacitors. Do not use for external
circuitry.
23
TACH.3
Tachometer Input No. 3. When disabled, this pin can be used as GPIO.
24
PWM.2
PWM Output No. 2. When disabled, this pin can be used as GPIO.
25
TACH.2
Tachometer Input No. 2. When disabled, this pin can be used as GPIO.
26
PWM.1
PWM Output No. 1. When disabled, this pin can be used as GPIO.
27
TACH.1
Tachometer Input No. 1. When disabled, this pin can be used as GPIO.
28
PWM.0
PWM Output No. 0. When disabled, this pin can be used as GPIO.
29
REG25
Bypass REG25 to VSS with 1FF and high-frequency 10nF capacitors. Do not use for external
circuitry.
30
TACH.0
Tachometer Input No. 0. When disabled, this pin can be used as GPIO.
31
SDA
Slave I2C-Compatible Bidirectional Data Line. When disabled, this pin can be used as GPIO.
32
SCL
Slave I2C-Compatible Clock. When disabled, this pin can be used as GPIO.
33
P6.4/TBA
Programmable I/O Pin. Alternate function: Timer/Counter TBA
34
P6.3/TDO
Programmable I/O Pin. Alternate function: JTAG TDO
35
P6.2/TMS/TBB
37
P6.1/TDI
38
P6.0/TCK
Programmable I/O Pin. Alternate function: JTAG TCK
39
AD5N
Ground Reference for ADC.5 Voltage Measurement
40
AD5P
ADC Voltage-Sense Input, Measurement Relative to AD5N
—
EP
Programmable I/O Pin. Alternate functions: Timer/Counter TBB, JTAG TMS
Programmable I/O Pin. Alternate function: JTAG TDI
Exposed Pad. Not electrically connected to IC. Connect to VSS.
System Management Microcontroller
PROGRAM
MEMORY SPACE
FFFFh
8FFFh
4K x 16 UTILITY ROM
8000h
7FFFh
32K x 16 USER
PROGRAM MEMORY
0000h
MAX31782
CLOCK CONTROL,
WATCHDOG TIMER, AND
POWER MONITOR
RST
CKCN
P6.n
n = 0−4
IC
03FFh
0000h
ADDRESS
GENERATION
IC
IP
IMR
LOOP COUNTERS
IIR
DATA POINTERS
DP[0], DP[1],
FP = (BP+OFFS)
LC[n]
DPC
BOOLEAN
VARIABLE
MANIPULATION
ACCUMULATORS
(16)
I2C
SLAVE
MAXQ20 CORE
SYSTEM MODULES/
REGISTERS
INSTRUCTION
DECODE
(src, dst TRANSPORT
DETERMINATION)
AP
APC
PSF
CURRENT
SOURCES
ADCH
6-CHANNEL PULSE-WIDTH
MODULATOR
6-CHANNEL TACHOMETER
TACH.5
12-BIT
ADC
PWM.5
CPU CLOCK
MULTIPLY
ACCUMULATE
UNIT
(MAC)
VDD
TACH.1
TACH.2
TACH.3
TACH.4
PWM.0
PWM.1
PWM.2
PWM.3
PWM.4
AD0P
AD1P
AD2P
AD3P
AD4P
MUX
AD5P
INTERNAL TEMP
SCL
SDA
1K x 16 SRAM
MEMORY MANAGEMENT
UNIT (MMU)
INTERRUPT
LOGIC
GPIO
4K x 16 UTILITY ROM
SP
WDCN
I2C
MASTER
8000h
TACH.0
MSDA
MSCL
STACK MEMORY
16 x 16
FFFFh
8FFFh
DATA
MEMORY SPACE
9
MAX31782
Block Diagram
MAX31782
System Management Microcontroller
Detailed Description
The MAX31782 incorporates the 16-bit MAXQ20 microcontroller core with 16 accumulators and 16-level hardware stack. Three memory blocks provide flash application code space, utility ROM code space, and RAM memory. Specialized peripherals are integrated to perform
PWM control of fan speed, read fan tachometers, and
perform temperature monitoring using diode-connected
transistors. The device also features two I2C-compatible
communication peripherals. The slave I2C-compatible
peripheral is included to allow communication between
a host system and the device. An I2C-compatible master
interface is also included to allow communication with
remote I2C digital temperature sensors or other I2C
devices. General-purpose I/O pins (GPIOs) are also
provided to allow interrupt functions and control of other
circuitry using the system management microprocessor.
The MAXQ20 core, along with the specialized peripherals, provides a flexible solution for system and thermal
management. Flexibility is further enhanced as the solution allows for upgrading the program and data flash
contents over the I2C-compatible interface. Updates to
the program flash are protected against unauthorized
writes by a 256-bit user password.
The following sections are an introduction to the primary features of the MAX31782 system management
microcontroller. More detailed descriptions of the device
features can be found in the MAX31782 User’s Guide.
MAXQ20 Core Architecture
The device employs a MAXQ20 low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller
with flash memory. It is structured on a highly advanced,
16-accumulator-based, 16-bit RISC architecture. Fetch
and execution operations are completed in one cycle
without pipelining, since the instruction contains both
the op code and data. The highly efficient core is supported by 16 accumulators and a 16-level hardware
stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with
three internal data pointers. Multiple data pointers allow
more than one function to access data memory without
having to save and restore data pointers each time. The
data pointers can automatically increment or decrement
following an operation, eliminating the need for software
intervention.
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules. The family architecture is modular, so that new
devices and modules can reuse code developed for
existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for higher level op codes defined by the assembly,
such as ADDC, OR, JUMP, etc. The op codes are implemented as MOVE instructions between certain register
locations, while the assembler handles the encoding,
which need not be a concern to the programmer. The
16-bit instruction word is designed for efficient execution.
Bit 15 indicates the format for the source field of the
instruction. Bits 0–7 of the instruction represent the
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or
a source register. If this field represents a register, the
lower 4 bits contain the module specifier and the upper
4 bits contain the register index in that module.
Bits 8–14 represent the destination for the transfer. This
value always represents a destination register, with the
lower 4 bits containing the module specifier and the
upper 3 bits containing the register subindex within that
module. Any time it is necessary to directly select one of
the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the extra destination bits.
This prefix register write is inserted automatically by the
assembler and requires only one additional execution
cycle. Refer to the MAX31782 User’s Guide for complete
instruction set information.
Memory Organization
The device incorporates several memory areas, including:
• 32KWords of flash memory for application program
storage
• 1KWords of SRAM for storage of temporary variables
• 4KWords of utility ROM contain a debugger and program loader
• 16-level stack memory for storage of program return
addresses and general-purpose use
10
System Management Microcontroller
8h
AP
9h
A
Bh
PFX
Ch
IP
Dh
SP
Eh
DPC
PROGRAM
MEMORY SPACE
00h
DATA MEMORY
(WORD MODE)
FFFFh
FFFFh
FFFFh
8FFFh
9FFFh
8FFFh
4K x 16
UTILITY ROM
DP
Fh
DATA MEMORY
(BYTE MODE)
0Fh
8000h
7FFFh
8K x 8
UTILITY ROM
8000h
MAX31782
SYSTEM
REGISTERS
4K x 16
UTILITY ROM
8000h
PERIPHERAL
REGISTERS
0h
M0
1h
M1
2h
M2
3h
M3
4h
M4
M5
5h
00h
0Fh
00h
32K x 16
USER PROGRAM
MEMORY
1Fh
16 x 16
STACK
07FFh
001Fh
0010h
0000h
PASSWORD
0000h
2K x 8
SRAM DATA
03FFh
0000h
1K x 16
SRAM DATA
Figure 3. Memory Map
The memory is implemented using the Harvard architecture, with separate address spaces for program
and data memory. A pseudo-Von Neumann memory
map is also used placing ROM, application code, and
data memory into a single contiguous memory map.
The pseudo-Von Neumann memory map allows data
memory to be mapped into program space, permitting
code execution from data memory. In addition, program
memory can be mapped into data space, permitting
code constants to be accessed as data memory. Figure
3 shows the device’s memory map when executing from
program memory space. Refer to the MAX31782 User’s
Guide for memory map information when executing from
data or ROM space.
The incorporation of flash memory allows field upgrade
of the firmware. Flash memory is password protected
with a 16-word key, denying access to program memory
by unauthorized individuals.
Utility ROM
The utility ROM is a 4KWord block of internal ROM
memory that defaults to a starting address of 8000h. The
utility ROM consists of subroutines that can be called
from application software. These include the following:
• In-system programming (bootstrap loader) over JTAG
or I2C-compatible interfaces
• In-circuit debug routines
• Callable routines for in-application flash programming
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of application code, or to one of the special
routines mentioned. Routines within the utility ROM are
firmware-accessible and can be called as subroutines
by the application software. More information on the utility ROM contents is contained in the MAX31782 User’s
Guide.
11
MAX31782
System Management Microcontroller
Password
The device is programmed with a default password
prior to being shipped. The password is defined as the
16 words of physical program memory at addresses
0010h–001Fh. A single password lock bit (PWL) is
implemented in the SC register. Once a new device is
programmed, a password is defined (password is other
than all zeros or all ones) and the PWL bit is set. If the
PWL is zero, the device is deemed unprogrammed. The
password is automatically set to all ones following a
mass erase.
Stack Memory
A 16-bit, 16-level internal stack provides storage for
program return addresses and general-purpose use.
The stack is used automatically by the processor when
the CALL, RET, and RETI instructions are executed and
interrupts serviced. The stack can also be used explicitly
to store and retrieve data by using the PUSH, POP, and
POPI instructions.
On reset, the stack pointer, SP, initializes to the top of the
stack (0Fh). The CALL, PUSH, and interrupt-vectoring
operations increment SP, and then store a value at the
location pointed to by SP. The RET, RETI, POP, and POPI
operations retrieve the value at SP and then decrement SP.
Programming
The flash memory of the microcontroller can be programmed by one of three methods: in-system programming, in-application programming, and production
programming. All three methods provide great flexibility
in system design and reduce the life-cycle cost of the
embedded system.
In-System Programming
An internal bootstrap loader allows the device to be programmed over the JTAG or I2C-compatible interfaces.
As a result, system software can be upgraded in-system,
eliminating the need for a costly hardware retrofit when
software updates are required.
Programming source select (PSS) bits in the ICDF
register determine which interface is used for bootloading operation. The device supports JTAG and I2C as
an interface corresponding to 00 and 01 bits of PSS,
respectively.
In-Application Programming
The in-application programming feature allows the
microcontroller to modify its own flash program memory.
This allows on-the-fly software updates in mission-critical
12
applications that cannot afford downtime. Alternatively, it
allows the application to develop custom loader software
that can operate under the control of the application software. The utility ROM contains firmware-accessible flash
programming functions that erase and program flash
memory. These functions are described in detail in the
MAX31782 User’s Guide.
System Timing
The device generates its 4MHz instruction clock (MOSC)
internally using a ring oscillator. On power-up, the output
of the oscillator (which cannot be accessed externally) is
disabled until VDD rises above VBO. Once this threshold
is reached, 1000 cycles are counted (~ 250Fs) and then
the output is enabled, clocking the device.
System Reset
The device features several sources that can be used to
reset the device.
Power-On Reset
An internal power-on-reset (POR) circuit is used to
enhance system reliability. This circuit forces the device
to perform a POR whenever a rising voltage on VDD
climbs above VPOR. When this happens the following
events occur:
• All registers and circuits enter their reset state
• The POR flag (WDCN.7) is set to indicate the source
of the reset
• Code execution begins at location 8000h when the
reset condition is released
Brownout Detect/Reset
The device features a brownout-detect/reset function.
Whenever the power monitor detects a brownout condition (when VDD < VBO), it immediately issues a reset
and stays in that state as long as VDD remains below
VBO. Once VDD voltage rises above VBO, the device
waits for tSU:MOSC before returning to normal operation, also referred to as CPU state. If a brownout occurs
during tSU:MOSC, it again goes back to the brownout
state. Otherwise, it enters into CPU state. In CPU state,
the brownout detector is also enabled. On power-up,
the device always enters into brownout state first and
then follows the previously mentioned sequence. The
reset issued by brownout is the same as POR. Whatever
action happens on POR also happens on brownout
reset. All the registers that are cleared on POR are also
cleared on brownout reset.
System Management Microcontroller
CKCN.
SVM.
SVM.
STOP
SVMEN
SVMSTOP
0
0
X
0
1
X
1
0
X
LDO
INTERNAL
BROWNOUT
SVM
LDO (1.8V)
(1.8V)
OSCILLATOR
DETECT
MONITOR
MONITOR
On
On
On
On
Off
On
On
On
On
On
On
On
Off
On
On
On
Off
On
CPU
POWER
LDO
MODE
(2.5V)
On/Off
CPU Mode
On
On/Off
CPU Mode
On
Off
Stop Mode
On
ADC
1
1
0
Off
On
On
On
Off
On
Off
Stop Mode
On
1
1
1
Off
On
On
On
On
On
Off
Stop Mode
On
Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution.
The watchdog timer is a hardware timer designed to
be periodically reset by the application software. If the
software operates correctly, the timer is reset before it
reaches its maximum count. However, if undesirable
code execution prevents a reset of the watchdog timer,
the timer reaches its maximum count and resets the
processor.
The watchdog timer is controlled through 2 bits in the
WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
ranging from 212 to 221 system clock (MOSC) periods
(1.024ms to 0.524s). The watchdog interrupt occurs at
the end of this timeout period, which is 512 MOSC clock
periods, or 128µs, before the reset. The reset generated
by the watchdog timer lasts for four system clock cycles,
which is 1µs. Software can determine if a watchdog time
caused a reset by checking the watchdog timer reset
flag (WTRF) in the WDCN register. Execution resumes at
location 8000h following a watchdog timer reset.
External Reset
Asserting the RST pin low causes the device to enter the
reset state. The external reset function is described in
the MAX31782 User’s Guide. Execution resumes at location 8000h after the RST pin is released.
Internal System Reset
In I2C bootload mode, the host can issue a BBh command to reset the communicating device using an I2C
slave address of 34h. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1).
Power Modes
The device supports two modes of operation: CPU mode
and stop mode. The device enters stop mode state after
a CPU STOP (CKCN.STOP) is asserted. On entering stop
mode, the digital core is inactive as its clock is turned
off. All the analog circuits, except ADC (including SVM,
LDOs, and monitor circuits), are still active. Stop mode
is exited by any of the following: an external interrupt on
port 6, an I2C START interrupt, an SVM interrupt, or an
external reset. For one of the mentioned interrupts to get
the device out of stop mode, it must be enabled. The
system returns to CPU mode within 10 system clocks.
If an interrupt causes the system to come out of stop
mode, the program execution starts from the point where
stop mode was asserted. However, if an external reset is
used to come out of stop mode, the program execution
begins from ORG (starting point). Table 1 explains the
state of analog/digital circuits during different modes.
Register Set
Most functions of the device are controlled by sets of
registers. These registers provide a working space for
memory operations as well as configuring and addressing peripheral registers on the device. Registers are
divided into two major types: system registers (SPRs)
and peripheral registers (SFRs). The common register
set, also known as the system registers, includes the
ALU, accumulator registers, data pointers, interrupt
vectors and control, and stack pointer. The peripheral
registers define additional functionality and the functionality is broken up into discrete modules. Both the system
registers and the peripheral registers are illustrated in
detail in the MAX31782 User’s Guide.
13
MAX31782
Table 1. Power Modes
MAX31782
System Management Microcontroller
Hardware Multiplier
The hardware multiplier (a multiply-accumulate, or MAC
module) is a very powerful tool, especially for applications that require heavy calculations. This multiplier
can execute the multiply, multiply-negate, or multiplyaccumulate, multiply-subtract operation for signed or
unsigned operands in a single machine cycle, and even
faster for special cases. The MAC module uses eight
SFRs, mapped as register 0h–07h in module M5.
System Interrupts
Multiple interrupt sources are available to respond to
internal and external events. The MAXQ20 architecture
uses a single interrupt vector (IV) and single interruptservice routine (ISR) design. For maximum flexibility,
interrupts can be enabled globally, individually, or by
module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled
at the local, module, or global level. Interrupt flags must
be cleared within the firmware-interrupt routine to avoid
repeated interrupts from the same source. Application
software must ensure a delay between the write to the
flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition.
Asynchronous interrupt flags require a one-instruction
delay and synchronous interrupt flags require a twoinstruction delay. When an enabled interrupt is detected,
execution jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or
power-up, so if it is not changed to a different address,
application firmware must determine whether a jump to
0000h came from a reset or interrupt source.
Once control has been transferred to the ISR, the
Interrupt Identification register (IIR) can be used to determine if a system register or peripheral register was the
source of the interrupt. In addition to IIR, MIIR registers
are implemented to indicate which particular function
under a peripheral module has caused the interrupt. The
device contains six peripheral modules, M0–M5. An MIIR
register is implemented under each module. The MIIR
registers are 16-bit read-only registers and all of them
default to all 0 on system reset. Once the module that
causes the interrupt is singled out, it can then be interrogated for the specific interrupt source and software
can take appropriate action. Interrupts are evaluated
by application code allowing the definition of a unique
interrupt priority scheme for each application. Interrupt
sources are available from the watchdog timer, the ADC,
the TACH.n pins, the programmable timer/counter, the
14
I2C-compatible master and slave interface, the SVM, and
the port 6 I/O pins.
Programmable Timer/Counter
The device features a general-purpose programmable
timer/counter commonly referred to as a Timer B module. The specification for this timer/counter block is the
same as the Timer B specification. There are four registers associated with this timer/counter block: TB0CN
(control register), TB0V (value register), TB0C (compare
register), and TB0R (capture/reload value register). The
timer/counter has two pins, TBA and TBB, that are multiplexed with pins P6.4 and P6.2, respectively. When TBA
or TBB is enabled, the corresponding pin functions as
a timer/counter pin instead of a GPIO. See the I/O Port
section for more details. Detailed information regarding
the timer/counter block can be found in the MAX31782
User’s Guide.
I/O Port
The device includes a simple input/output (I/O) data port,
port 6. Pins P6.0–P6.4 are primary GPIO pins with alternate functions. Each pin is multiplexed with at least one
special function, such as interrupts, timer/counter I/O
pins, or JTAG pins. Table 2 summarizes the functionality
of the I/O pins. Figure 4 shows a block diagram of the
I/O port.
Port 6 pins have Schmitt trigger receivers and full CMOS
output drivers, and can support alternate functions. The
port is accessed through six SFRs (PO6, PI6, PD6, EIE6,
EIF6, and EIES6) in module 1 and each pin can be individually configured. The pin is either high impedance or
a weak pullup when defined as an input, dependent on
the state of the corresponding bit in the output register.
In addition, each pin can function as external interrupt
with individual enable, flag, and active edge selection,
when programmed as input.
On power-up, pins P6.0–P6.3 default to JTAG. Clearing
SC.TAP to 0 (1 is the power-up state) configures them as
GPIO. Setting EIE6.n (n = 0–4, 6, 7) to 1 configures P6.n
to an interrupt.
Pins P6.2 and P6.4 have special functions that are the
timer/counter’s TBB and TBA pins, respectively. When
TBB or TBA or both are enabled, P6.2 or P6.4 or both
are used as their special functions. P6.2 and P6.4 are
independent when used as timer/counter pins, i.e., when
either of them is used as a timer/counter pin, the other
can still be used as GPIO if the corresponding special
function is not enabled.
System Management Microcontroller
PORT INDEX
PRIMARY
FUNCTION
ALTERNATE
FUNCTION
INTERRUPTS
TAP (JTAG)
RESET STATE
P6.0
GPIO, P6.0
—
INT0
TCK
TCK
P6.1
GPIO, P6.1
—
INT1
TDI
TDI
P6.2
GPIO, P6.2
Timer B TBB Pin
INT2
TMS
TMS
P6.3
GPIO, P6.3
—
INT3
TDO
TDO
P6.4
GPIO, P6.4
Timer B TBA Pin
INT4
—
GPIO input with
weak pullup
MAX31782
Table 2. I/O Port Pins
VDD
I/O PAD
WEAK
MUX
PD6.n
SF DIRECTION
MAX31782
VDD
SF ENABLE
MUX
PO6.n
SF OUTPUT
P6.n
PI6.n OR SF INPUT
FLAG
INTERRUPT
FLAG
DETECT
CIRCUIT
EIE6.n
EIES6.n
n = 0−4
Figure 4. Port 6 I/O Block Diagram
PWM Outputs
The device provides six independent PWM outputs. Each
PWM output is associated with four SFRs: PWMCNn,
PWMVn, PWMRn, and PWMCn, where n = 0–5 is the
channel number. The PWM clock is derived from the
system clock with a division ratio defined by PWMCNn.
The PWMCNn register also enables/disables the PWM
output and selects the PWM polarity. The user can set
the frequency and the duty cycle of each PWM output
individually by configuring the corresponding PWMRn
register and the PWMCn register, respectively.
When the PWM output functionality of a PWM.n pin is
disabled, that pin can be used as a GPIO. When used
as GPIO pins, PWM.n pins are accessed as Port 1 and
through three SFRs: PO1, PI1, and PD1. Each PWM.n pin
can be independently configured, and can be defined
as an input with weak pullup, an input without pullup, or
an output.
15
MAX31782
System Management Microcontroller
Tachometer Inputs
The device provides six pins for reading fan tachometer
pulses. Each TACH.n pin functions independently and is
associated with three SFRs: TACHCNn (the control register), TACHVn (the timer value register), and TACHRn
(the timer capture register), where n = 0–5 is the channel
number.
There is an internal timer for each TACH.n pin. The clock
for the TACH.n timer is derived from the system clock
with a division ratio defined by TACHCNn. The TACH.n
timer, when initially enabled, begins counting up from the
TACHVn value and upon overflow subsequently continues counting from 0000h to the FFFFh overflow, i.e., rolls
over from FFFFh to 0000h if left enabled and running.
If the capture function is enabled by configuring the
TACHCNn register, a 1-to-0 transition on the prescaled
tachometer pulses causes the value in the TACHVn register to be transferred into the TACHRn register and set
the external trigger flag. Upon capture, TACHVn reloads
0000h and continues counting. The user can calculate
the tachometer pulse period and the fan speed by reading the TACHRn register.
When the tachometer input functionality of a TACH.n
pin is disabled, that pin can be used as a GPIO. When
used as GPIO pins, TACH.n pins are accessed as port
2 and through three SFRs: PO2, PI2, and PD2. Each
TACH.n pin can be independently configured, and can
be defined as an input with weak pullup, an input without
pullup, or an output.
I2C-Compatible Interface Modules
The device provides two independent I2C-compatible
interfaces; one is a master and the other is a slave.
I2C-Compatible Master Interface
The device features an internal I2C-comaptible master interface for communication with a wide variety of
external I2C devices. The I2C-compatible master bus is
a bidirectional bus using two bus lines, the serial-data
line (MSDA) and the serial-clock line (MSCL). For the
I2C-compatible master, the device has ownership of the
I2C bus, and drives the clock and generates the START
and STOP signals. This allows the device to send data
to a slave or receive data from a slave as required. Both
the MSDA and MSCL lines must be driven as open-drain
outputs. External pullup resistors are required to pull the
lines to a logic-high state.
When the I2C-compatible master interface is disabled,
MSDA and MSCL can be used as GPIO pins. When used
16
as GPIO pins, MSDA and MSCL can be used as pins
P2.7 and P2.6, respectively, and are accessed through
three SFRs: PO2, PI2, and PD2. Because these pins are
open drain, external pullups are required to realize a
logic-high.
I2C-Compatible Slave Interface
The device also features an internal I2C-comaptible slave
interface for communication with a host. Furthermore, the
device can be in-system programmed (bootloaded)
through the I2C-compatible slave interface. For the
I2C-compatible slave interface, the device relies on an
externally generated clock to drive SCL and responds
to data and commands only when requested by the I2C
master device.
SMBus Timeout
Both the I2C-compatible master and slave interfaces can
work in SMBus-compatible mode for communication with
other SMBus devices. To achieve this, a 30ms timer has
been implemented on the I2C-compatible slave interface
to make the interface SMBus compatible. The purpose
of this timer is to issue a timeout interrupt and thus the
firmware can reset the I2C-compatible slave interface
when the SCL is held low for longer than 30ms. The timer
only starts when none of the following conditions is true:
• The I2C-compatible slave interface is in the idle state
and there is no communication on the bus.
• The I2C-compatible slave interface is not working in
SMBus-compatible mode.
• The SCL logic level is high.
• The I2C-compatible slave interface is disabled.
When a timeout occurs, the timeout bit is set and an
interrupt is generated, if enabled. If a timeout interrupt is
generated, the firmware disables and reenables the I2Ccompatible slave interface. After this process, the SCL
and SDA pins are set to high impedance. All the relevant
I2C slave SFRs should be reloaded by firmware.
Analog-to-Digital Converter (ADC)
The device contains a 12-bit analog-to-digital converter
(ADC) with a 7-input mux (Figure 5). The mux selects the
ADC input from six external channels and one internal
channel. The six external channels can operate in fully
differential voltage mode or in single-ended voltage
mode. In addition, any of the six external channels can
be configured to measure the temperature of an external
diode. The internal channel is used exclusively to measure the die temperature. The ADC is controlled by SFR
registers.
System Management Microcontroller
The six external channels can be individually configured
to operate in external temperature mode. In external temperature mode, current is forced into an external diode
that is connected between user-specified channel pins.
The diode temperature is obtained by measuring the
diode voltages at multiple bias currents. The device features a 3-point series resistance-cancellation algorithm
to provide high-temperature measurement accuracy.
The ADC is able to measure the external diode temperature immune to the loop resistance. For both external
and internal temperature measurements, the internal reference is automatically selected and the full-scale (FS)
value is fixed at 1.225V. The temperature measurement
resolution is 0.125NC.
When the external channels are configured to operate in
voltage mode, the voltage applied on the corresponding channel (differential or single-ended) is converted
to a digital readout. In voltage mode, the reference can
be either internal or external. If the internal reference is
used, the FS can be set to 1.225V or 5.5V. These FS
values can be trimmed by modifying the associated registers (ADCG1 and ADCG5), respectively.
In voltage mode, an ADC conversion takes 34 ADCCLK
cycles to complete. The ADCCLK is derived from the
system clock with division ratio defined by the ADC
Control register. The fastest ADC sampling rate is
SYSCLK/544. With a 4MHz system clock, this is theoretically equivalent to 7.35ksps. In applications where
extending the acquisition time is desired, the sample can
be acquired over a prolonged period determined by the
ADC Control register.
The ADC has eight configuration registers. Each channel
can have its own configuration, such as differential mode
select, data alignment select, acquisition extension
enable, ADC reference select, and external temperature
mode select, etc. The ADC also has sixteen 13-bit circular data buffers for conversion result storage. The ADC
data available interrupt flag (ADDAI) can be configured
to trigger an interrupt following a predetermined number
of samples. Once set, ADDAI can be cleared by software or at the start of a conversion process.
When the device is put into stop mode, any in-progress
ADC conversion is aborted and the ADC start conversion bit (ADCONV) is reset to 0. The ADC is shut down
completely to conserve power. On exiting stop mode,
the ADC waits on ADCONV = 1. When ADCONV is set
to 1, it counts 20 ADCCLK cycles before acquisition
commences.
ADCG1
INTERNAL
ADCG5 REFERENCE
EXTERNAL
REFERENCE
AD0P
AD0N
VOLTAGE
OFFSET
AD5P
MUX
AD5N
SCALER FOR
TEMPERATURE
SENSING CHANNELS
INTERNAL
CHANNEL
12-BIT ADC CORE
TEMPERATURE
OFFSET
ADC DATA
MAX31782
Figure 5. ADC Block Diagram
17
MAX31782
The ADC can be set up to continuously poll the input
channels (continuous-sequence mode) or run a short
burst of conversions and enter a shutdown mode to conserve power (single-sequence mode).
MAX31782
System Management Microcontroller
In-Circuit Debug
Embedded debugging capability is available through
the JTAG-compatible test access port (TAP). Embedded
debug hardware and embedded ROM firmware provide
in-circuit debugging capability to the user application,
eliminating the need for an expensive in-circuit emulator.
Figure 6 shows a block diagram of the in-circuit debugger. The in-circuit debug features include the following:
Applications Information
Power-Supply Decoupling
• Hardware debug engine
To achieve the best results when using the device,
decouple the VDD power supply with a 0.1FF capacitor.
Use a high-quality, ceramic, surface-mount capacitor
if possible. Surface-mount components minimize lead
inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency
response for decoupling applications.
• Set of registers able to set breakpoints on register,
code, or data accesses (ICDA, ICDB, ICDC, ICDD,
ICDF, ICDT0, and ICDT1)
Decouple REG25 and REG18 using 1FF and 10nF
capacitors (one each per output). Note: Do not use
either of these pins for external circuitry.
• Set of debug service routines stored in the utility ROM
Additional Documentation
The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug
engine can monitor internal activities and interact with
selected internal registers while the CPU is executing
user code. Collectively, the hardware and software
features allow two basic modes of in-circuit debugging:
background and debug.
Designers must have four documents to fully use all
the features of this device. This data sheet contains pin
descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published
specifications. The user’s guides offer detailed information
about device features and operation. The following documents can be downloaded from www.maxim-ic.com.
Background mode allows the host to configure and set
up the in-circuit debugger while the CPU continues to
execute the application software at full speed. Debug
mode can be invoked from background mode.
• The MAX31782 data sheet, which contains electrical/
timing specifications and pin descriptions.
Debug mode allows the debug engine to take control of
the CPU, providing read/write access to internal registers and memory, and single-step trace operation.
• The MAX31782 User’s Guide, which contains detailed
information on core features and operation, including
programming.
• The MAX31782 revision-specific
(www.maxim-ic.com/errata).
errata
sheet
___________________Development and
Technical Support
MAX31782
Maxim and third-party suppliers provide a variety of
highly versatile, affordably priced development tools for
this microcontroller, including the following:
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
• Compilers (C and assembly)
• In-circuit debugger
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
Figure 6. In-Circuit Debugger
18
CONTROL
BREAKPOINT
ADDRESS
DATA
• Integrated development environments (IDEs)
• Serial-to-JTAG converters for programming and
debugging
• USB-to-JTAG converters for programming and
debugging
Technical support is available through email at
[email protected].
System Management Microcontroller
VIN
IN
OUT
TO LOAD
POWER SUPPLY
TRIM
EN
MSDA
MSCL
DS75
I2C TEMP SENSOR
MAX31782
3.3V
VDD
VSS (3)
SDA
SCL
PWM.5
PWM.4
PWM.3
PWM.2
PWM.1
PWM.0
PWM
FOR D/A;
OTHER
3.3V
V4-WIRE FAN
3.3V
TO HOST µP
RST
REG18
TACH.5
TACH.4
TACH.3
TACH.2
TACH.1
TACH.0
REG25
PWM
TACH
TACH/TIMER
INPUTS OR GPIO
AD5P
AD5N
REMOTE TEMPERATURE
SENSOR
AD4P
GPIO/SPECIAL FUNCTIONS
P6.4/TBA
P6.3/TDO
P6.2/TMS/TBB
P6.1/TDI
P6.0/TCK
AD4N
AD3P
AD3N
AD2P
AD2N
AD1P
AD1N
AD0P
AD0N
ADDITIONAL ADC
CHANNELS FOR MONITORING
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
40 TQFN-EP
T4066+2
21-0141
90-0053
19
MAX31782
Typical Operating Circuit
MAX31782
System Management Microcontroller
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/10
Initial release
1
11/11
Changed the lead temperature and added the ADxN to VSS voltage range and
continuous power dissipation numbers to the Absolute Maximum Ratings section;
updated the VI2C_IH, VI2C_IL conditions, changed the VIL(MIN) number, and
removed the VIH1, VIL1 parameters in the Recommended Operating Conditions
table; updated the VOL, VOH parameters and tCONV_V(TYP) and INL(MAX) numbers
in the DC Electrical Characteristics table
2, 3
2
1/12
Added new Note 7 to the INL parameter and removed the DNL parameter in the DC
Electrical Characteristics table; added the Typical Operating Characteristics section
3, 5, 6
DESCRIPTION
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
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2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.