IDT74FCT163501/A/C 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER Integrated Device Technology, Inc. FEATURES: high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similiar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163501/A/C have series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors. • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP • Extended commercial range of -40°C to +85°C • VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range • CMOS power levels (0.4µW typ. static) • Rail-to-Rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components DESCRIPTION: The FCT163501/A/C 18-bit registered transceivers are built using advanced dual metal CMOS technology. These FUNCTIONAL BLOCK DIAGRAM OEAB CLKBA LEBA OEBA CLKAB LEAB A1 C C D D B1 C C D D TO 17 OTHER CHANNELS 2776 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. AUGUST 1996 8.6 DSC-2776/4 1 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION PIN CONFIGURATIONS Pin Names Description OEAB A-to-B Output Enable Input OEAB 1 56 GND OEBA B-to-A Output Enable Input (Active LOW) LEAB 2 55 CLKAB LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or A-to-B 3-State Outputs A1 3 54 B1 GND 4 53 GND A2 5 52 B2 A3 6 51 B3 VCC 7 50 VCC A4 8 49 B4 A5 9 48 B5 A6 10 47 B6 GND 11 46 GND A7 12 45 B7 A8 13 44 B8 A9 14 B9 A10 15 SO56-1 43 SO56-2 SO56-3 42 A11 16 41 2776 tbl 01 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM(2) TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature I OUT DC Output Current VTERM(3) VTERM(4) B10 B11 Max. –0.5 to +4.6 Unit V –0.5 to +7.0 V –0.5 to VCC + 0.5 –65 to +150 V °C –60 to +60 mA 2776 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals. A12 17 40 B12 GND 18 39 GND A13 19 38 B13 A14 20 37 B14 A15 21 36 B15 VCC 22 35 VCC A16 23 34 B16 A17 24 33 B17 GND 25 32 GND A18 26 31 B18 L X X OEBA 27 30 CLKBA H H X L L GND H H X H H H L ↑ L L H L ↑ H H H L L X B(2) H L H X B(3) LEBA 28 29 FUNCTION TABLE(1,4) OEAB SSOP/ TSSOP/TVSOP TOP VIEW 2776 drw 02 Conditions VIN = 0V Typ. 3.5 VOUT = 0V 3.5 Max. Unit 6.0 pF 8.0 Ax X Outputs Bx Z NOTES: 2776 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance ↑ = LOW-to-HIGH Transition CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Inputs LEAB CLKAB pF 2776 lnk 04 NOTE: 1. This parameter is measured at characterization but not tested. 8.6 2 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Guaranteed Logic LOW Level VI = 5.5V Input HIGH Current (I/O pins) Input LOW Current (Input pins) Parameter Input HIGH Level (Input pins) Typ.(2) — Max. 5.5 2.0 — VCC+0.5 –0.5 — 0.8 V — — ±1 µA VI = VCC — — ±1 VI = GND — — ±1 Input HIGH Level (I/O pins) VIL Input LOW Level Unit V (Input and I/O pins) II H II L Input HIGH Current (Input pins) VCC = Max. Input LOW Current (I/O pins) VI = GND — — ±1 — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA 90 200 mA V High Impedance Output Current I OZL (3-State Output pins) VIK Clamp Diode Voltage VCC = Min., IIN = –18mA I ODH Output HIGH Current VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) I ODL Output LOW Current VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) 50 VOH Output HIGH Voltage VOL Output LOW Voltage I OS Short Circuit Current(4) VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current VCC = Max. VO = V CC I OZH µA VCC = Min. I OH = –0.1mA VCC– 0.2 — — VIN = VIH or V IL I OH = –3mA 2.4 3.0 — VCC = 3.0V VIN = VIH or V IL VCC = Min. I OH = –8mA 2.4 (5) 3.0 — I OL = 0.1mA — — 0.2 VIN = VIH or V IL I OL = 16mA — 0.2 0.4 I OL = 24mA — 0.3 0.55 VCC = 3.0V I OL = 24mA VIN = VIH or V IL VCC = Max., VO = GND(3) — 0.3 0.50 –60 –135 –240 mA — 150 — mV — 0.1 10 µA — VCC = Max., VIN = GND or VCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC –0.6V at rated current. 8.6 V 2776 lnk 05 3 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) VCC = Max. Test Conditions(1) VIN = VCC – 0.6V(3) Min. — Typ.(2) 2.0 Max. 30 Unit µA VCC = Max. Outputs Open OEAB = OEBA = VCC or GND 50% Duty Cycle One Input Toggling VIN = VCC VIN = GND — 60 100 µA/ MHz VCC = Max. VIN = VCC — 0.6 1.0 mA Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND fi = 5MHz 50% Duty Cycle VIN = GND VIN = VCC –0.6V VIN = GND — 0.6 1.0 VIN = VCC VIN = GND — 3.0 5.0 (5) VIN = VCC –0.6V VIN = GND — 3.0 5.3 (5) One Bit Toggling VCC = Max. Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = VCC LEAB = GND fi = 2.5MHz 50% Duty Cycle Eighteen Bits Toggling NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 8.6 2776 tbl 08 4 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4) FCT163501 Condition(1) Min.(2) CLKAB or CLKBA frequency CL = 50pF Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA tH Hold Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA tSU Set-up Time Clock HIGH or LOW LOW Ax to LEAB, Clock Bx to LEBA HIGH tH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA tW LEAB or LEBA Pulse Width HIGH(5) tW CLKAB or CLKBA Pulse Width HIGH or LOW(5) tSK(o) Output Skew (3) RL = 500Ω Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Parameter FCT163501A FCT163501C Max. Min.(2) Max. Min.(2) Max. Unit — 100 — 150 — 150 MHz 1.5 6.5 1.5 5.1 1.5 4.6 ns 1.5 7.5 1.5 5.6 1.5 5.3 ns 1.5 8.0 1.5 5.6 1.5 5.3 ns 1.5 8.0 1.5 6.0 1.5 5.6 ns 1.5 7.5 1.5 5.6 1.5 5.2 ns 4.0 — 3.0 — 3.0 — ns 0 — 0 — 0 — ns 4.0 — 3.0 — 3.0 — ns 1.5 — 1.5 — 1.5 — ns 1.5 — 1.5 — 1.5 — ns 3.0 — 3.0 — 3.0 — ns 3.0 — 3.0 — 3.0 — ns — 0.5 — 0.5 — 0.5 ns 2776 tbl 07 NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design. 4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 5. This parameter is guaranteed but not tested. 8.6 5 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS 6V ← V CC 500Ω V V IN Pulse Generator Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Open GND OUT D.U.T. 50pF R T C Switch 6V GND Open 2776 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω L 2776 drw 05 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2776 drw 07 2776 drw 06 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V tPZL VOH 1.5V VOL OUTPUT NORMALLY SWITCH 6V LOW tPZH 3V 1.5V 0V OUTPUT NORMALLY HIGH 2776 drw 08 SWITCH GND 0V tPLZ 3V 3V 1.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V 0V 2776 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. If VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 8.6 6 IDT74FCT163501/A/C 3.3V 18-BIT REGISTERED TRANSCEIVER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT FCT XXXX X Device Temperature Type Range X Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 163501 163501A Non-Inverting 18-Bit Registered Transceiver Fast Non-Inverting 18-Bit Registered Transceiver 74 -40°C to +85°C 2776 drw 10 8.6 7